X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fbnxt%2Ftf_core%2Ftf_device_p58.c;h=50facce1557dc2c540fd23a7a43f194849e86361;hb=05b405d581486651305551a9f7295f40388d95db;hp=6cef1d5ba5e14107d2d087404e138e95d1f00fcc;hpb=539931eab3a5f81adaaac583e792ac1e4237db20;p=dpdk.git diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index 6cef1d5ba5..50facce155 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -58,25 +58,11 @@ const char *tf_resource_str_p58[CFA_RESOURCE_TYPE_P58_LAST + 1] = { */ static int tf_dev_p58_get_max_types(struct tf *tfp, - uint16_t *max_types) + uint16_t *max_types) { - struct tf_session *tfs; - struct tf_dev_info *dev; - int rc; - if (max_types == NULL || tfp == NULL) return -EINVAL; - /* Retrieve the session information */ - rc = tf_session_get_session(tfp, &tfs); - if (rc) - return rc; - - /* Retrieve the device information */ - rc = tf_session_get_device(tfs, &dev); - if (rc) - return rc; - *max_types = CFA_RESOURCE_TYPE_P58_LAST + 1; return 0; @@ -137,15 +123,14 @@ tf_dev_p58_get_tcam_slice_info(struct tf *tfp __rte_unused, uint16_t key_sz, uint16_t *num_slices_per_row) { -#define CFA_P58_WC_TCAM_SLICES_PER_ROW 2 -#define CFA_P58_WC_TCAM_SLICE_SIZE 12 +#define CFA_P58_WC_TCAM_SLICES_PER_ROW 1 +#define CFA_P58_WC_TCAM_SLICE_SIZE 24 if (type == TF_TCAM_TBL_TYPE_WC_TCAM) { + /* only support single slice key size now */ *num_slices_per_row = CFA_P58_WC_TCAM_SLICES_PER_ROW; if (key_sz > *num_slices_per_row * CFA_P58_WC_TCAM_SLICE_SIZE) return -ENOTSUP; - - *num_slices_per_row = 1; } else { /* for other type of tcam */ *num_slices_per_row = 1; } @@ -153,46 +138,85 @@ tf_dev_p58_get_tcam_slice_info(struct tf *tfp __rte_unused, return 0; } -static int -tf_dev_p58_map_parif(struct tf *tfp __rte_unused, - uint16_t parif_bitmask, - uint16_t pf, - uint8_t *data, - uint8_t *mask, - uint16_t sz_in_bytes) +static int tf_dev_p58_get_mailbox(void) { - uint32_t parif_pf[2] = { 0 }; - uint32_t parif_pf_mask[2] = { 0 }; - uint32_t parif; - uint32_t shift; - - if (sz_in_bytes != sizeof(uint64_t)) - return -ENOTSUP; - - for (parif = 0; parif < TF_DEV_P58_PARIF_MAX; parif++) { - if (parif_bitmask & (1UL << parif)) { - if (parif < 8) { - shift = 4 * parif; - parif_pf_mask[0] |= TF_DEV_P58_PF_MASK << shift; - parif_pf[0] |= pf << shift; - } else { - shift = 4 * (parif - 8); - parif_pf_mask[1] |= TF_DEV_P58_PF_MASK << shift; - parif_pf[1] |= pf << shift; - } - } - } - tfp_memcpy(data, parif_pf, sz_in_bytes); - tfp_memcpy(mask, parif_pf_mask, sz_in_bytes); - - return 0; + return TF_CHIMP_MB; } -static int tf_dev_p58_get_mailbox(void) +static int tf_dev_p58_word_align(uint16_t size) { - return TF_CHIMP_MB; + return ((((size) + 63) >> 6) * 8); } + +#define TF_DEV_P58_BANK_SZ_64B 2048 +/** + * Get SRAM table information. + * + * Converts an internal RM allocated element offset to + * a user address and vice versa. + * + * [in] tfp + * Pointer to TF handle + * + * [in] type + * Truflow index table type, e.g. TF_TYPE_FULL_ACT_RECORD + * + * [in/out] base + * Pointer to the Base address of the associated SRAM bank used for + * the type of record allocated. + * + * [in/out] shift + * Pointer to the factor to be used as a multiplier to translate + * between the RM units to the user address. SRAM manages 64B entries + * Addresses must be shifted to an 8B address. + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +static int tf_dev_p58_get_sram_tbl_info(struct tf *tfp __rte_unused, + void *db, + enum tf_tbl_type type, + uint16_t *base, + uint16_t *shift) +{ + uint16_t hcapi_type; + struct tf_rm_get_hcapi_parms parms; + int rc; + + parms.rm_db = db; + parms.subtype = type; + parms.hcapi_type = &hcapi_type; + + rc = tf_rm_get_hcapi_type(&parms); + if (rc) + return rc; + + switch (hcapi_type) { + case CFA_RESOURCE_TYPE_P58_SRAM_BANK_0: + *base = 0; + *shift = 3; + break; + case CFA_RESOURCE_TYPE_P58_SRAM_BANK_1: + *base = TF_DEV_P58_BANK_SZ_64B; + *shift = 3; + break; + case CFA_RESOURCE_TYPE_P58_SRAM_BANK_2: + *base = TF_DEV_P58_BANK_SZ_64B * 2; + *shift = 3; + break; + case CFA_RESOURCE_TYPE_P58_SRAM_BANK_3: + *base = TF_DEV_P58_BANK_SZ_64B * 3; + *shift = 3; + break; + default: + *base = 0; + *shift = 0; + break; + } + return 0; +} /** * Truflow P58 device specific functions */ @@ -203,6 +227,8 @@ const struct tf_dev_ops tf_dev_ops_p58_init = { .tf_dev_alloc_ident = NULL, .tf_dev_free_ident = NULL, .tf_dev_search_ident = NULL, + .tf_dev_get_ident_resc_info = NULL, + .tf_dev_get_tbl_info = NULL, .tf_dev_alloc_ext_tbl = NULL, .tf_dev_alloc_tbl = NULL, .tf_dev_free_ext_tbl = NULL, @@ -212,15 +238,18 @@ const struct tf_dev_ops tf_dev_ops_p58_init = { .tf_dev_set_ext_tbl = NULL, .tf_dev_get_tbl = NULL, .tf_dev_get_bulk_tbl = NULL, + .tf_dev_get_tbl_resc_info = NULL, .tf_dev_alloc_tcam = NULL, .tf_dev_free_tcam = NULL, .tf_dev_alloc_search_tcam = NULL, .tf_dev_set_tcam = NULL, .tf_dev_get_tcam = NULL, + .tf_dev_get_tcam_resc_info = NULL, .tf_dev_insert_int_em_entry = NULL, .tf_dev_delete_int_em_entry = NULL, .tf_dev_insert_ext_em_entry = NULL, .tf_dev_delete_ext_em_entry = NULL, + .tf_dev_get_em_resc_info = NULL, .tf_dev_alloc_tbl_scope = NULL, .tf_dev_map_tbl_scope = NULL, .tf_dev_map_parif = NULL, @@ -230,6 +259,7 @@ const struct tf_dev_ops tf_dev_ops_p58_init = { .tf_dev_set_global_cfg = NULL, .tf_dev_get_global_cfg = NULL, .tf_dev_get_mailbox = tf_dev_p58_get_mailbox, + .tf_dev_word_align = NULL, }; /** @@ -242,6 +272,8 @@ const struct tf_dev_ops tf_dev_ops_p58 = { .tf_dev_alloc_ident = tf_ident_alloc, .tf_dev_free_ident = tf_ident_free, .tf_dev_search_ident = tf_ident_search, + .tf_dev_get_ident_resc_info = tf_ident_get_resc_info, + .tf_dev_get_tbl_info = tf_dev_p58_get_sram_tbl_info, .tf_dev_alloc_tbl = tf_tbl_alloc, .tf_dev_alloc_ext_tbl = tf_tbl_ext_alloc, .tf_dev_free_tbl = tf_tbl_free, @@ -251,22 +283,32 @@ const struct tf_dev_ops tf_dev_ops_p58 = { .tf_dev_set_ext_tbl = tf_tbl_ext_common_set, .tf_dev_get_tbl = tf_tbl_get, .tf_dev_get_bulk_tbl = tf_tbl_bulk_get, + .tf_dev_get_tbl_resc_info = tf_tbl_get_resc_info, .tf_dev_alloc_tcam = tf_tcam_alloc, .tf_dev_free_tcam = tf_tcam_free, .tf_dev_alloc_search_tcam = tf_tcam_alloc_search, .tf_dev_set_tcam = tf_tcam_set, - .tf_dev_get_tcam = NULL, + .tf_dev_get_tcam = tf_tcam_get, + .tf_dev_get_tcam_resc_info = tf_tcam_get_resc_info, .tf_dev_insert_int_em_entry = tf_em_hash_insert_int_entry, .tf_dev_delete_int_em_entry = tf_em_hash_delete_int_entry, +#if (TF_EM_ALLOC == 1) + .tf_dev_move_int_em_entry = tf_em_move_int_entry, +#else + .tf_dev_move_int_em_entry = NULL, +#endif .tf_dev_insert_ext_em_entry = NULL, .tf_dev_delete_ext_em_entry = NULL, + .tf_dev_get_em_resc_info = tf_em_get_resc_info, .tf_dev_alloc_tbl_scope = NULL, .tf_dev_map_tbl_scope = NULL, - .tf_dev_map_parif = tf_dev_p58_map_parif, + .tf_dev_map_parif = NULL, .tf_dev_free_tbl_scope = NULL, .tf_dev_set_if_tbl = tf_if_tbl_set, .tf_dev_get_if_tbl = tf_if_tbl_get, .tf_dev_set_global_cfg = tf_global_cfg_set, .tf_dev_get_global_cfg = tf_global_cfg_get, .tf_dev_get_mailbox = tf_dev_p58_get_mailbox, + .tf_dev_word_align = tf_dev_p58_word_align, + .tf_dev_cfa_key_hash = hcapi_cfa_p58_key_hash };