X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fcnxk%2Fcn9k_ethdev.c;h=d34bc6898f79534363cd1d69aa7be0feb5105ad2;hb=28968ad1d39260678e7e26a2901a396a7fb34351;hp=994fdb7c3befb723fdeda3e229c13dcb2073cf3e;hpb=5a6ce511b1f306eb915d75b69286d980d58e0e45;p=dpdk.git diff --git a/drivers/net/cnxk/cn9k_ethdev.c b/drivers/net/cnxk/cn9k_ethdev.c index 994fdb7c3b..d34bc6898f 100644 --- a/drivers/net/cnxk/cn9k_ethdev.c +++ b/drivers/net/cnxk/cn9k_ethdev.c @@ -15,27 +15,30 @@ nix_rx_offload_flags(struct rte_eth_dev *eth_dev) struct rte_eth_rxmode *rxmode = &conf->rxmode; uint16_t flags = 0; - if (rxmode->mq_mode == ETH_MQ_RX_RSS && - (dev->rx_offloads & DEV_RX_OFFLOAD_RSS_HASH)) + if (rxmode->mq_mode == RTE_ETH_MQ_RX_RSS && + (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_RSS_HASH)) flags |= NIX_RX_OFFLOAD_RSS_F; if (dev->rx_offloads & - (DEV_RX_OFFLOAD_TCP_CKSUM | DEV_RX_OFFLOAD_UDP_CKSUM)) + (RTE_ETH_RX_OFFLOAD_TCP_CKSUM | RTE_ETH_RX_OFFLOAD_UDP_CKSUM)) flags |= NIX_RX_OFFLOAD_CHECKSUM_F; if (dev->rx_offloads & - (DEV_RX_OFFLOAD_IPV4_CKSUM | DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM)) + (RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM)) flags |= NIX_RX_OFFLOAD_CHECKSUM_F; - if (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER) + if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SCATTER) flags |= NIX_RX_MULTI_SEG_F; - if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP)) + if ((dev->rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)) flags |= NIX_RX_OFFLOAD_TSTAMP_F; if (!dev->ptype_disable) flags |= NIX_RX_OFFLOAD_PTYPE_F; + if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) + flags |= NIX_RX_OFFLOAD_SECURITY_F; + return flags; } @@ -47,15 +50,15 @@ nix_tx_offload_flags(struct rte_eth_dev *eth_dev) uint16_t flags = 0; /* Fastpath is dependent on these enums */ - RTE_BUILD_BUG_ON(PKT_TX_TCP_CKSUM != (1ULL << 52)); - RTE_BUILD_BUG_ON(PKT_TX_SCTP_CKSUM != (2ULL << 52)); - RTE_BUILD_BUG_ON(PKT_TX_UDP_CKSUM != (3ULL << 52)); - RTE_BUILD_BUG_ON(PKT_TX_IP_CKSUM != (1ULL << 54)); - RTE_BUILD_BUG_ON(PKT_TX_IPV4 != (1ULL << 55)); - RTE_BUILD_BUG_ON(PKT_TX_OUTER_IP_CKSUM != (1ULL << 58)); - RTE_BUILD_BUG_ON(PKT_TX_OUTER_IPV4 != (1ULL << 59)); - RTE_BUILD_BUG_ON(PKT_TX_OUTER_IPV6 != (1ULL << 60)); - RTE_BUILD_BUG_ON(PKT_TX_OUTER_UDP_CKSUM != (1ULL << 41)); + RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_TCP_CKSUM != (1ULL << 52)); + RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_SCTP_CKSUM != (2ULL << 52)); + RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_UDP_CKSUM != (3ULL << 52)); + RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_IP_CKSUM != (1ULL << 54)); + RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_IPV4 != (1ULL << 55)); + RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_OUTER_IP_CKSUM != (1ULL << 58)); + RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_OUTER_IPV4 != (1ULL << 59)); + RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_OUTER_IPV6 != (1ULL << 60)); + RTE_BUILD_BUG_ON(RTE_MBUF_F_TX_OUTER_UDP_CKSUM != (1ULL << 41)); RTE_BUILD_BUG_ON(RTE_MBUF_L2_LEN_BITS != 7); RTE_BUILD_BUG_ON(RTE_MBUF_L3_LEN_BITS != 9); RTE_BUILD_BUG_ON(RTE_MBUF_OUTL2_LEN_BITS != 7); @@ -69,38 +72,41 @@ nix_tx_offload_flags(struct rte_eth_dev *eth_dev) RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, tx_offload) != offsetof(struct rte_mbuf, pool) + 2 * sizeof(void *)); - if (conf & DEV_TX_OFFLOAD_VLAN_INSERT || - conf & DEV_TX_OFFLOAD_QINQ_INSERT) + if (conf & RTE_ETH_TX_OFFLOAD_VLAN_INSERT || + conf & RTE_ETH_TX_OFFLOAD_QINQ_INSERT) flags |= NIX_TX_OFFLOAD_VLAN_QINQ_F; - if (conf & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM || - conf & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM) + if (conf & RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM || + conf & RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM) flags |= NIX_TX_OFFLOAD_OL3_OL4_CSUM_F; - if (conf & DEV_TX_OFFLOAD_IPV4_CKSUM || - conf & DEV_TX_OFFLOAD_TCP_CKSUM || - conf & DEV_TX_OFFLOAD_UDP_CKSUM || conf & DEV_TX_OFFLOAD_SCTP_CKSUM) + if (conf & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM || + conf & RTE_ETH_TX_OFFLOAD_TCP_CKSUM || + conf & RTE_ETH_TX_OFFLOAD_UDP_CKSUM || conf & RTE_ETH_TX_OFFLOAD_SCTP_CKSUM) flags |= NIX_TX_OFFLOAD_L3_L4_CSUM_F; - if (!(conf & DEV_TX_OFFLOAD_MBUF_FAST_FREE)) + if (!(conf & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE)) flags |= NIX_TX_OFFLOAD_MBUF_NOFF_F; - if (conf & DEV_TX_OFFLOAD_MULTI_SEGS) + if (conf & RTE_ETH_TX_OFFLOAD_MULTI_SEGS) flags |= NIX_TX_MULTI_SEG_F; /* Enable Inner checksum for TSO */ - if (conf & DEV_TX_OFFLOAD_TCP_TSO) + if (conf & RTE_ETH_TX_OFFLOAD_TCP_TSO) flags |= (NIX_TX_OFFLOAD_TSO_F | NIX_TX_OFFLOAD_L3_L4_CSUM_F); /* Enable Inner and Outer checksum for Tunnel TSO */ - if (conf & (DEV_TX_OFFLOAD_VXLAN_TNL_TSO | - DEV_TX_OFFLOAD_GENEVE_TNL_TSO | DEV_TX_OFFLOAD_GRE_TNL_TSO)) + if (conf & (RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO | + RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO | RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO)) flags |= (NIX_TX_OFFLOAD_TSO_F | NIX_TX_OFFLOAD_OL3_OL4_CSUM_F | NIX_TX_OFFLOAD_L3_L4_CSUM_F); - if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP)) + if ((dev->rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)) flags |= NIX_TX_OFFLOAD_TSTAMP_F; + if (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY) + flags |= NIX_TX_OFFLOAD_SECURITY_F; + return flags; } @@ -179,8 +185,10 @@ cn9k_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, const struct rte_eth_txconf *tx_conf) { struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct roc_cpt_lf *inl_lf; struct cn9k_eth_txq *txq; struct roc_nix_sq *sq; + uint16_t crypto_qid; int rc; RTE_SET_USED(socket); @@ -200,6 +208,19 @@ cn9k_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, txq->nb_sqb_bufs_adj = sq->nb_sqb_bufs_adj; txq->sqes_per_sqb_log2 = sq->sqes_per_sqb_log2; + /* Fetch CPT LF info for outbound if present */ + if (dev->outb.lf_base) { + crypto_qid = qid % dev->outb.nb_crypto_qs; + inl_lf = dev->outb.lf_base + crypto_qid; + + txq->cpt_io_addr = inl_lf->io_addr; + txq->cpt_fc = inl_lf->fc_addr; + txq->cpt_desc = inl_lf->nb_desc * 0.7; + txq->sa_base = (uint64_t)dev->outb.sa_base; + txq->sa_base |= eth_dev->data->port_id; + PLT_STATIC_ASSERT(BIT_ULL(16) == ROC_NIX_INL_SA_BASE_ALIGN); + } + nix_form_default_desc(dev, txq, qid); txq->lso_tun_fmt = dev->lso_tun_fmt; return 0; @@ -277,9 +298,9 @@ cn9k_nix_configure(struct rte_eth_dev *eth_dev) /* Platform specific checks */ if ((roc_model_is_cn96_a0() || roc_model_is_cn95_a0()) && - (txmode->offloads & DEV_TX_OFFLOAD_SCTP_CKSUM) && - ((txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) || - (txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM))) { + (txmode->offloads & RTE_ETH_TX_OFFLOAD_SCTP_CKSUM) && + ((txmode->offloads & RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM) || + (txmode->offloads & RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM))) { plt_err("Outer IP and SCTP checksum unsupported"); return -EINVAL; } @@ -309,7 +330,6 @@ nix_ptp_enable_vf(struct rte_eth_dev *eth_dev) if (nix_recalc_mtu(eth_dev)) plt_err("Failed to set MTU size for ptp"); - dev->scalar_ena = true; dev->rx_offload_flags |= NIX_RX_OFFLOAD_TSTAMP_F; /* Setting up the function pointers as per new offload flags */ @@ -466,6 +486,7 @@ nix_eth_dev_ops_override(void) cnxk_eth_dev_ops.dev_ptypes_set = cn9k_nix_ptypes_set; cnxk_eth_dev_ops.timesync_enable = cn9k_nix_timesync_enable; cnxk_eth_dev_ops.timesync_disable = cn9k_nix_timesync_disable; + cnxk_eth_dev_ops.mtr_ops_get = NULL; } static void @@ -509,6 +530,8 @@ cn9k_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev) nix_eth_dev_ops_override(); npc_flow_ops_override(); + cn9k_eth_sec_ops_override(); + /* Common probe */ rc = cnxk_nix_probe(pci_drv, pci_dev); if (rc) @@ -531,17 +554,17 @@ cn9k_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev) * TSO not supported for earlier chip revisions */ if (roc_model_is_cn96_a0() || roc_model_is_cn95_a0()) - dev->tx_offload_capa &= ~(DEV_TX_OFFLOAD_TCP_TSO | - DEV_TX_OFFLOAD_VXLAN_TNL_TSO | - DEV_TX_OFFLOAD_GENEVE_TNL_TSO | - DEV_TX_OFFLOAD_GRE_TNL_TSO); + dev->tx_offload_capa &= ~(RTE_ETH_TX_OFFLOAD_TCP_TSO | + RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO | + RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO | + RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO); /* 50G and 100G to be supported for board version C0 * and above of CN9K. */ if (roc_model_is_cn96_a0() || roc_model_is_cn95_a0()) { - dev->speed_capa &= ~(uint64_t)ETH_LINK_SPEED_50G; - dev->speed_capa &= ~(uint64_t)ETH_LINK_SPEED_100G; + dev->speed_capa &= ~(uint64_t)RTE_ETH_LINK_SPEED_50G; + dev->speed_capa &= ~(uint64_t)RTE_ETH_LINK_SPEED_100G; } dev->hwcap = 0; @@ -556,6 +579,21 @@ cn9k_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev) } static const struct rte_pci_id cn9k_pci_nix_map[] = { + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KA, PCI_DEVID_CNXK_RVU_PF), + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KB, PCI_DEVID_CNXK_RVU_PF), + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KC, PCI_DEVID_CNXK_RVU_PF), + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KD, PCI_DEVID_CNXK_RVU_PF), + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KE, PCI_DEVID_CNXK_RVU_PF), + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KA, PCI_DEVID_CNXK_RVU_VF), + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KB, PCI_DEVID_CNXK_RVU_VF), + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KC, PCI_DEVID_CNXK_RVU_VF), + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KD, PCI_DEVID_CNXK_RVU_VF), + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KE, PCI_DEVID_CNXK_RVU_VF), + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KA, PCI_DEVID_CNXK_RVU_AF_VF), + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KB, PCI_DEVID_CNXK_RVU_AF_VF), + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KC, PCI_DEVID_CNXK_RVU_AF_VF), + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KD, PCI_DEVID_CNXK_RVU_AF_VF), + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KE, PCI_DEVID_CNXK_RVU_AF_VF), { .vendor_id = 0, },