X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fcnxk%2Fcnxk_ethdev.c;h=7adab4605819b3582970980c0b2b44e911a548e4;hb=99fc1f6eefa7850089d392bc682767e75bc79259;hp=522f7ec0b4db91d4f44e8ecfcaee027cf2cc3a8a;hpb=c7c7c8ed7d47cb9fd6590d8c3f00f5d469e1c449;p=dpdk.git

diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c
index 522f7ec0b4..7adab46058 100644
--- a/drivers/net/cnxk/cnxk_ethdev.c
+++ b/drivers/net/cnxk/cnxk_ethdev.c
@@ -150,7 +150,8 @@ cnxk_nix_rxq_mbuf_setup(struct cnxk_eth_dev *dev)
 				 offsetof(struct rte_mbuf, data_off) !=
 			 6);
 	mb_def.nb_segs = 1;
-	mb_def.data_off = RTE_PKTMBUF_HEADROOM;
+	mb_def.data_off = RTE_PKTMBUF_HEADROOM +
+			  (dev->ptp_en * CNXK_NIX_TIMESYNC_RX_OFFSET);
 	mb_def.port = port_id;
 	rte_mbuf_refcnt_set(&mb_def, 1);
 
@@ -356,6 +357,18 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 	eth_dev->data->rx_queues[qid] = rxq_sp + 1;
 	eth_dev->data->rx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STOPPED;
 
+	/* Calculating delta and freq mult between PTP HI clock and tsc.
+	 * These are needed in deriving raw clock value from tsc counter.
+	 * read_clock eth op returns raw clock value.
+	 */
+	if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) || dev->ptp_en) {
+		rc = cnxk_nix_tsc_convert(dev);
+		if (rc) {
+			plt_err("Failed to calculate delta and freq mult");
+			goto rq_fini;
+		}
+	}
+
 	return 0;
 rq_fini:
 	rc |= roc_nix_rq_fini(rq);
@@ -1124,7 +1137,7 @@ cnxk_nix_dev_start(struct rte_eth_dev *eth_dev)
 	struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 	int rc, i;
 
-	if (eth_dev->data->nb_rx_queues != 0) {
+	if (eth_dev->data->nb_rx_queues != 0 && !dev->ptp_en) {
 		rc = nix_recalc_mtu(eth_dev);
 		if (rc)
 			return rc;
@@ -1169,6 +1182,25 @@ cnxk_nix_dev_start(struct rte_eth_dev *eth_dev)
 		}
 	}
 
+	/* Enable PTP if it is requested by the user or already
+	 * enabled on PF owning this VF
+	 */
+	memset(&dev->tstamp, 0, sizeof(struct cnxk_timesync_info));
+	if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) || dev->ptp_en)
+		cnxk_eth_dev_ops.timesync_enable(eth_dev);
+	else
+		cnxk_eth_dev_ops.timesync_disable(eth_dev);
+
+	if (dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) {
+		rc = rte_mbuf_dyn_rx_timestamp_register
+			(&dev->tstamp.tstamp_dynfield_offset,
+			 &dev->tstamp.rx_tstamp_dynflag);
+		if (rc != 0) {
+			plt_err("Failed to register Rx timestamp field/flag");
+			goto rx_disable;
+		}
+	}
+
 	cnxk_nix_toggle_flag_link_cfg(dev, false);
 
 	return 0;
@@ -1228,6 +1260,17 @@ struct eth_dev_ops cnxk_eth_dev_ops = {
 	.tx_done_cleanup = cnxk_nix_tx_done_cleanup,
 	.flow_ops_get = cnxk_nix_flow_ops_get,
 	.get_reg = cnxk_nix_dev_get_reg,
+	.timesync_read_rx_timestamp = cnxk_nix_timesync_read_rx_timestamp,
+	.timesync_read_tx_timestamp = cnxk_nix_timesync_read_tx_timestamp,
+	.timesync_read_time = cnxk_nix_timesync_read_time,
+	.timesync_write_time = cnxk_nix_timesync_write_time,
+	.timesync_adjust_time = cnxk_nix_timesync_adjust_time,
+	.read_clock = cnxk_nix_read_clock,
+	.reta_update = cnxk_nix_reta_update,
+	.reta_query = cnxk_nix_reta_query,
+	.rss_hash_update = cnxk_nix_rss_hash_update,
+	.rss_hash_conf_get = cnxk_nix_rss_hash_conf_get,
+	.set_mc_addr_list = cnxk_nix_mc_addr_list_configure,
 };
 
 static int
@@ -1256,6 +1299,7 @@ cnxk_eth_dev_init(struct rte_eth_dev *eth_dev)
 
 	/* Initialize base roc nix */
 	nix->pci_dev = pci_dev;
+	nix->hw_vlan_ins = true;
 	rc = roc_nix_dev_init(nix);
 	if (rc) {
 		plt_err("Failed to initialize roc nix rc=%d", rc);
@@ -1292,6 +1336,7 @@ cnxk_eth_dev_init(struct rte_eth_dev *eth_dev)
 	}
 
 	dev->max_mac_entries = max_entries;
+	dev->dmac_filter_count = 1;
 
 	/* Get mac address */
 	rc = roc_nix_npc_mac_addr_get(nix, dev->mac_addr);