X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fcxgbe%2Fbase%2Fadapter.h;h=1c7c8afe163d1163cc3d1b2092d674077c658630;hb=5b634932410ca41c2071a8d015180fd464df2fa5;hp=e98dd2182555536c264944d9c94500edc0b2d105;hpb=af44a577988bd8aeafcd7e40549187fc7c0eee15;p=dpdk.git diff --git a/drivers/net/cxgbe/base/adapter.h b/drivers/net/cxgbe/base/adapter.h index e98dd21825..1c7c8afe16 100644 --- a/drivers/net/cxgbe/base/adapter.h +++ b/drivers/net/cxgbe/base/adapter.h @@ -12,14 +12,13 @@ #include #include #include -#include +#include -#include "cxgbe_compat.h" +#include "../cxgbe_compat.h" +#include "../cxgbe_ofld.h" #include "t4_regs_values.h" -#include "cxgbe_ofld.h" enum { - MAX_ETH_QSETS = 64, /* # of Ethernet Tx/Rx queue sets */ MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ }; @@ -40,28 +39,29 @@ struct port_info { short int xact_addr_filt; /* index of exact MAC address filter */ u16 viid; /* associated virtual interface id */ - s8 mdio_addr; /* address of the PHY */ - u8 port_type; /* firmware port type */ - u8 mod_type; /* firmware module type */ u8 port_id; /* physical port ID */ u8 pidx; /* port index for this PF */ u8 tx_chan; /* associated channel */ - u8 n_rx_qsets; /* # of rx qsets */ - u8 n_tx_qsets; /* # of tx qsets */ - u8 first_qset; /* index of first qset */ + u16 n_rx_qsets; /* # of rx qsets */ + u16 n_tx_qsets; /* # of tx qsets */ + u16 first_rxqset; /* index of first rxqset */ + u16 first_txqset; /* index of first txqset */ u16 *rss; /* rss table */ u8 rss_mode; /* rss mode */ u16 rss_size; /* size of VI's RSS table slice */ u64 rss_hf; /* RSS Hash Function */ -}; -/* Enable or disable autonegotiation. If this is set to enable, - * the forced link modes above are completely ignored. - */ -#define AUTONEG_DISABLE 0x00 -#define AUTONEG_ENABLE 0x01 + /* viid fields either returned by fw + * or decoded by parsing viid by driver. + */ + u8 vin; + u8 vivld; + + u8 vi_en_rx; /* Enable/disable VI Rx */ + u8 vi_en_tx; /* Enable/disable VI Tx */ +}; enum { /* adapter flags */ FULL_INIT_DONE = (1 << 0), @@ -156,6 +156,7 @@ struct sge_eth_rx_stats { /* Ethernet rx queue statistics */ }; struct sge_eth_rxq { /* a SW Ethernet Rx queue */ + unsigned int flags; /* flags for state of the queue */ struct sge_rspq rspq; struct sge_fl fl; struct sge_eth_rx_stats stats; @@ -193,10 +194,14 @@ struct tx_sw_desc { /* SW state per Tx descriptor */ struct tx_eth_coal_desc coalesce; }; -enum { +enum cxgbe_txq_state { EQ_STOPPED = (1 << 0), }; +enum cxgbe_rxq_state { + IQ_STOPPED = (1 << 0), +}; + struct eth_coalesce { unsigned char *ptr; unsigned char type; @@ -268,8 +273,8 @@ struct sge_ctrl_txq { /* State for an SGE control Tx queue */ } __rte_cache_aligned; struct sge { - struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; - struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; + struct sge_eth_txq *ethtxq; + struct sge_eth_rxq *ethrxq; struct sge_rspq fw_evtq __rte_cache_aligned; struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; @@ -299,6 +304,14 @@ struct mbox_entry { TAILQ_HEAD(mbox_list, mbox_entry); +struct adapter_devargs { + bool keep_ovlan; + bool force_link_up; + bool tx_mode_latency; + u32 filtermode; + u32 filtermask; +}; + struct adapter { struct rte_pci_device *pdev; /* associated rte pci device */ struct rte_eth_dev *eth_dev; /* first port's rte eth device */ @@ -322,11 +335,20 @@ struct adapter { int use_unpacked_mode; /* unpacked rx mode state */ rte_spinlock_t win0_lock; + rte_spinlock_t flow_lock; /* Serialize access for rte_flow ops */ + unsigned int clipt_start; /* CLIP table start */ unsigned int clipt_end; /* CLIP table end */ + unsigned int l2t_start; /* Layer 2 table start */ + unsigned int l2t_end; /* Layer 2 table end */ struct clip_tbl *clipt; /* CLIP table */ + struct l2t_data *l2t; /* Layer 2 table */ + struct smt_data *smt; /* Source mac table */ + struct mpstcam_table *mpstcam; struct tid_info tids; /* Info used to access TID related tables */ + + struct adapter_devargs devargs; }; /** @@ -364,7 +386,7 @@ static inline void t4_os_write_unlock(rte_rwlock_t *lock) */ static inline struct port_info *ethdev2pinfo(const struct rte_eth_dev *dev) { - return (struct port_info *)dev->data->dev_private; + return dev->data->dev_private; } /** @@ -446,11 +468,7 @@ static inline uint64_t cxgbe_write_addr64(volatile void *addr, uint64_t val) */ static inline u32 t4_read_reg(struct adapter *adapter, u32 reg_addr) { - u32 val = CXGBE_READ_REG(adapter, reg_addr); - - CXGBE_DEBUG_REG(adapter, "read register 0x%x value 0x%x\n", reg_addr, - val); - return val; + return CXGBE_READ_REG(adapter, reg_addr); } /** @@ -463,8 +481,6 @@ static inline u32 t4_read_reg(struct adapter *adapter, u32 reg_addr) */ static inline void t4_write_reg(struct adapter *adapter, u32 reg_addr, u32 val) { - CXGBE_DEBUG_REG(adapter, "setting register 0x%x to 0x%x\n", reg_addr, - val); CXGBE_WRITE_REG(adapter, reg_addr, val); } @@ -479,8 +495,6 @@ static inline void t4_write_reg(struct adapter *adapter, u32 reg_addr, u32 val) static inline void t4_write_reg_relaxed(struct adapter *adapter, u32 reg_addr, u32 val) { - CXGBE_DEBUG_REG(adapter, "setting register 0x%x to 0x%x\n", reg_addr, - val); CXGBE_WRITE_REG_RELAXED(adapter, reg_addr, val); } @@ -493,11 +507,7 @@ static inline void t4_write_reg_relaxed(struct adapter *adapter, u32 reg_addr, */ static inline u64 t4_read_reg64(struct adapter *adapter, u32 reg_addr) { - u64 val = CXGBE_READ_REG64(adapter, reg_addr); - - CXGBE_DEBUG_REG(adapter, "64-bit read register %#x value %#llx\n", - reg_addr, (unsigned long long)val); - return val; + return CXGBE_READ_REG64(adapter, reg_addr); } /** @@ -511,9 +521,6 @@ static inline u64 t4_read_reg64(struct adapter *adapter, u32 reg_addr) static inline void t4_write_reg64(struct adapter *adapter, u32 reg_addr, u64 val) { - CXGBE_DEBUG_REG(adapter, "setting register %#x to %#llx\n", reg_addr, - (unsigned long long)val); - CXGBE_WRITE_REG64(adapter, reg_addr, val); } @@ -667,7 +674,7 @@ static inline void t4_os_set_hw_addr(struct adapter *adapter, int port_idx, { struct port_info *pi = adap2pinfo(adapter, port_idx); - ether_addr_copy((struct ether_addr *)hw_addr, + rte_ether_addr_copy((struct rte_ether_addr *)hw_addr, &pi->eth_dev->data->mac_addrs[0]); } @@ -788,7 +795,7 @@ void t4_free_mem(void *addr); #define t4_os_free(_ptr) t4_free_mem((_ptr)) void t4_os_portmod_changed(const struct adapter *adap, int port_id); -void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); +void t4_os_link_changed(struct adapter *adap, int port_id); void reclaim_completed_tx(struct sge_txq *q); void t4_free_sge_resources(struct adapter *adap); @@ -797,8 +804,6 @@ void t4_sge_tx_monitor_stop(struct adapter *adap); int t4_eth_xmit(struct sge_eth_txq *txq, struct rte_mbuf *mbuf, uint16_t nb_pkts); int t4_mgmt_tx(struct sge_ctrl_txq *txq, struct rte_mbuf *mbuf); -int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, - const struct pkt_gl *gl); int t4_sge_init(struct adapter *adap); int t4vf_sge_init(struct adapter *adap); int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, @@ -815,10 +820,11 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *rspq, bool fwevtq, int t4_sge_eth_txq_start(struct sge_eth_txq *txq); int t4_sge_eth_txq_stop(struct sge_eth_txq *txq); void t4_sge_eth_txq_release(struct adapter *adap, struct sge_eth_txq *txq); -int t4_sge_eth_rxq_start(struct adapter *adap, struct sge_rspq *rq); -int t4_sge_eth_rxq_stop(struct adapter *adap, struct sge_rspq *rq); +int t4_sge_eth_rxq_start(struct adapter *adap, struct sge_eth_rxq *rxq); +int t4_sge_eth_rxq_stop(struct adapter *adap, struct sge_eth_rxq *rxq); void t4_sge_eth_rxq_release(struct adapter *adap, struct sge_eth_rxq *rxq); void t4_sge_eth_clear_queues(struct port_info *pi); +void t4_sge_eth_release_queues(struct port_info *pi); int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, unsigned int cnt); int cxgbe_poll(struct sge_rspq *q, struct rte_mbuf **rx_pkts,