X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fcxgbe%2Fbase%2Fcommon.h;h=86f3dc80b8d1ffee38b9c7224039628b6a181843;hb=439009e4ef3469ff1cd68d4ec71ca922f3a6d68f;hp=8fe8e2a36b9e7ac5798beb2c8050305f86123665;hpb=e30e5407fd608b9d6d3925e8081638fd21cdd77a;p=dpdk.git

diff --git a/drivers/net/cxgbe/base/common.h b/drivers/net/cxgbe/base/common.h
index 8fe8e2a36b..86f3dc80b8 100644
--- a/drivers/net/cxgbe/base/common.h
+++ b/drivers/net/cxgbe/base/common.h
@@ -274,7 +274,6 @@ struct adapter_params {
 	struct arch_specific_params arch; /* chip specific params */
 
 	bool ulptx_memwrite_dsgl;          /* use of T5 DSGL allowed */
-	u8 fw_caps_support;		  /* 32-bit Port Capabilities */
 	u8 filter2_wr_support;            /* FW support for FILTER2_WR */
 	u32 viid_smt_extn_support:1;	  /* FW returns vin and smt index */
 	u32 max_tx_coalesce_num; /* Max # of Tx packets that can be coalesced */
@@ -282,15 +281,8 @@ struct adapter_params {
 
 /* Firmware Port Capabilities types.
  */
-typedef u16 fw_port_cap16_t;    /* 16-bit Port Capabilities integral value */
 typedef u32 fw_port_cap32_t;    /* 32-bit Port Capabilities integral value */
 
-enum fw_caps {
-	FW_CAPS_UNKNOWN = 0,    /* 0'ed out initial state */
-	FW_CAPS16       = 1,    /* old Firmware: 16-bit Port Capabilities */
-	FW_CAPS32       = 2,    /* new Firmware: 32-bit Port Capabilities */
-};
-
 struct link_config {
 	fw_port_cap32_t pcaps;          /* link capabilities */
 	fw_port_cap32_t acaps;          /* advertised capabilities */
@@ -552,5 +544,4 @@ static inline int t4_memory_rw(struct adapter *adap, int win,
 {
 	return t4_memory_rw_mtype(adap, win, mtype, maddr, len, hbuf, dir);
 }
-fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16);
 #endif /* __CHELSIO_COMMON_H */