X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fcxgbe%2Fbase%2Fcommon.h;h=892aab64b9a3e2f5e13b88bb44b1a6bd1cc705d2;hb=24c1d49ac82f35ba999d93c4d1d5ee6930259b5f;hp=c80304b243fc68b5a88cfe8151f217081cd96b3d;hpb=3a3aaabc7c77ff0101896e788fb3b3f550213b0d;p=dpdk.git diff --git a/drivers/net/cxgbe/base/common.h b/drivers/net/cxgbe/base/common.h index c80304b243..892aab64b9 100644 --- a/drivers/net/cxgbe/base/common.h +++ b/drivers/net/cxgbe/base/common.h @@ -6,7 +6,7 @@ #ifndef __CHELSIO_COMMON_H #define __CHELSIO_COMMON_H -#include "cxgbe_compat.h" +#include "../cxgbe_compat.h" #include "t4_hw.h" #include "t4vf_hw.h" #include "t4_chip_type.h" @@ -18,6 +18,9 @@ extern "C" { #define CXGBE_PAGE_SIZE RTE_PGSIZE_4K +#define T4_MEMORY_WRITE 0 +#define T4_MEMORY_READ 1 + enum { MAX_NPORTS = 4, /* max # of ports */ }; @@ -47,6 +50,8 @@ enum cc_fec { FEC_BASER_RS = 1 << 2, /* BaseR/Reed-Solomon */ }; +enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 }; + struct port_stats { u64 tx_octets; /* total # of octets in good frames */ u64 tx_frames; /* all good frames */ @@ -151,6 +156,11 @@ struct tp_params { int vnic_shift; int port_shift; int protocol_shift; + int ethertype_shift; + int macmatch_shift; + int tos_shift; + + u64 hash_filter_mask; }; struct vpd_params { @@ -202,6 +212,14 @@ struct rss_params { } u; }; +/* + * Maximum resources provisioned for a PCI PF. + */ +struct pf_resources { + unsigned int neq; /* N egress Qs */ + unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */ +}; + /* * Maximum resources provisioned for a PCI VF. */ @@ -225,6 +243,7 @@ struct adapter_params { struct pci_params pci; struct devlog_params devlog; struct rss_params rss; + struct pf_resources pfres; struct vf_resources vfres; enum pcie_memwin drv_memwin; @@ -246,11 +265,16 @@ struct adapter_params { unsigned char nports; /* # of ethernet ports */ unsigned char portvec; + unsigned char hash_filter; + enum chip_type chip; /* chip code */ struct arch_specific_params arch; /* chip specific params */ bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ u8 fw_caps_support; /* 32-bit Port Capabilities */ + u8 filter2_wr_support; /* FW support for FILTER2_WR */ + u32 viid_smt_extn_support:1; /* FW returns vin and smt index */ + u32 max_tx_coalesce_num; /* Max # of Tx packets that can be coalesced */ }; /* Firmware Port Capabilities types. @@ -309,6 +333,11 @@ static inline int is_pf4(struct adapter *adap) #define for_each_port(adapter, iter) \ for (iter = 0; iter < (adapter)->params.nports; ++iter) +static inline int is_hashfilter(const struct adapter *adap) +{ + return adap->params.hash_filter; +} + void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, unsigned int mask, unsigned int val); @@ -354,16 +383,23 @@ int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, unsigned int port, unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, unsigned int *rss_size, - unsigned int portfunc, unsigned int idstype); + unsigned int portfunc, unsigned int idstype, + u8 *vivld, u8 *vin); int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, - unsigned int *rss_size); + unsigned int *rss_size, u8 *vivild, u8 *vin); int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf, unsigned int vf, unsigned int viid); int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, int mtu, int promisc, int all_multi, int bcast, int vlanex, bool sleep_ok); +int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, + const u8 *addr, const u8 *mask, unsigned int idx, + u8 lookup_type, u8 port_id, bool sleep_ok); +int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, + const u8 *addr, const u8 *mask, unsigned int idx, + u8 lookup_type, u8 port_id, bool sleep_ok); int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, int idx, const u8 *addr, bool persist, bool add_smt); int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, @@ -451,6 +487,7 @@ void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, unsigned int nregs, unsigned int start_idx); int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); +int t4_get_pfres(struct adapter *adapter); int t4_read_flash(struct adapter *adapter, unsigned int addr, unsigned int nwords, u32 *data, int byte_oriented); int t4_flash_cfg_addr(struct adapter *adapter); @@ -489,7 +526,7 @@ void t4_read_rss_key(struct adapter *adap, u32 *key); enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid, - unsigned int qtype, u64 *pbar2_qoffset, + enum t4_bar2_qtype qtype, u64 *pbar2_qoffset, unsigned int *pbar2_qid); int t4_init_sge_params(struct adapter *adapter); @@ -502,5 +539,15 @@ void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data); int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data); int t4_seeprom_wp(struct adapter *adapter, int enable); +int t4_memory_rw_addr(struct adapter *adap, int win, + u32 addr, u32 len, void *hbuf, int dir); +int t4_memory_rw_mtype(struct adapter *adap, int win, int mtype, u32 maddr, + u32 len, void *hbuf, int dir); +static inline int t4_memory_rw(struct adapter *adap, int win, + int mtype, u32 maddr, u32 len, + void *hbuf, int dir) +{ + return t4_memory_rw_mtype(adap, win, mtype, maddr, len, hbuf, dir); +} fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16); #endif /* __CHELSIO_COMMON_H */