X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fcxgbe%2Fbase%2Ft4_regs.h;h=1100e16fe0a0574c7d4c66e97a47134d39408ad1;hb=2ac67c32837a3e47eed1a6610edd80d6a2754488;hp=cd28b593a86b57aada05eebf3dc26a7d4cc63a03;hpb=3bd122eef2cc1de8d65b5219e54f4be3affa0cc2;p=dpdk.git

diff --git a/drivers/net/cxgbe/base/t4_regs.h b/drivers/net/cxgbe/base/t4_regs.h
index cd28b593a8..1100e16fe0 100644
--- a/drivers/net/cxgbe/base/t4_regs.h
+++ b/drivers/net/cxgbe/base/t4_regs.h
@@ -1,7 +1,7 @@
 /*-
  *   BSD LICENSE
  *
- *   Copyright(c) 2014-2015 Chelsio Communications.
+ *   Copyright(c) 2014-2017 Chelsio Communications.
  *   All rights reserved.
  *
  *   Redistribution and use in source and binary forms, with or without
@@ -266,6 +266,18 @@
 #define A_SGE_FL_BUFFER_SIZE2 0x104c
 #define A_SGE_FL_BUFFER_SIZE3 0x1050
 
+#define A_SGE_FLM_CFG 0x1090
+
+#define S_CREDITCNT    4
+#define M_CREDITCNT    0x3U
+#define V_CREDITCNT(x) ((x) << S_CREDITCNT)
+#define G_CREDITCNT(x) (((x) >> S_CREDITCNT) & M_CREDITCNT)
+
+#define S_CREDITCNTPACKING    2
+#define M_CREDITCNTPACKING    0x3U
+#define V_CREDITCNTPACKING(x) ((x) << S_CREDITCNTPACKING)
+#define G_CREDITCNTPACKING(x) (((x) >> S_CREDITCNTPACKING) & M_CREDITCNTPACKING)
+
 #define A_SGE_CONM_CTRL 0x1094
 
 #define S_EGRTHRESHOLD    8
@@ -361,6 +373,10 @@
 
 #define A_SGE_CONTROL2 0x1124
 
+#define S_IDMAARBROUNDROBIN    19
+#define V_IDMAARBROUNDROBIN(x) ((x) << S_IDMAARBROUNDROBIN)
+#define F_IDMAARBROUNDROBIN    V_IDMAARBROUNDROBIN(1U)
+
 #define S_INGPACKBOUNDARY    16
 #define M_INGPACKBOUNDARY    0x7U
 #define V_INGPACKBOUNDARY(x) ((x) << S_INGPACKBOUNDARY)
@@ -404,6 +420,26 @@
 #define A_PCIE_FW 0x30b8
 #define A_PCIE_FW_PF 0x30bc
 
+#define A_PCIE_CFG2 0x3018
+
+#define S_TOTMAXTAG    0
+#define M_TOTMAXTAG    0x3U
+#define V_TOTMAXTAG(x) ((x) << S_TOTMAXTAG)
+
+#define S_T6_TOTMAXTAG    0
+#define M_T6_TOTMAXTAG    0x7U
+#define V_T6_TOTMAXTAG(x) ((x) << S_T6_TOTMAXTAG)
+
+#define A_PCIE_CMD_CFG	0x5980
+
+#define S_MINTAG	0
+#define M_MINTAG	0xffU
+#define V_MINTAG(x)	((x) << S_MINTAG)
+
+#define S_T6_MINTAG	0
+#define M_T6_MINTAG	0xffU
+#define V_T6_MINTAG(x)	((x) << S_T6_MINTAG)
+
 /* registers for module CIM */
 #define CIM_BASE_ADDR 0x7b00
 
@@ -427,6 +463,12 @@
 #define F_UPCRST    V_UPCRST(1U)
 
 /* registers for module TP */
+#define A_TP_OUT_CONFIG 0x7d04
+
+#define S_CRXPKTENC    3
+#define V_CRXPKTENC(x) ((x) << S_CRXPKTENC)
+#define F_CRXPKTENC    V_CRXPKTENC(1U)
+
 #define TP_BASE_ADDR 0x7d00
 
 #define A_TP_TIMER_RESOLUTION 0x7d90
@@ -537,6 +579,24 @@
 #define V_VF(x) ((x) << S_VF)
 #define G_VF(x) (((x) >> S_VF) & M_VF)
 
+#define A_MPS_STAT_CTL 0x9600
+
+#define S_COUNTPAUSEMCRX    5
+#define V_COUNTPAUSEMCRX(x) ((x) << S_COUNTPAUSEMCRX)
+#define F_COUNTPAUSEMCRX    V_COUNTPAUSEMCRX(1U)
+
+#define S_COUNTPAUSESTATRX    4
+#define V_COUNTPAUSESTATRX(x) ((x) << S_COUNTPAUSESTATRX)
+#define F_COUNTPAUSESTATRX    V_COUNTPAUSESTATRX(1U)
+
+#define S_COUNTPAUSEMCTX    3
+#define V_COUNTPAUSEMCTX(x) ((x) << S_COUNTPAUSEMCTX)
+#define F_COUNTPAUSEMCTX    V_COUNTPAUSEMCTX(1U)
+
+#define S_COUNTPAUSESTATTX    2
+#define V_COUNTPAUSESTATTX(x) ((x) << S_COUNTPAUSESTATTX)
+#define F_COUNTPAUSESTATTX    V_COUNTPAUSESTATTX(1U)
+
 #define A_MPS_PORT_STAT_TX_PORT_BYTES_L 0x400
 #define A_MPS_PORT_STAT_TX_PORT_BYTES_H 0x404
 #define A_MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408
@@ -747,6 +807,11 @@
 #define V_SOURCEPF(x) ((x) << S_SOURCEPF)
 #define G_SOURCEPF(x) (((x) >> S_SOURCEPF) & M_SOURCEPF)
 
+#define S_T6_SOURCEPF    9
+#define M_T6_SOURCEPF    0x7U
+#define V_T6_SOURCEPF(x) ((x) << S_T6_SOURCEPF)
+#define G_T6_SOURCEPF(x) (((x) >> S_T6_SOURCEPF) & M_T6_SOURCEPF)
+
 #define A_PL_PF_INT_ENABLE 0x3c4
 
 #define S_PFSW    3