X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fcxgbe%2Fbase%2Ft4fw_interface.h;h=a0a9292c0c88ddcdf2f86852fd01a9d049d9d1f3;hb=88ba30f0076c58ba076b13c5a2612c6bd6a465f5;hp=e2d2ee89766299fb08f50f55b39e1e072968eb7c;hpb=6fda3f0ddda9127c8562e724e3abc0f808c0bfd5;p=dpdk.git diff --git a/drivers/net/cxgbe/base/t4fw_interface.h b/drivers/net/cxgbe/base/t4fw_interface.h index e2d2ee8976..a0a9292c0c 100644 --- a/drivers/net/cxgbe/base/t4fw_interface.h +++ b/drivers/net/cxgbe/base/t4fw_interface.h @@ -61,6 +61,7 @@ enum fw_wr_opcodes { FW_ETH_TX_PKTS_WR = 0x09, FW_ETH_TX_PKT_VM_WR = 0x11, FW_ETH_TX_PKTS_VM_WR = 0x12, + FW_FILTER2_WR = 0x77, FW_ETH_TX_PKTS2_WR = 0x78, }; @@ -165,7 +166,7 @@ enum fw_filter_wr_cookie { FW_FILTER_WR_EINVAL, }; -struct fw_filter_wr { +struct fw_filter2_wr { __be32 op_pkd; __be32 len16_pkd; __be64 r3; @@ -195,6 +196,19 @@ struct fw_filter_wr { __be16 fpm; __be16 r7; __u8 sma[6]; + __be16 r8; + __u8 filter_type_swapmac; + __u8 natmode_to_ulp_type; + __be16 newlport; + __be16 newfport; + __u8 newlip[16]; + __u8 newfip[16]; + __be32 natseqcheck; + __be32 r9; + __be64 r10; + __be64 r11; + __be64 r12; + __be64 r13; }; #define S_FW_FILTER_WR_TID 12 @@ -234,6 +248,9 @@ struct fw_filter_wr { #define S_FW_FILTER_WR_DMAC 19 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC) +#define S_FW_FILTER_WR_SMAC 18 +#define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC) + #define S_FW_FILTER_WR_INSVLAN 17 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN) @@ -300,6 +317,15 @@ struct fw_filter_wr { #define S_FW_FILTER_WR_MATCHTYPEM 0 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM) +#define S_FW_FILTER2_WR_SWAPMAC 0 +#define V_FW_FILTER2_WR_SWAPMAC(x) ((x) << S_FW_FILTER2_WR_SWAPMAC) + +#define S_FW_FILTER2_WR_NATMODE 5 +#define V_FW_FILTER2_WR_NATMODE(x) ((x) << S_FW_FILTER2_WR_NATMODE) + +#define S_FW_FILTER2_WR_ULP_TYPE 0 +#define V_FW_FILTER2_WR_ULP_TYPE(x) ((x) << S_FW_FILTER2_WR_ULP_TYPE) + /****************************************************************************** * C O M M A N D s *********************/ @@ -601,7 +627,7 @@ struct fw_caps_config_cmd { __be16 niccaps; __be16 toecaps; __be16 rdmacaps; - __be16 r4; + __be16 cryptocaps; __be16 iscsicaps; __be16 fcoecaps; __be32 cfcsum; @@ -645,6 +671,23 @@ enum fw_params_mnem { /* * device parameters */ + +#define S_FW_PARAMS_PARAM_FILTER_MODE 16 +#define M_FW_PARAMS_PARAM_FILTER_MODE 0xffff +#define V_FW_PARAMS_PARAM_FILTER_MODE(x) \ + ((x) << S_FW_PARAMS_PARAM_FILTER_MODE) +#define G_FW_PARAMS_PARAM_FILTER_MODE(x) \ + (((x) >> S_FW_PARAMS_PARAM_FILTER_MODE) & \ + M_FW_PARAMS_PARAM_FILTER_MODE) + +#define S_FW_PARAMS_PARAM_FILTER_MASK 0 +#define M_FW_PARAMS_PARAM_FILTER_MASK 0xffff +#define V_FW_PARAMS_PARAM_FILTER_MASK(x) \ + ((x) << S_FW_PARAMS_PARAM_FILTER_MASK) +#define G_FW_PARAMS_PARAM_FILTER_MASK(x) \ + (((x) >> S_FW_PARAMS_PARAM_FILTER_MASK) & \ + M_FW_PARAMS_PARAM_FILTER_MASK) + enum fw_params_param_dev { FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ @@ -655,6 +698,13 @@ enum fw_params_param_dev { FW_PARAMS_PARAM_DEV_FWREV = 0x0B, /* fw version */ FW_PARAMS_PARAM_DEV_TPREV = 0x0C, /* tp version */ FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17, + FW_PARAMS_PARAM_DEV_FILTER2_WR = 0x1D, + FW_PARAMS_PARAM_DEV_OPAQUE_VIID_SMT_EXTN = 0x27, + FW_PARAMS_PARAM_DEV_HASHFILTER_WITH_OFLD = 0x28, + FW_PARAMS_PARAM_DEV_FILTER = 0x2E, + FW_PARAMS_PARAM_DEV_VI_ENABLE_INGRESS_AFTER_LINKUP = 0x32, + FW_PARAMS_PARAM_PFVF_RAWF_START = 0x36, + FW_PARAMS_PARAM_PFVF_RAWF_END = 0x37, }; /* @@ -668,7 +718,10 @@ enum fw_params_param_pfvf { FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31, - FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A + FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A, + FW_PARAMS_PARAM_PFVF_MAX_PKTS_PER_ETH_TX_PKTS_WR = 0x3D, + FW_PARAMS_PARAM_PFVF_GET_SMT_START = 0x3E, + FW_PARAMS_PARAM_PFVF_GET_SMT_SIZE = 0x3F, }; /* @@ -679,6 +732,11 @@ enum fw_params_param_dmaq { FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20, }; +enum fw_params_param_dev_filter { + FW_PARAM_DEV_FILTER_VNIC_MODE = 0x00, + FW_PARAM_DEV_FILTER_MODE_MASK = 0x01, +}; + #define S_FW_PARAMS_MNEM 24 #define M_FW_PARAMS_MNEM 0xff #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM) @@ -1210,6 +1268,18 @@ enum fw_vi_func { FW_VI_FUNC_ETH, }; +/* Macros for VIID parsing: + * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number + */ + +#define S_FW_VIID_VIVLD 7 +#define M_FW_VIID_VIVLD 0x1 +#define G_FW_VIID_VIVLD(x) (((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD) + +#define S_FW_VIID_VIN 0 +#define M_FW_VIID_VIN 0x7F +#define G_FW_VIID_VIN(x) (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN) + struct fw_vi_cmd { __be32 op_to_vfn; __be32 alloc_to_len16; @@ -1251,6 +1321,16 @@ struct fw_vi_cmd { #define G_FW_VI_CMD_FREE(x) (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE) #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U) +#define S_FW_VI_CMD_VFVLD 24 +#define M_FW_VI_CMD_VFVLD 0x1 +#define G_FW_VI_CMD_VFVLD(x) \ + (((x) >> S_FW_VI_CMD_VFVLD) & M_FW_VI_CMD_VFVLD) + +#define S_FW_VI_CMD_VIN 16 +#define M_FW_VI_CMD_VIN 0xff +#define G_FW_VI_CMD_VIN(x) \ + (((x) >> S_FW_VI_CMD_VIN) & M_FW_VI_CMD_VIN) + #define S_FW_VI_CMD_TYPE 15 #define M_FW_VI_CMD_TYPE 0x1 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE) @@ -1285,8 +1365,8 @@ struct fw_vi_cmd { #define FW_VI_MAC_ID_BASED_FREE 0x3FC enum fw_vi_mac_smac { - FW_VI_MAC_MPS_TCAM_ENTRY, - FW_VI_MAC_SMT_AND_MPSTCAM + FW_VI_MAC_MPS_TCAM_ENTRY = 0x0, + FW_VI_MAC_SMT_AND_MPSTCAM = 0x3 }; enum fw_vi_mac_entry_types { @@ -1521,41 +1601,6 @@ struct fw_vi_stats_cmd { #define S_FW_VI_STATS_CMD_IX 0 #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX) -/* old 16-bit port capabilities bitmap */ -enum fw_port_cap { - FW_PORT_CAP_SPEED_100M = 0x0001, - FW_PORT_CAP_SPEED_1G = 0x0002, - FW_PORT_CAP_SPEED_25G = 0x0004, - FW_PORT_CAP_SPEED_10G = 0x0008, - FW_PORT_CAP_SPEED_40G = 0x0010, - FW_PORT_CAP_SPEED_100G = 0x0020, - FW_PORT_CAP_FC_RX = 0x0040, - FW_PORT_CAP_FC_TX = 0x0080, - FW_PORT_CAP_ANEG = 0x0100, - FW_PORT_CAP_MDIX = 0x0200, - FW_PORT_CAP_MDIAUTO = 0x0400, - FW_PORT_CAP_FEC_RS = 0x0800, - FW_PORT_CAP_FEC_BASER_RS = 0x1000, - FW_PORT_CAP_FEC_RESERVED = 0x2000, - FW_PORT_CAP_802_3_PAUSE = 0x4000, - FW_PORT_CAP_802_3_ASM_DIR = 0x8000, -}; - -#define S_FW_PORT_CAP_SPEED 0 -#define M_FW_PORT_CAP_SPEED 0x3f -#define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED) -#define G_FW_PORT_CAP_SPEED(x) \ - (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED) - -enum fw_port_mdi { - FW_PORT_CAP_MDI_AUTO, -}; - -#define S_FW_PORT_CAP_MDI 9 -#define M_FW_PORT_CAP_MDI 3 -#define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI) -#define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI) - /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */ #define FW_PORT_CAP32_SPEED_100M 0x00000001UL #define FW_PORT_CAP32_SPEED_1G 0x00000002UL @@ -1573,6 +1618,9 @@ enum fw_port_mdi { #define FW_PORT_CAP32_MDIAUTO 0x00400000UL #define FW_PORT_CAP32_FEC_RS 0x00800000UL #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL +#define FW_PORT_CAP32_FEC_NO_FEC 0x02000000UL +#define FW_PORT_CAP32_FORCE_PAUSE 0x10000000UL +#define FW_PORT_CAP32_FORCE_FEC 0x20000000UL #define S_FW_PORT_CAP32_SPEED 0 #define M_FW_PORT_CAP32_SPEED 0xfff @@ -1580,8 +1628,16 @@ enum fw_port_mdi { #define G_FW_PORT_CAP32_SPEED(x) \ (((x) >> S_FW_PORT_CAP32_SPEED) & M_FW_PORT_CAP32_SPEED) +#define S_FW_PORT_CAP32_FC 16 +#define M_FW_PORT_CAP32_FC 0x3 +#define V_FW_PORT_CAP32_FC(x) ((x) << S_FW_PORT_CAP32_FC) + +#define S_FW_PORT_CAP32_802_3 18 +#define M_FW_PORT_CAP32_802_3 0x3 +#define V_FW_PORT_CAP32_802_3(x) ((x) << S_FW_PORT_CAP32_802_3) + enum fw_port_mdi32 { - FW_PORT_CAP32_MDI_AUTO, + FW_PORT_CAP32_MDI_AUTO = 1, }; #define S_FW_PORT_CAP32_MDI 21 @@ -1590,9 +1646,11 @@ enum fw_port_mdi32 { #define G_FW_PORT_CAP32_MDI(x) \ (((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI) +#define S_FW_PORT_CAP32_FEC 23 +#define M_FW_PORT_CAP32_FEC 0x1f +#define V_FW_PORT_CAP32_FEC(x) ((x) << S_FW_PORT_CAP32_FEC) + enum fw_port_action { - FW_PORT_ACTION_L1_CFG = 0x0001, - FW_PORT_ACTION_GET_PORT_INFO = 0x0003, FW_PORT_ACTION_L1_CFG32 = 0x0009, FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a, }; @@ -1737,37 +1795,12 @@ struct fw_port_cmd { (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE) #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U) -#define S_FW_PORT_CMD_MDIOCAP 21 -#define M_FW_PORT_CMD_MDIOCAP 0x1 -#define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP) -#define G_FW_PORT_CMD_MDIOCAP(x) \ - (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP) -#define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U) - -#define S_FW_PORT_CMD_MDIOADDR 16 -#define M_FW_PORT_CMD_MDIOADDR 0x1f -#define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR) -#define G_FW_PORT_CMD_MDIOADDR(x) \ - (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR) - #define S_FW_PORT_CMD_PTYPE 8 #define M_FW_PORT_CMD_PTYPE 0x1f #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE) #define G_FW_PORT_CMD_PTYPE(x) \ (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE) -#define S_FW_PORT_CMD_LINKDNRC 5 -#define M_FW_PORT_CMD_LINKDNRC 0x7 -#define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC) -#define G_FW_PORT_CMD_LINKDNRC(x) \ - (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC) - -#define S_FW_PORT_CMD_MODTYPE 0 -#define M_FW_PORT_CMD_MODTYPE 0x1f -#define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE) -#define G_FW_PORT_CMD_MODTYPE(x) \ - (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE) - #define S_FW_PORT_CMD_LSTATUS32 31 #define M_FW_PORT_CMD_LSTATUS32 0x1 #define V_FW_PORT_CMD_LSTATUS32(x) ((x) << S_FW_PORT_CMD_LSTATUS32) @@ -1847,10 +1880,10 @@ enum fw_port_module_type { FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4, FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5, FW_PORT_MOD_TYPE_LRM = 0x6, - FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3, - FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2, - FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1, - FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE + FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE32 - 3, + FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE32 - 2, + FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE32 - 1, + FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE32 }; /* used by FW and tools may use this to generate VPD */