X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fcxgbe%2Fcxgbe_ethdev.c;h=010a818eb61856109f7503831d3eaa916bd29591;hb=c09eb9352978fc0344e1865a1857e6e1c9cf266f;hp=3df51b5bede786e8297ded52bb734bfa7cfcc9b7;hpb=caccf8b318cafcdafe39faa3c5ce3eef67007621;p=dpdk.git diff --git a/drivers/net/cxgbe/cxgbe_ethdev.c b/drivers/net/cxgbe/cxgbe_ethdev.c index 3df51b5bed..010a818eb6 100644 --- a/drivers/net/cxgbe/cxgbe_ethdev.c +++ b/drivers/net/cxgbe/cxgbe_ethdev.c @@ -36,6 +36,7 @@ #include "cxgbe.h" #include "cxgbe_pfvf.h" +#include "cxgbe_flow.h" /* * Macros needed to support the PCI Device ID Table ... @@ -56,20 +57,7 @@ /* *... and the PCI ID Table itself ... */ -#include "t4_pci_id_tbl.h" - -#define CXGBE_TX_OFFLOADS (DEV_TX_OFFLOAD_VLAN_INSERT |\ - DEV_TX_OFFLOAD_IPV4_CKSUM |\ - DEV_TX_OFFLOAD_UDP_CKSUM |\ - DEV_TX_OFFLOAD_TCP_CKSUM |\ - DEV_TX_OFFLOAD_TCP_TSO) - -#define CXGBE_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_STRIP |\ - DEV_RX_OFFLOAD_CRC_STRIP |\ - DEV_RX_OFFLOAD_IPV4_CKSUM |\ - DEV_RX_OFFLOAD_JUMBO_FRAME |\ - DEV_RX_OFFLOAD_UDP_CKSUM |\ - DEV_RX_OFFLOAD_TCP_CKSUM) +#include "base/t4_pci_id_tbl.h" uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) @@ -199,23 +187,86 @@ void cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev) } int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev, - __rte_unused int wait_to_complete) + int wait_to_complete) { struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); struct adapter *adapter = pi->adapter; struct sge *s = &adapter->sge; - struct rte_eth_link *old_link = ð_dev->data->dev_link; - unsigned int work_done, budget = 4; + struct rte_eth_link new_link = { 0 }; + unsigned int i, work_done, budget = 32; + u8 old_link = pi->link_cfg.link_ok; + + for (i = 0; i < CXGBE_LINK_STATUS_POLL_CNT; i++) { + cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); + + /* Exit if link status changed or always forced up */ + if (pi->link_cfg.link_ok != old_link || force_linkup(adapter)) + break; + + if (!wait_to_complete) + break; + + rte_delay_ms(CXGBE_LINK_STATUS_POLL_MS); + } + new_link.link_status = force_linkup(adapter) ? + ETH_LINK_UP : pi->link_cfg.link_ok; + new_link.link_autoneg = pi->link_cfg.autoneg; + new_link.link_duplex = ETH_LINK_FULL_DUPLEX; + new_link.link_speed = pi->link_cfg.speed; + + return rte_eth_linkstatus_set(eth_dev, &new_link); +} + +/** + * Set device link up. + */ +int cxgbe_dev_set_link_up(struct rte_eth_dev *dev) +{ + struct port_info *pi = (struct port_info *)(dev->data->dev_private); + struct adapter *adapter = pi->adapter; + unsigned int work_done, budget = 32; + struct sge *s = &adapter->sge; + int ret; + + /* Flush all link events */ cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); - if (old_link->link_status == pi->link_cfg.link_ok) - return -1; /* link not changed */ - eth_dev->data->dev_link.link_status = pi->link_cfg.link_ok; - eth_dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX; - eth_dev->data->dev_link.link_speed = pi->link_cfg.speed; + /* If link already up, nothing to do */ + if (pi->link_cfg.link_ok) + return 0; + + ret = cxgbe_set_link_status(pi, true); + if (ret) + return ret; - /* link has changed */ + cxgbe_dev_link_update(dev, 1); + return 0; +} + +/** + * Set device link down. + */ +int cxgbe_dev_set_link_down(struct rte_eth_dev *dev) +{ + struct port_info *pi = (struct port_info *)(dev->data->dev_private); + struct adapter *adapter = pi->adapter; + unsigned int work_done, budget = 32; + struct sge *s = &adapter->sge; + int ret; + + /* Flush all link events */ + cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); + + /* If link already down, nothing to do */ + if (!pi->link_cfg.link_ok) + return 0; + + ret = cxgbe_set_link_status(pi, false); + if (ret) + return ret; + + cxgbe_dev_link_update(dev, 0); return 0; } @@ -256,7 +307,6 @@ void cxgbe_dev_close(struct rte_eth_dev *eth_dev) { struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); struct adapter *adapter = pi->adapter; - int i, dev_down = 0; CXGBE_FUNC_TRACE(); @@ -270,22 +320,6 @@ void cxgbe_dev_close(struct rte_eth_dev *eth_dev) * have been disabled */ t4_sge_eth_clear_queues(pi); - - /* See if all ports are down */ - for_each_port(adapter, i) { - pi = adap2pinfo(adapter, i); - /* - * Skip first port of the adapter since it will be closed - * by DPDK - */ - if (i == 0) - continue; - dev_down += (pi->eth_dev->data->dev_started == 0) ? 1 : 0; - } - - /* If rest of the ports are stopped, then free up resources */ - if (dev_down == (adapter->params.nports - 1)) - cxgbe_close(adapter); } /* Start the device. @@ -294,6 +328,7 @@ void cxgbe_dev_close(struct rte_eth_dev *eth_dev) int cxgbe_dev_start(struct rte_eth_dev *eth_dev) { struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); + struct rte_eth_rxmode *rx_conf = ð_dev->data->dev_conf.rxmode; struct adapter *adapter = pi->adapter; int err = 0, i; @@ -314,6 +349,11 @@ int cxgbe_dev_start(struct rte_eth_dev *eth_dev) goto out; } + if (rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) + eth_dev->data->scattered_rx = 1; + else + eth_dev->data->scattered_rx = 0; + cxgbe_enable_rx_queues(pi); err = setup_rss(pi); @@ -360,44 +400,27 @@ void cxgbe_dev_stop(struct rte_eth_dev *eth_dev) * have been disabled */ t4_sge_eth_clear_queues(pi); + eth_dev->data->scattered_rx = 0; } int cxgbe_dev_configure(struct rte_eth_dev *eth_dev) { struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); struct adapter *adapter = pi->adapter; - uint64_t unsupported_offloads, configured_offloads; int err; CXGBE_FUNC_TRACE(); - configured_offloads = eth_dev->data->dev_conf.rxmode.offloads; - if (!(configured_offloads & DEV_RX_OFFLOAD_CRC_STRIP)) { - dev_info(adapter, "can't disable hw crc strip\n"); - configured_offloads |= DEV_RX_OFFLOAD_CRC_STRIP; - } - - unsupported_offloads = configured_offloads & ~CXGBE_RX_OFFLOADS; - if (unsupported_offloads) { - dev_err(adapter, "Rx offloads 0x%" PRIx64 " are not supported. " - "Supported:0x%" PRIx64 "\n", - unsupported_offloads, (uint64_t)CXGBE_RX_OFFLOADS); - return -ENOTSUP; - } - - configured_offloads = eth_dev->data->dev_conf.txmode.offloads; - unsupported_offloads = configured_offloads & ~CXGBE_TX_OFFLOADS; - if (unsupported_offloads) { - dev_err(adapter, "Tx offloads 0x%" PRIx64 " are not supported. " - "Supported:0x%" PRIx64 "\n", - unsupported_offloads, (uint64_t)CXGBE_TX_OFFLOADS); - return -ENOTSUP; - } if (!(adapter->flags & FW_QUEUE_BOUND)) { err = setup_sge_fwevtq(adapter); if (err) return err; adapter->flags |= FW_QUEUE_BOUND; + if (is_pf4(adapter)) { + err = setup_sge_ctrl_txq(adapter); + if (err) + return err; + } } err = cfg_queue_count(eth_dev); @@ -440,7 +463,7 @@ int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t queue_idx, uint16_t nb_desc, unsigned int socket_id, - const struct rte_eth_txconf *tx_conf) + const struct rte_eth_txconf *tx_conf __rte_unused) { struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); struct adapter *adapter = pi->adapter; @@ -448,15 +471,6 @@ int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset + queue_idx]; int err = 0; unsigned int temp_nb_desc; - uint64_t unsupported_offloads; - - unsupported_offloads = tx_conf->offloads & ~CXGBE_TX_OFFLOADS; - if (unsupported_offloads) { - dev_err(adapter, "Tx offloads 0x%" PRIx64 " are not supported. " - "Supported:0x%" PRIx64 "\n", - unsupported_offloads, (uint64_t)CXGBE_TX_OFFLOADS); - return -ENOTSUP; - } dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n", __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc, @@ -553,7 +567,7 @@ int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t queue_idx, uint16_t nb_desc, unsigned int socket_id, - const struct rte_eth_rxconf *rx_conf, + const struct rte_eth_rxconf *rx_conf __rte_unused, struct rte_mempool *mp) { struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); @@ -565,21 +579,6 @@ int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev, unsigned int temp_nb_desc; struct rte_eth_dev_info dev_info; unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len; - uint64_t unsupported_offloads, configured_offloads; - - configured_offloads = rx_conf->offloads; - if (!(configured_offloads & DEV_RX_OFFLOAD_CRC_STRIP)) { - dev_info(adapter, "can't disable hw crc strip\n"); - configured_offloads |= DEV_RX_OFFLOAD_CRC_STRIP; - } - - unsupported_offloads = configured_offloads & ~CXGBE_RX_OFFLOADS; - if (unsupported_offloads) { - dev_err(adapter, "Rx offloads 0x%" PRIx64 " are not supported. " - "Supported:0x%" PRIx64 "\n", - unsupported_offloads, (uint64_t)CXGBE_RX_OFFLOADS); - return -ENOTSUP; - } dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n", __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc, @@ -853,13 +852,13 @@ static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, return err; if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) { - rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP; + rss_hf |= CXGBE_RSS_HF_TCP_IPV6_MASK; if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN) - rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP; + rss_hf |= CXGBE_RSS_HF_UDP_IPV6_MASK; } if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) - rss_hf |= ETH_RSS_IPV6; + rss_hf |= CXGBE_RSS_HF_IPV6_MASK; if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) { rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; @@ -868,7 +867,7 @@ static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, } if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) - rss_hf |= ETH_RSS_IPV4; + rss_hf |= CXGBE_RSS_HF_IPV4_MASK; rss_conf->rss_hf = rss_hf; @@ -1059,11 +1058,9 @@ static int cxgbe_get_regs(struct rte_eth_dev *eth_dev, int cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr) { struct port_info *pi = (struct port_info *)(dev->data->dev_private); - struct adapter *adapter = pi->adapter; int ret; - ret = t4_change_mac(adapter, adapter->mbox, pi->viid, - pi->xact_addr_filt, (u8 *)addr, true, true); + ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt, (u8 *)addr); if (ret < 0) { dev_err(adapter, "failed to set mac addr; err = %d\n", ret); @@ -1085,6 +1082,8 @@ static const struct eth_dev_ops cxgbe_eth_dev_ops = { .dev_infos_get = cxgbe_dev_info_get, .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get, .link_update = cxgbe_dev_link_update, + .dev_set_link_up = cxgbe_dev_set_link_up, + .dev_set_link_down = cxgbe_dev_set_link_down, .mtu_set = cxgbe_dev_mtu_set, .tx_queue_setup = cxgbe_dev_tx_queue_setup, .tx_queue_start = cxgbe_dev_tx_queue_start, @@ -1094,6 +1093,7 @@ static const struct eth_dev_ops cxgbe_eth_dev_ops = { .rx_queue_start = cxgbe_dev_rx_queue_start, .rx_queue_stop = cxgbe_dev_rx_queue_stop, .rx_queue_release = cxgbe_dev_rx_queue_release, + .filter_ctrl = cxgbe_dev_filter_ctrl, .stats_get = cxgbe_dev_stats_get, .stats_reset = cxgbe_dev_stats_reset, .flow_ctrl_get = cxgbe_flow_ctrl_get, @@ -1147,6 +1147,7 @@ static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev) eth_dev->rx_pkt_burst; rest_eth_dev->tx_pkt_burst = eth_dev->tx_pkt_burst; + rte_eth_dev_probing_finish(rest_eth_dev); } } return 0; @@ -1182,6 +1183,16 @@ out_free_adapter: return err; } +static int eth_cxgbe_dev_uninit(struct rte_eth_dev *eth_dev) +{ + struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); + struct adapter *adap = pi->adapter; + + /* Free up other ports and all resources */ + cxgbe_close(adap); + return 0; +} + static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, struct rte_pci_device *pci_dev) { @@ -1191,7 +1202,7 @@ static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev) { - return rte_eth_dev_pci_generic_remove(pci_dev, NULL); + return rte_eth_dev_pci_generic_remove(pci_dev, eth_cxgbe_dev_uninit); } static struct rte_pci_driver rte_cxgbe_pmd = { @@ -1204,3 +1215,6 @@ static struct rte_pci_driver rte_cxgbe_pmd = { RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd); RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl); RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci"); +RTE_PMD_REGISTER_PARAM_STRING(net_cxgbe, + CXGBE_DEVARG_KEEP_OVLAN "=<0|1> " + CXGBE_DEVARG_FORCE_LINK_UP "=<0|1> ");