X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fcxgbe%2Fcxgbe_ethdev.c;h=bb929a98a9ad35e20bbc9348c2c90fd0d14209df;hb=c830cb295411fc71c3f3d3591308d531937dd58f;hp=788464252bd4cfda7774e109d64ac60ad56b8852;hpb=eeefe73f0af19a287b5dec1d0b63bb83821d8dc9;p=dpdk.git diff --git a/drivers/net/cxgbe/cxgbe_ethdev.c b/drivers/net/cxgbe/cxgbe_ethdev.c index 788464252b..bb929a98a9 100644 --- a/drivers/net/cxgbe/cxgbe_ethdev.c +++ b/drivers/net/cxgbe/cxgbe_ethdev.c @@ -1,7 +1,7 @@ /*- * BSD LICENSE * - * Copyright(c) 2014-2015 Chelsio Communications. + * Copyright(c) 2014-2016 Chelsio Communications. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -171,6 +171,7 @@ static void cxgbe_dev_info_get(struct rte_eth_dev *eth_dev, device_info->rx_desc_lim = cxgbe_desc_lim; device_info->tx_desc_lim = cxgbe_desc_lim; + device_info->speed_capa = ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G; } static void cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev) @@ -405,23 +406,33 @@ static int cxgbe_dev_configure(struct rte_eth_dev *eth_dev) static int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) { + int ret; struct sge_eth_txq *txq = (struct sge_eth_txq *) (eth_dev->data->tx_queues[tx_queue_id]); dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id); - return t4_sge_eth_txq_start(txq); + ret = t4_sge_eth_txq_start(txq); + if (ret == 0) + eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; + + return ret; } static int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) { + int ret; struct sge_eth_txq *txq = (struct sge_eth_txq *) (eth_dev->data->tx_queues[tx_queue_id]); dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id); - return t4_sge_eth_txq_stop(txq); + ret = t4_sge_eth_txq_stop(txq); + if (ret == 0) + eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; + + return ret; } static int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, @@ -497,6 +508,7 @@ static void cxgbe_dev_tx_queue_release(void *q) static int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) { + int ret; struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); struct adapter *adap = pi->adapter; struct sge_rspq *q; @@ -505,12 +517,18 @@ static int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, __func__, pi->port_id, rx_queue_id); q = eth_dev->data->rx_queues[rx_queue_id]; - return t4_sge_eth_rxq_start(adap, q); + + ret = t4_sge_eth_rxq_start(adap, q); + if (ret == 0) + eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; + + return ret; } static int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) { + int ret; struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); struct adapter *adap = pi->adapter; struct sge_rspq *q; @@ -519,7 +537,11 @@ static int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, __func__, pi->port_id, rx_queue_id); q = eth_dev->data->rx_queues[rx_queue_id]; - return t4_sge_eth_rxq_stop(adap, q); + ret = t4_sge_eth_rxq_stop(adap, q); + if (ret == 0) + eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; + + return ret; } static int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev, @@ -634,23 +656,18 @@ static void cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev, /* RX Stats */ eth_stats->ipackets = ps.rx_frames; eth_stats->ibytes = ps.rx_octets; - eth_stats->imcasts = ps.rx_mcast_frames; eth_stats->imissed = ps.rx_ovflow0 + ps.rx_ovflow1 + ps.rx_ovflow2 + ps.rx_ovflow3 + ps.rx_trunc0 + ps.rx_trunc1 + ps.rx_trunc2 + ps.rx_trunc3; - eth_stats->ibadcrc = ps.rx_fcs_err; - eth_stats->ibadlen = ps.rx_jabber + ps.rx_too_long + ps.rx_runt; - eth_stats->ierrors = ps.rx_symbol_err + eth_stats->ibadcrc + - eth_stats->ibadlen + ps.rx_len_err + - eth_stats->imissed; - eth_stats->rx_pause_xon = ps.rx_pause; + eth_stats->ierrors = ps.rx_symbol_err + ps.rx_fcs_err + + ps.rx_jabber + ps.rx_too_long + ps.rx_runt + + ps.rx_len_err; /* TX Stats */ eth_stats->opackets = ps.tx_frames; eth_stats->obytes = ps.tx_octets; eth_stats->oerrors = ps.tx_error_frames; - eth_stats->tx_pause_xon = ps.tx_pause; for (i = 0; i < pi->n_rx_qsets; i++) { struct sge_eth_rxq *rxq = @@ -750,7 +767,190 @@ static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev, &pi->link_cfg); } -static struct eth_dev_ops cxgbe_eth_dev_ops = { +static const uint32_t * +cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev) +{ + static const uint32_t ptypes[] = { + RTE_PTYPE_L3_IPV4, + RTE_PTYPE_L3_IPV6, + RTE_PTYPE_UNKNOWN + }; + + if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts) + return ptypes; + return NULL; +} + +static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev) +{ + RTE_SET_USED(dev); + return EEPROMSIZE; +} + +/** + * eeprom_ptov - translate a physical EEPROM address to virtual + * @phys_addr: the physical EEPROM address + * @fn: the PCI function number + * @sz: size of function-specific area + * + * Translate a physical EEPROM address to virtual. The first 1K is + * accessed through virtual addresses starting at 31K, the rest is + * accessed through virtual addresses starting at 0. + * + * The mapping is as follows: + * [0..1K) -> [31K..32K) + * [1K..1K+A) -> [31K-A..31K) + * [1K+A..ES) -> [0..ES-A-1K) + * + * where A = @fn * @sz, and ES = EEPROM size. + */ +static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz) +{ + fn *= sz; + if (phys_addr < 1024) + return phys_addr + (31 << 10); + if (phys_addr < 1024 + fn) + return fn + phys_addr - 1024; + if (phys_addr < EEPROMSIZE) + return phys_addr - 1024 - fn; + if (phys_addr < EEPROMVSIZE) + return phys_addr - 1024; + return -EINVAL; +} + +/* The next two routines implement eeprom read/write from physical addresses. + */ +static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v) +{ + int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE); + + if (vaddr >= 0) + vaddr = t4_seeprom_read(adap, vaddr, v); + return vaddr < 0 ? vaddr : 0; +} + +static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v) +{ + int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE); + + if (vaddr >= 0) + vaddr = t4_seeprom_write(adap, vaddr, v); + return vaddr < 0 ? vaddr : 0; +} + +#define EEPROM_MAGIC 0x38E2F10C + +static int cxgbe_get_eeprom(struct rte_eth_dev *dev, + struct rte_dev_eeprom_info *e) +{ + struct port_info *pi = (struct port_info *)(dev->data->dev_private); + struct adapter *adapter = pi->adapter; + u32 i, err = 0; + u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0); + + if (!buf) + return -ENOMEM; + + e->magic = EEPROM_MAGIC; + for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4) + err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]); + + if (!err) + rte_memcpy(e->data, buf + e->offset, e->length); + rte_free(buf); + return err; +} + +static int cxgbe_set_eeprom(struct rte_eth_dev *dev, + struct rte_dev_eeprom_info *eeprom) +{ + struct port_info *pi = (struct port_info *)(dev->data->dev_private); + struct adapter *adapter = pi->adapter; + u8 *buf; + int err = 0; + u32 aligned_offset, aligned_len, *p; + + if (eeprom->magic != EEPROM_MAGIC) + return -EINVAL; + + aligned_offset = eeprom->offset & ~3; + aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3; + + if (adapter->pf > 0) { + u32 start = 1024 + adapter->pf * EEPROMPFSIZE; + + if (aligned_offset < start || + aligned_offset + aligned_len > start + EEPROMPFSIZE) + return -EPERM; + } + + if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) { + /* RMW possibly needed for first or last words. + */ + buf = rte_zmalloc(NULL, aligned_len, 0); + if (!buf) + return -ENOMEM; + err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf); + if (!err && aligned_len > 4) + err = eeprom_rd_phys(adapter, + aligned_offset + aligned_len - 4, + (u32 *)&buf[aligned_len - 4]); + if (err) + goto out; + rte_memcpy(buf + (eeprom->offset & 3), eeprom->data, + eeprom->length); + } else { + buf = eeprom->data; + } + + err = t4_seeprom_wp(adapter, false); + if (err) + goto out; + + for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) { + err = eeprom_wr_phys(adapter, aligned_offset, *p); + aligned_offset += 4; + } + + if (!err) + err = t4_seeprom_wp(adapter, true); +out: + if (buf != eeprom->data) + rte_free(buf); + return err; +} + +static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev) +{ + struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); + struct adapter *adapter = pi->adapter; + + return t4_get_regs_len(adapter) / sizeof(uint32_t); +} + +static int cxgbe_get_regs(struct rte_eth_dev *eth_dev, + struct rte_dev_reg_info *regs) +{ + struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); + struct adapter *adapter = pi->adapter; + + regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) | + (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) | + (1 << 16); + + if (regs->data == NULL) { + regs->length = cxgbe_get_regs_len(eth_dev); + regs->width = sizeof(uint32_t); + + return 0; + } + + t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t))); + + return 0; +} + +static const struct eth_dev_ops cxgbe_eth_dev_ops = { .dev_start = cxgbe_dev_start, .dev_stop = cxgbe_dev_stop, .dev_close = cxgbe_dev_close, @@ -760,6 +960,7 @@ static struct eth_dev_ops cxgbe_eth_dev_ops = { .allmulticast_disable = cxgbe_dev_allmulticast_disable, .dev_configure = cxgbe_dev_configure, .dev_infos_get = cxgbe_dev_info_get, + .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get, .link_update = cxgbe_dev_link_update, .mtu_set = cxgbe_dev_mtu_set, .tx_queue_setup = cxgbe_dev_tx_queue_setup, @@ -774,6 +975,10 @@ static struct eth_dev_ops cxgbe_eth_dev_ops = { .stats_reset = cxgbe_dev_stats_reset, .flow_ctrl_get = cxgbe_flow_ctrl_get, .flow_ctrl_set = cxgbe_flow_ctrl_set, + .get_eeprom_length = cxgbe_get_eeprom_length, + .get_eeprom = cxgbe_get_eeprom, + .set_eeprom = cxgbe_set_eeprom, + .get_reg = cxgbe_get_regs, }; /* @@ -802,8 +1007,6 @@ static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev) pci_dev = eth_dev->pci_dev; - rte_eth_copy_pci_info(eth_dev, pci_dev); - snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id); adapter = rte_zmalloc(name, sizeof(*adapter), 0); if (!adapter) @@ -821,42 +1024,30 @@ static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev) pi->adapter = adapter; err = cxgbe_probe(adapter); - if (err) + if (err) { dev_err(adapter, "%s: cxgbe probe failed with err %d\n", __func__, err); + goto out_free_adapter; + } + + return 0; out_free_adapter: + rte_free(adapter); return err; } static struct eth_driver rte_cxgbe_pmd = { - { + .pci_drv = { .name = "rte_cxgbe_pmd", .id_table = cxgb4_pci_tbl, .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, + .probe = rte_eth_dev_pci_probe, + .remove = rte_eth_dev_pci_remove, }, .eth_dev_init = eth_cxgbe_dev_init, .dev_private_size = sizeof(struct port_info), }; -/* - * Driver initialization routine. - * Invoked once at EAL init time. - * Register itself as the [Poll Mode] Driver of PCI CXGBE devices. - */ -static int rte_cxgbe_pmd_init(const char *name __rte_unused, - const char *params __rte_unused) -{ - CXGBE_FUNC_TRACE(); - - rte_eth_driver_register(&rte_cxgbe_pmd); - return 0; -} - -static struct rte_driver rte_cxgbe_driver = { - .name = "cxgbe_driver", - .type = PMD_PDEV, - .init = rte_cxgbe_pmd_init, -}; - -PMD_REGISTER_DRIVER(rte_cxgbe_driver); +DRIVER_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd.pci_drv); +DRIVER_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl);