X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fcxgbe%2Fcxgbe_main.c;h=ceaf5ab2c691753c9364c60b03c2474061f50a89;hb=3eae93a9bfd5f4bf56bedfa4affa690d36128fc4;hp=3029b57c695a016c509953e521362977ccf4b617;hpb=4a01078b4fd1d9dcfe3a154b4ad864452f34ab5e;p=dpdk.git diff --git a/drivers/net/cxgbe/cxgbe_main.c b/drivers/net/cxgbe/cxgbe_main.c index 3029b57c69..ceaf5ab2c6 100644 --- a/drivers/net/cxgbe/cxgbe_main.c +++ b/drivers/net/cxgbe/cxgbe_main.c @@ -1,7 +1,7 @@ /*- * BSD LICENSE * - * Copyright(c) 2014-2015 Chelsio Communications. + * Copyright(c) 2014-2016 Chelsio Communications. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -200,7 +200,7 @@ int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, static inline bool is_x_1g_port(const struct link_config *lc) { - return ((lc->supported & FW_PORT_CAP_SPEED_1G) != 0); + return (lc->supported & FW_PORT_CAP_SPEED_1G) != 0; } static inline bool is_x_10g_port(const struct link_config *lc) @@ -310,6 +310,17 @@ void cfg_queues(struct rte_eth_dev *eth_dev) } } +void cxgbe_stats_get(struct port_info *pi, struct port_stats *stats) +{ + t4_get_port_stats_offset(pi->adapter, pi->tx_chan, stats, + &pi->stats_base); +} + +void cxgbe_stats_reset(struct port_info *pi) +{ + t4_clr_port_stats(pi->adapter, pi->tx_chan); +} + static void setup_memwin(struct adapter *adap) { u32 mem_win0_base; @@ -344,7 +355,7 @@ static int init_rss(struct adapter *adap) for_each_port(adap, i) { struct port_info *pi = adap2pinfo(adap, i); - pi->rss = rte_zmalloc(NULL, pi->rss_size, 0); + pi->rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0); if (!pi->rss) return -ENOMEM; } @@ -372,7 +383,8 @@ static void print_port_info(struct adapter *adap) if (bufp != buf) --bufp; sprintf(bufp, "BASE-%s", - t4_get_port_type_description(pi->port_type)); + t4_get_port_type_description( + (enum fw_port_type)pi->port_type)); dev_info(adap, " " PCI_PRI_FMT " Chelsio rev %d %s %s\n", @@ -399,7 +411,7 @@ static int adap_init0_tweaks(struct adapter *adapter) * Line Size, etc. The firmware default is for a 4KB Page Size and * 64B Cache Line Size ... */ - t4_fixup_host_params_compat(adapter, PAGE_SIZE, L1_CACHE_BYTES, + t4_fixup_host_params_compat(adapter, CXGBE_PAGE_SIZE, L1_CACHE_BYTES, T5_LAST_REV); /* @@ -410,6 +422,13 @@ static int adap_init0_tweaks(struct adapter *adapter) t4_set_reg_field(adapter, A_SGE_CONTROL, V_PKTSHIFT(M_PKTSHIFT), V_PKTSHIFT(rx_dma_offset)); + t4_set_reg_field(adapter, A_SGE_FLM_CFG, + V_CREDITCNT(M_CREDITCNT) | M_CREDITCNTPACKING, + V_CREDITCNT(3) | V_CREDITCNTPACKING(1)); + + t4_set_reg_field(adapter, A_SGE_CONTROL2, V_IDMAARBROUNDROBIN(1U), + V_IDMAARBROUNDROBIN(1U)); + /* * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux * adds the pseudo header itself. @@ -618,7 +637,7 @@ static int adap_init0(struct adapter *adap) dev_err(adap, "Failed to restart. Exit.\n"); goto bye; } - state &= ~DEV_STATE_INIT; + state = (enum dev_state)((unsigned)state & ~DEV_STATE_INIT); } t4_get_fw_version(adap, &adap->params.fw_vers); @@ -826,6 +845,54 @@ void t4_os_portmod_changed(const struct adapter *adap, int port_id) pi->port_id, pi->mod_type); } +/** + * link_start - enable a port + * @dev: the port to enable + * + * Performs the MAC and PHY actions needed to enable a port. + */ +int link_start(struct port_info *pi) +{ + struct adapter *adapter = pi->adapter; + int ret; + unsigned int mtu; + + mtu = pi->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len - + (ETHER_HDR_LEN + ETHER_CRC_LEN); + + /* + * We do not set address filters and promiscuity here, the stack does + * that step explicitly. + */ + ret = t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, -1, -1, + -1, 1, true); + if (ret == 0) { + ret = t4_change_mac(adapter, adapter->mbox, pi->viid, + pi->xact_addr_filt, + (u8 *)&pi->eth_dev->data->mac_addrs[0], + true, true); + if (ret >= 0) { + pi->xact_addr_filt = ret; + ret = 0; + } + } + if (ret == 0) + ret = t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan, + &pi->link_cfg); + if (ret == 0) { + /* + * Enabling a Virtual Interface can result in an interrupt + * during the processing of the VI Enable command and, in some + * paths, result in an attempt to issue another command in the + * interrupt context. Thus, we disable interrupts during the + * course of the VI Enable command ... + */ + ret = t4_enable_vi_params(adapter, adapter->mbox, pi->viid, + true, true, false); + } + return ret; +} + /** * cxgb4_write_rss - write the RSS table for a given port * @pi: the port @@ -907,6 +974,101 @@ int setup_rss(struct port_info *pi) return 0; } +/* + * Enable NAPI scheduling and interrupt generation for all Rx queues. + */ +static void enable_rx(struct adapter *adap) +{ + struct sge *s = &adap->sge; + struct sge_rspq *q = &s->fw_evtq; + int i, j; + + /* 0-increment GTS to start the timer and enable interrupts */ + t4_write_reg(adap, MYPF_REG(A_SGE_PF_GTS), + V_SEINTARM(q->intr_params) | + V_INGRESSQID(q->cntxt_id)); + + for_each_port(adap, i) { + const struct port_info *pi = &adap->port[i]; + struct rte_eth_dev *eth_dev = pi->eth_dev; + + for (j = 0; j < eth_dev->data->nb_rx_queues; j++) { + q = eth_dev->data->rx_queues[j]; + + /* + * 0-increment GTS to start the timer and enable + * interrupts + */ + t4_write_reg(adap, MYPF_REG(A_SGE_PF_GTS), + V_SEINTARM(q->intr_params) | + V_INGRESSQID(q->cntxt_id)); + } + } +} + +/** + * cxgb_up - enable the adapter + * @adap: adapter being enabled + * + * Called when the first port is enabled, this function performs the + * actions necessary to make an adapter operational, such as completing + * the initialization of HW modules, and enabling interrupts. + */ +int cxgbe_up(struct adapter *adap) +{ + enable_rx(adap); + t4_sge_tx_monitor_start(adap); + t4_intr_enable(adap); + adap->flags |= FULL_INIT_DONE; + + /* TODO: deadman watchdog ?? */ + return 0; +} + +/* + * Close the port + */ +int cxgbe_down(struct port_info *pi) +{ + struct adapter *adapter = pi->adapter; + int err = 0; + + err = t4_enable_vi(adapter, adapter->mbox, pi->viid, false, false); + if (err) { + dev_err(adapter, "%s: disable_vi failed: %d\n", __func__, err); + return err; + } + + t4_reset_link_config(adapter, pi->port_id); + return 0; +} + +/* + * Release resources when all the ports have been stopped. + */ +void cxgbe_close(struct adapter *adapter) +{ + struct port_info *pi; + int i; + + if (adapter->flags & FULL_INIT_DONE) { + t4_intr_disable(adapter); + t4_sge_tx_monitor_stop(adapter); + t4_free_sge_resources(adapter); + for_each_port(adapter, i) { + pi = adap2pinfo(adapter, i); + if (pi->viid != 0) + t4_free_vi(adapter, adapter->mbox, + adapter->pf, 0, pi->viid); + rte_free(pi->eth_dev->data->mac_addrs); + } + adapter->flags &= ~FULL_INIT_DONE; + } + + if (adapter->flags & FW_OK) + t4_fw_bye(adapter, adapter->mbox); +} + int cxgbe_probe(struct adapter *adapter) { struct port_info *pi; @@ -949,7 +1111,7 @@ int cxgbe_probe(struct adapter *adapter) qpp = 1 << ((t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp) & M_QUEUESPERPAGEPF0); - num_seg = PAGE_SIZE / UDBS_SEG_SIZE; + num_seg = CXGBE_PAGE_SIZE / UDBS_SEG_SIZE; if (qpp > num_seg) dev_warn(adapter, "Incorrect SGE EGRESS QUEUES_PER_PAGE configuration, continuing in debug mode\n"); @@ -1007,6 +1169,9 @@ allocate_mac: pi->eth_dev->dev_ops = adapter->eth_dev->dev_ops; pi->eth_dev->tx_pkt_burst = adapter->eth_dev->tx_pkt_burst; pi->eth_dev->rx_pkt_burst = adapter->eth_dev->rx_pkt_burst; + + rte_eth_copy_pci_info(pi->eth_dev, pi->eth_dev->pci_dev); + TAILQ_INIT(&pi->eth_dev->link_intr_cbs); pi->eth_dev->data->mac_addrs = rte_zmalloc(name,