X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fcxgbe%2Fcxgbe_main.c;h=df54e54f509c47df9fd36371e467536cff36aebb;hb=993541b2fa4ffe4b532e22fae58fd9aa6638e441;hp=c3e6b9557fc6b71b1eda4539c8b99fbfe5d54661;hpb=71e9b334a23764a5baa55cbacbdd99aeb9733631;p=dpdk.git diff --git a/drivers/net/cxgbe/cxgbe_main.c b/drivers/net/cxgbe/cxgbe_main.c index c3e6b9557f..df54e54f50 100644 --- a/drivers/net/cxgbe/cxgbe_main.c +++ b/drivers/net/cxgbe/cxgbe_main.c @@ -37,8 +37,10 @@ #include "base/t4_regs.h" #include "base/t4_msg.h" #include "cxgbe.h" +#include "cxgbe_pfvf.h" #include "clip_tbl.h" #include "l2t.h" +#include "smt.h" #include "mps_tcam.h" /** @@ -105,6 +107,10 @@ static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp, const struct cpl_l2t_write_rpl *p = (const void *)rsp; cxgbe_do_l2t_write_rpl(q->adapter, p); + } else if (opcode == CPL_SMT_WRITE_RPL) { + const struct cpl_smt_write_rpl *p = (const void *)rsp; + + cxgbe_do_smt_write_rpl(q->adapter, p); } else { dev_err(adapter, "unexpected CPL %#x on FW event queue\n", opcode); @@ -669,19 +675,26 @@ void cxgbe_print_port_info(struct adapter *adap) } } -static int -check_devargs_handler(__rte_unused const char *key, const char *value, - __rte_unused void *opaque) +static int check_devargs_handler(const char *key, const char *value, void *p) { - if (strcmp(value, "1")) - return -1; + if (!strncmp(key, CXGBE_DEVARG_CMN_KEEP_OVLAN, strlen(key)) || + !strncmp(key, CXGBE_DEVARG_CMN_TX_MODE_LATENCY, strlen(key)) || + !strncmp(key, CXGBE_DEVARG_VF_FORCE_LINK_UP, strlen(key))) { + if (!strncmp(value, "1", 1)) { + bool *dst_val = (bool *)p; + + *dst_val = true; + } + } return 0; } -int cxgbe_get_devargs(struct rte_devargs *devargs, const char *key) +static int cxgbe_get_devargs(struct rte_devargs *devargs, const char *key, + void *p) { struct rte_kvargs *kvlist; + int ret = 0; if (!devargs) return 0; @@ -690,24 +703,47 @@ int cxgbe_get_devargs(struct rte_devargs *devargs, const char *key) if (!kvlist) return 0; - if (!rte_kvargs_count(kvlist, key)) { - rte_kvargs_free(kvlist); - return 0; - } + if (!rte_kvargs_count(kvlist, key)) + goto out; - if (rte_kvargs_process(kvlist, key, - check_devargs_handler, NULL) < 0) { - rte_kvargs_free(kvlist); - return 0; - } + ret = rte_kvargs_process(kvlist, key, check_devargs_handler, p); + +out: rte_kvargs_free(kvlist); - return 1; + return ret; +} + +static void cxgbe_get_devargs_int(struct adapter *adap, bool *dst, + const char *key, bool default_value) +{ + struct rte_pci_device *pdev = adap->pdev; + int ret; + bool devarg_value = default_value; + + *dst = default_value; + if (!pdev) + return; + + ret = cxgbe_get_devargs(pdev->device.devargs, key, &devarg_value); + if (ret) + return; + + *dst = devarg_value; +} + +void cxgbe_process_devargs(struct adapter *adap) +{ + cxgbe_get_devargs_int(adap, &adap->devargs.keep_ovlan, + CXGBE_DEVARG_CMN_KEEP_OVLAN, false); + cxgbe_get_devargs_int(adap, &adap->devargs.tx_mode_latency, + CXGBE_DEVARG_CMN_TX_MODE_LATENCY, false); + cxgbe_get_devargs_int(adap, &adap->devargs.force_link_up, + CXGBE_DEVARG_VF_FORCE_LINK_UP, false); } static void configure_vlan_types(struct adapter *adapter) { - struct rte_pci_device *pdev = adapter->pdev; int i; for_each_port(adapter, i) { @@ -723,12 +759,6 @@ static void configure_vlan_types(struct adapter *adapter) V_OVLAN_ETYPE(M_OVLAN_ETYPE), V_OVLAN_MASK(M_OVLAN_MASK) | V_OVLAN_ETYPE(0x9100)); - /* OVLAN Type 0x8100 */ - t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN2), - V_OVLAN_MASK(M_OVLAN_MASK) | - V_OVLAN_ETYPE(M_OVLAN_ETYPE), - V_OVLAN_MASK(M_OVLAN_MASK) | - V_OVLAN_ETYPE(0x8100)); /* IVLAN 0X8100 */ t4_set_reg_field(adapter, MPS_PORT_RX_IVLAN(i), @@ -737,14 +767,13 @@ static void configure_vlan_types(struct adapter *adapter) t4_set_reg_field(adapter, MPS_PORT_RX_CTL(i), F_OVLAN_EN0 | F_OVLAN_EN1 | - F_OVLAN_EN2 | F_IVLAN_EN, + F_IVLAN_EN, F_OVLAN_EN0 | F_OVLAN_EN1 | - F_OVLAN_EN2 | F_IVLAN_EN); + F_IVLAN_EN); } - if (cxgbe_get_devargs(pdev->device.devargs, CXGBE_DEVARG_KEEP_OVLAN)) - t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG, - V_RM_OVLAN(1), V_RM_OVLAN(0)); + t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG, V_RM_OVLAN(1), + V_RM_OVLAN(!adapter->devargs.keep_ovlan)); } static void configure_pcie_ext_tag(struct adapter *adapter) @@ -1134,20 +1163,10 @@ static int adap_init0(struct adapter *adap) /* * Grab some of our basic fundamental operating parameters. */ -#define FW_PARAM_DEV(param) \ - (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ - V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) - -#define FW_PARAM_PFVF(param) \ - (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ - V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) | \ - V_FW_PARAMS_PARAM_Y(0) | \ - V_FW_PARAMS_PARAM_Z(0)) - - params[0] = FW_PARAM_PFVF(L2T_START); - params[1] = FW_PARAM_PFVF(L2T_END); - params[2] = FW_PARAM_PFVF(FILTER_START); - params[3] = FW_PARAM_PFVF(FILTER_END); + params[0] = CXGBE_FW_PARAM_PFVF(L2T_START); + params[1] = CXGBE_FW_PARAM_PFVF(L2T_END); + params[2] = CXGBE_FW_PARAM_PFVF(FILTER_START); + params[3] = CXGBE_FW_PARAM_PFVF(FILTER_END); ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 4, params, val); if (ret < 0) goto bye; @@ -1156,8 +1175,8 @@ static int adap_init0(struct adapter *adap) adap->tids.ftid_base = val[2]; adap->tids.nftids = val[3] - val[2] + 1; - params[0] = FW_PARAM_PFVF(CLIP_START); - params[1] = FW_PARAM_PFVF(CLIP_END); + params[0] = CXGBE_FW_PARAM_PFVF(CLIP_START); + params[1] = CXGBE_FW_PARAM_PFVF(CLIP_END); ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); if (ret < 0) goto bye; @@ -1187,14 +1206,23 @@ static int adap_init0(struct adapter *adap) if (is_t4(adap->params.chip)) { adap->params.filter2_wr_support = 0; } else { - params[0] = FW_PARAM_DEV(FILTER2_WR); + params[0] = CXGBE_FW_PARAM_DEV(FILTER2_WR); ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, val); adap->params.filter2_wr_support = (ret == 0 && val[0] != 0); } + /* Check if FW supports returning vin. + * If this is not supported, driver will interpret + * these values from viid. + */ + params[0] = CXGBE_FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN); + ret = t4_query_params(adap, adap->mbox, adap->pf, 0, + 1, params, val); + adap->params.viid_smt_extn_support = (ret == 0 && val[0] != 0); + /* query tid-related parameters */ - params[0] = FW_PARAM_DEV(NTID); + params[0] = CXGBE_FW_PARAM_DEV(NTID); ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, val); if (ret < 0) @@ -1207,7 +1235,7 @@ static int adap_init0(struct adapter *adap) * firmware won't understand this and we'll just get * unencapsulated messages ... */ - params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); + params[0] = CXGBE_FW_PARAM_PFVF(CPLFW4MSG_ENCAP); val[0] = 1; (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val); @@ -1220,12 +1248,20 @@ static int adap_init0(struct adapter *adap) if (is_t4(adap->params.chip)) { adap->params.ulptx_memwrite_dsgl = false; } else { - params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL); + params[0] = CXGBE_FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL); ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, val); adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0); } + /* Query for max number of packets that can be coalesced for Tx */ + params[0] = CXGBE_FW_PARAM_PFVF(MAX_PKTS_PER_ETH_TX_PKTS_WR); + ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, val); + if (!ret && val[0] > 0) + adap->params.max_tx_coalesce_num = val[0]; + else + adap->params.max_tx_coalesce_num = ETH_COALESCE_PKT_NUM; + /* * The MTU/MSS Table is initialized by now, so load their values. If * we're initializing the adapter, then we'll make any modifications @@ -1323,14 +1359,10 @@ void t4_os_portmod_changed(const struct adapter *adap, int port_id) bool cxgbe_force_linkup(struct adapter *adap) { - struct rte_pci_device *pdev = adap->pdev; - if (is_pf4(adap)) - return false; /* force_linkup not required for pf driver*/ - if (!cxgbe_get_devargs(pdev->device.devargs, - CXGBE_DEVARG_FORCE_LINK_UP)) - return false; - return true; + return false; /* force_linkup not required for pf driver */ + + return adap->devargs.force_link_up; } /** @@ -1708,6 +1740,7 @@ void cxgbe_close(struct adapter *adapter) t4_cleanup_mpstcam(adapter); t4_cleanup_clip_tbl(adapter); t4_cleanup_l2t(adapter); + t4_cleanup_smt(adapter); if (is_pf4(adapter)) t4_intr_disable(adapter); t4_sge_tx_monitor_stop(adapter); @@ -1726,13 +1759,45 @@ void cxgbe_close(struct adapter *adapter) t4_fw_bye(adapter, adapter->mbox); } +static void adap_smt_index(struct adapter *adapter, u32 *smt_start_idx, + u32 *smt_size) +{ + u32 params[2], smt_val[2]; + int ret; + + params[0] = CXGBE_FW_PARAM_PFVF(GET_SMT_START); + params[1] = CXGBE_FW_PARAM_PFVF(GET_SMT_SIZE); + + ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, + 2, params, smt_val); + + /* if FW doesn't recognize this command then set it to default setting + * which is start index as 0 and size as 256. + */ + if (ret < 0) { + *smt_start_idx = 0; + *smt_size = SMT_SIZE; + } else { + *smt_start_idx = smt_val[0]; + /* smt size can be zero, if nsmt is not yet configured in + * the config file or set as zero, then configure all the + * remaining entries to this PF itself. + */ + if (!smt_val[1]) + *smt_size = SMT_SIZE - *smt_start_idx; + else + *smt_size = smt_val[1]; + } +} + int cxgbe_probe(struct adapter *adapter) { + u32 smt_start_idx, smt_size; struct port_info *pi; - int chip; int func, i; int err = 0; u32 whoami; + int chip; whoami = t4_read_reg(adapter, A_PL_WHOAMI); chip = t4_get_chip_type(adapter, @@ -1877,6 +1942,11 @@ allocate_mac: dev_warn(adapter, "could not allocate CLIP. Continuing\n"); } + adap_smt_index(adapter, &smt_start_idx, &smt_size); + adapter->smt = t4_init_smt(smt_start_idx, smt_size); + if (!adapter->smt) + dev_warn(adapter, "could not allocate SMT, continuing\n"); + adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end); if (!adapter->l2t) { /* We tolerate a lack of L2T, giving up some functionality */ @@ -1889,6 +1959,8 @@ allocate_mac: "filter support disabled. Continuing\n"); } + t4_os_lock_init(&adapter->flow_lock); + adapter->mpstcam = t4_init_mpstcam(adapter); if (!adapter->mpstcam) dev_warn(adapter, "could not allocate mps tcam table."