X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fcxgbe%2Fcxgbe_main.c;h=f1ac322709619a6e552f4f9753fb90a8682f0beb;hb=9fda31c3229ca6e036cae80392578ed6e5a51119;hp=3b56eccfbe8e3cb9b35746fcfe3adb18d48afccd;hpb=a83041b1e998cda085b90e9bb744dd2e72874160;p=dpdk.git diff --git a/drivers/net/cxgbe/cxgbe_main.c b/drivers/net/cxgbe/cxgbe_main.c index 3b56eccfbe..f1ac322709 100644 --- a/drivers/net/cxgbe/cxgbe_main.c +++ b/drivers/net/cxgbe/cxgbe_main.c @@ -20,15 +20,14 @@ #include #include #include -#include #include #include #include #include #include #include -#include -#include +#include +#include #include #include #include @@ -417,13 +416,15 @@ void cxgbe_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid, if (t->tid_tab[tid]) { t->tid_tab[tid] = NULL; - rte_atomic32_dec(&t->conns_in_use); + __atomic_sub_fetch(&t->conns_in_use, 1, __ATOMIC_RELAXED); if (t->hash_base && tid >= t->hash_base) { if (family == FILTER_TYPE_IPV4) - rte_atomic32_dec(&t->hash_tids_in_use); + __atomic_sub_fetch(&t->hash_tids_in_use, 1, + __ATOMIC_RELAXED); } else { if (family == FILTER_TYPE_IPV4) - rte_atomic32_dec(&t->tids_in_use); + __atomic_sub_fetch(&t->tids_in_use, 1, + __ATOMIC_RELAXED); } } @@ -445,13 +446,15 @@ void cxgbe_insert_tid(struct tid_info *t, void *data, unsigned int tid, t->tid_tab[tid] = data; if (t->hash_base && tid >= t->hash_base) { if (family == FILTER_TYPE_IPV4) - rte_atomic32_inc(&t->hash_tids_in_use); + __atomic_add_fetch(&t->hash_tids_in_use, 1, + __ATOMIC_RELAXED); } else { if (family == FILTER_TYPE_IPV4) - rte_atomic32_inc(&t->tids_in_use); + __atomic_add_fetch(&t->tids_in_use, 1, + __ATOMIC_RELAXED); } - rte_atomic32_inc(&t->conns_in_use); + __atomic_add_fetch(&t->conns_in_use, 1, __ATOMIC_RELAXED); } /** @@ -504,10 +507,8 @@ static int tid_init(struct tid_info *t) t->afree = NULL; t->atids_in_use = 0; - rte_atomic32_init(&t->tids_in_use); - rte_atomic32_set(&t->tids_in_use, 0); - rte_atomic32_init(&t->conns_in_use); - rte_atomic32_set(&t->conns_in_use, 0); + t->tids_in_use = 0; + t->conns_in_use = 0; /* Setup the free list for atid_tab and clear the stid bitmap. */ if (natids) { @@ -1496,6 +1497,24 @@ static int adap_init0(struct adapter *adap) else adap->params.max_tx_coalesce_num = ETH_COALESCE_PKT_NUM; + params[0] = CXGBE_FW_PARAM_DEV(VI_ENABLE_INGRESS_AFTER_LINKUP); + ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, val); + adap->params.vi_enable_rx = (ret == 0 && val[0] != 0); + + /* Read the RAW MPS entries. In T6, the last 2 TCAM entries + * are reserved for RAW MAC addresses (rawf = 2, one per port). + */ + if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) { + params[0] = CXGBE_FW_PARAM_PFVF(RAWF_START); + params[1] = CXGBE_FW_PARAM_PFVF(RAWF_END); + ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, + params, val); + if (ret == 0) { + adap->params.rawf_start = val[0]; + adap->params.rawf_size = val[1] - val[0] + 1; + } + } + /* * The MTU/MSS Table is initialized by now, so load their values. If * we're initializing the adapter, then we'll make any modifications @@ -1594,6 +1613,33 @@ void t4_os_portmod_changed(const struct adapter *adap, int port_id) pi->port_id, pi->link_cfg.mod_type); } +void t4_os_link_changed(struct adapter *adap, int port_id) +{ + struct port_info *pi = adap2pinfo(adap, port_id); + + /* If link status has not changed or if firmware doesn't + * support enabling/disabling VI's Rx path during runtime, + * then return. + */ + if (adap->params.vi_enable_rx == 0 || + pi->vi_en_rx == pi->link_cfg.link_ok) + return; + + /* Don't enable VI Rx path, if link has been administratively + * turned off. + */ + if (pi->vi_en_tx == 0 && pi->vi_en_rx == 0) + return; + + /* When link goes down, disable the port's Rx path to drop + * Rx traffic closer to the wire, instead of processing it + * further in the Rx pipeline. The Rx path will be re-enabled + * once the link up message comes in firmware event queue. + */ + pi->vi_en_rx = pi->link_cfg.link_ok; + t4_enable_vi(adap, adap->mbox, pi->viid, pi->vi_en_rx, pi->vi_en_tx); +} + bool cxgbe_force_linkup(struct adapter *adap) { if (is_pf4(adap)) @@ -1615,8 +1661,7 @@ int cxgbe_link_start(struct port_info *pi) unsigned int mtu; int ret; - mtu = pi->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len - - (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN); + mtu = pi->eth_dev->data->mtu; conf_offloads = pi->eth_dev->data->dev_conf.rxmode.offloads; @@ -1625,7 +1670,7 @@ int cxgbe_link_start(struct port_info *pi) * that step explicitly. */ ret = t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, -1, -1, -1, - !!(conf_offloads & DEV_RX_OFFLOAD_VLAN_STRIP), + !!(conf_offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP), true); if (ret == 0) { ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt, @@ -1638,19 +1683,18 @@ int cxgbe_link_start(struct port_info *pi) if (ret == 0 && is_pf4(adapter)) ret = t4_link_l1cfg(pi, pi->link_cfg.admin_caps); if (ret == 0) { - /* - * Enabling a Virtual Interface can result in an interrupt - * during the processing of the VI Enable command and, in some - * paths, result in an attempt to issue another command in the - * interrupt context. Thus, we disable interrupts during the - * course of the VI Enable command ... + /* Disable VI Rx until link up message is received in + * firmware event queue, if firmware supports enabling/ + * disabling VI Rx at runtime. */ + pi->vi_en_rx = adapter->params.vi_enable_rx ? 0 : 1; + pi->vi_en_tx = 1; ret = t4_enable_vi_params(adapter, adapter->mbox, pi->viid, - true, true, false); + pi->vi_en_rx, pi->vi_en_tx, false); } if (ret == 0 && cxgbe_force_linkup(adapter)) - pi->eth_dev->data->dev_link.link_status = ETH_LINK_UP; + pi->eth_dev->data->dev_link.link_status = RTE_ETH_LINK_UP; return ret; } @@ -1681,10 +1725,10 @@ int cxgbe_write_rss_conf(const struct port_info *pi, uint64_t rss_hf) if (rss_hf & CXGBE_RSS_HF_IPV4_MASK) flags |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN; - if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) + if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_TCP) flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; - if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) + if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_UDP) flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN; @@ -1821,7 +1865,7 @@ static void fw_caps_to_speed_caps(enum fw_port_type port_type, { #define SET_SPEED(__speed_name) \ do { \ - *speed_caps |= ETH_LINK_ ## __speed_name; \ + *speed_caps |= RTE_ETH_LINK_ ## __speed_name; \ } while (0) #define FW_CAPS_TO_SPEED(__fw_name) \ @@ -1908,7 +1952,7 @@ void cxgbe_get_speed_caps(struct port_info *pi, u32 *speed_caps) speed_caps); if (!(pi->link_cfg.pcaps & FW_PORT_CAP32_ANEG)) - *speed_caps |= ETH_LINK_SPEED_FIXED; + *speed_caps |= RTE_ETH_LINK_SPEED_FIXED; } /** @@ -1923,7 +1967,13 @@ int cxgbe_set_link_status(struct port_info *pi, bool status) struct adapter *adapter = pi->adapter; int err = 0; - err = t4_enable_vi(adapter, adapter->mbox, pi->viid, status, status); + /* Wait for link up message from firmware to enable Rx path, + * if firmware supports enabling/disabling VI Rx at runtime. + */ + pi->vi_en_rx = adapter->params.vi_enable_rx ? 0 : status; + pi->vi_en_tx = status; + err = t4_enable_vi(adapter, adapter->mbox, pi->viid, pi->vi_en_rx, + pi->vi_en_tx); if (err) { dev_err(adapter, "%s: disable_vi failed: %d\n", __func__, err); return err;