X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fdpaa%2Fdpaa_ethdev.h;h=659bceb46748406b15fa61163faf2f662c2a0d21;hb=f593944fc988dfccebed62205fd0b88c60ed7d77;hp=a980262e626a21367dd69d9774115d6a998bf263;hpb=cf0fab1d2ca50b48bdca8914f7bdcfc32ca770e8;p=dpdk.git diff --git a/drivers/net/dpaa/dpaa_ethdev.h b/drivers/net/dpaa/dpaa_ethdev.h index a980262e62..659bceb467 100644 --- a/drivers/net/dpaa/dpaa_ethdev.h +++ b/drivers/net/dpaa/dpaa_ethdev.h @@ -1,60 +1,27 @@ -/*- - * BSD LICENSE +/* SPDX-License-Identifier: BSD-3-Clause * * Copyright (c) 2014-2016 Freescale Semiconductor, Inc. All rights reserved. - * Copyright 2017 NXP. + * Copyright 2017-2019 NXP * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Freescale Semiconductor, Inc nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __DPAA_ETHDEV_H__ #define __DPAA_ETHDEV_H__ /* System headers */ #include -#include +#include +#include #include #include #include -#include +#include #include -/* DPAA SoC identifier; If this is not available, it can be concluded - * that board is non-DPAA. Single slot is currently supported. - */ -#define DPAA_SOC_ID_FILE "sys/devices/soc0/soc_id" - +#define MAX_DPAA_CORES 4 #define DPAA_MBUF_HW_ANNOTATION 64 #define DPAA_FD_PTA_SIZE 64 -#if (DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) > RTE_PKTMBUF_HEADROOM -#error "Annotation requirement is more than RTE_PKTMBUF_HEADROOM" -#endif - /* we will re-use the HEADROOM for annotation in RX */ #define DPAA_HW_BUF_RESERVE 0 #define DPAA_PACKET_LAYOUT_ALIGN 64 @@ -62,27 +29,36 @@ /* Alignment to use for cpu-local structs to avoid coherency problems. */ #define MAX_CACHELINE 64 -#define DPAA_MIN_RX_BUF_SIZE 512 #define DPAA_MAX_RX_PKT_LEN 10240 -/* RX queue tail drop threshold - * currently considering 32 KB packets. - */ -#define CONG_THRESHOLD_RX_Q (32 * 1024) +#define DPAA_SGT_MAX_ENTRIES 16 /* maximum number of entries in SG Table */ + +/* RX queue tail drop threshold (CGR Based) in frame count */ +#define CGR_RX_PERFQ_THRESH 256 +#define CGR_TX_CGR_THRESH 512 /*max mac filter for memac(8) including primary mac addr*/ #define DPAA_MAX_MAC_FILTER (MEMAC_NUM_OF_PADDRS + 1) /*Maximum number of slots available in TX ring*/ -#define MAX_TX_RING_SLOTS 8 +#define DPAA_TX_BURST_SIZE 7 + +/* Optimal burst size for RX and TX as default */ +#define DPAA_DEF_RX_BURST_SIZE 7 +#define DPAA_DEF_TX_BURST_SIZE DPAA_TX_BURST_SIZE + +#ifndef VLAN_TAG_SIZE +#define VLAN_TAG_SIZE 4 /** < Vlan Header Length */ +#endif /* PCD frame queues */ -#define DPAA_PCD_FQID_START 0x400 -#define DPAA_PCD_FQID_MULTIPLIER 0x100 #define DPAA_DEFAULT_NUM_PCD_QUEUES 1 +#define DPAA_VSP_PROFILE_MAX_NUM 8 +#define DPAA_MAX_NUM_PCD_QUEUES DPAA_VSP_PROFILE_MAX_NUM +/*Same as VSP profile number*/ #define DPAA_IF_TX_PRIORITY 3 -#define DPAA_IF_RX_PRIORITY 4 +#define DPAA_IF_RX_PRIORITY 0 #define DPAA_IF_DEBUG_PRIORITY 7 #define DPAA_IF_RX_ANNOTATION_STASH 1 @@ -94,14 +70,11 @@ #define DPAA_DEBUG_FQ_TX_ERROR 1 #define DPAA_RSS_OFFLOAD_ALL ( \ - ETH_RSS_FRAG_IPV4 | \ - ETH_RSS_NONFRAG_IPV4_TCP | \ - ETH_RSS_NONFRAG_IPV4_UDP | \ - ETH_RSS_NONFRAG_IPV4_SCTP | \ - ETH_RSS_FRAG_IPV6 | \ - ETH_RSS_NONFRAG_IPV6_TCP | \ - ETH_RSS_NONFRAG_IPV6_UDP | \ - ETH_RSS_NONFRAG_IPV6_SCTP) + ETH_RSS_L2_PAYLOAD | \ + ETH_RSS_IP | \ + ETH_RSS_UDP | \ + ETH_RSS_TCP | \ + ETH_RSS_SCTP) #define DPAA_TX_CKSUM_OFFLOAD_MASK ( \ PKT_TX_IP_CKSUM | \ @@ -123,20 +96,119 @@ #define DPAA_FD_CMD_CFQ 0x00ffffff /**< Confirmation Frame Queue */ +#define DPAA_DEFAULT_RXQ_VSP_ID 1 + +#define FMC_FILE "/tmp/fmc.bin" + /* Each network interface is represented by one of these */ struct dpaa_if { int valid; char *name; const struct fm_eth_port_cfg *cfg; struct qman_fq *rx_queues; + struct qman_cgr *cgr_rx; struct qman_fq *tx_queues; + struct qman_cgr *cgr_tx; struct qman_fq debug_queues[2]; uint16_t nb_rx_queues; uint16_t nb_tx_queues; uint32_t ifid; - struct fman_if *fif; struct dpaa_bp_info *bp_info; struct rte_eth_fc_conf *fc_conf; + void *port_handle; + void *netenv_handle; + void *scheme_handle[2]; + uint32_t scheme_count; + + void *vsp_handle[DPAA_VSP_PROFILE_MAX_NUM]; + uint32_t vsp_bpid[DPAA_VSP_PROFILE_MAX_NUM]; +}; + +struct dpaa_if_stats { + /* Rx Statistics Counter */ + uint64_t reoct; /**>") + +#define DPAA_PMD_DEBUG(fmt, args...) \ + DPAA_PMD_LOG(DEBUG, fmt, ## args) +#define DPAA_PMD_ERR(fmt, args...) \ + DPAA_PMD_LOG(ERR, fmt, ## args) +#define DPAA_PMD_INFO(fmt, args...) \ + DPAA_PMD_LOG(INFO, fmt, ## args) +#define DPAA_PMD_WARN(fmt, args...) \ + DPAA_PMD_LOG(WARNING, fmt, ## args) + +/* DP Logs, toggled out at compile time if level lower than current level */ +#define DPAA_DP_LOG(level, fmt, args...) \ + RTE_LOG_DP(level, PMD, fmt, ## args) + #endif