X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fdpaa%2Fdpaa_ethdev.h;h=b5728e09c29f72686118b9eb5ae2fc9c74639a68;hb=953e74e6b73a876d6f149fd759bd0423e5438247;hp=182becac18a69e905ade75a78a113c2130e64391;hpb=8c83f28cc8a4dc7ee0fab676051dd483695d4140;p=dpdk.git diff --git a/drivers/net/dpaa/dpaa_ethdev.h b/drivers/net/dpaa/dpaa_ethdev.h index 182becac18..b5728e09c2 100644 --- a/drivers/net/dpaa/dpaa_ethdev.h +++ b/drivers/net/dpaa/dpaa_ethdev.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-3-Clause * * Copyright (c) 2014-2016 Freescale Semiconductor, Inc. All rights reserved. - * Copyright 2017 NXP + * Copyright 2017-2019 NXP * */ #ifndef __DPAA_ETHDEV_H__ @@ -9,7 +9,7 @@ /* System headers */ #include -#include +#include #include #include @@ -22,13 +22,6 @@ #define DPAA_MBUF_HW_ANNOTATION 64 #define DPAA_FD_PTA_SIZE 64 -/* mbuf->seqn will be used to store event entry index for - * driver specific usage. For parallel mode queues, invalid - * index will be set and for atomic mode queues, valid value - * ranging from 1 to 16. - */ -#define DPAA_INVALID_MBUF_SEQN 0 - /* we will re-use the HEADROOM for annotation in RX */ #define DPAA_HW_BUF_RESERVE 0 #define DPAA_PACKET_LAYOUT_ALIGN 64 @@ -42,6 +35,7 @@ /* RX queue tail drop threshold (CGR Based) in frame count */ #define CGR_RX_PERFQ_THRESH 256 +#define CGR_TX_CGR_THRESH 512 /*max mac filter for memac(8) including primary mac addr*/ #define DPAA_MAX_MAC_FILTER (MEMAC_NUM_OF_PADDRS + 1) @@ -57,11 +51,15 @@ #define VLAN_TAG_SIZE 4 /** < Vlan Header Length */ #endif +#define DPAA_ETH_MAX_LEN (RTE_ETHER_MTU + \ + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + \ + VLAN_TAG_SIZE) + /* PCD frame queues */ -#define DPAA_PCD_FQID_START 0x400 -#define DPAA_PCD_FQID_MULTIPLIER 0x100 #define DPAA_DEFAULT_NUM_PCD_QUEUES 1 -#define DPAA_MAX_NUM_PCD_QUEUES 4 +#define DPAA_VSP_PROFILE_MAX_NUM 8 +#define DPAA_MAX_NUM_PCD_QUEUES DPAA_VSP_PROFILE_MAX_NUM +/*Same as VSP profile number*/ #define DPAA_IF_TX_PRIORITY 3 #define DPAA_IF_RX_PRIORITY 0 @@ -76,14 +74,11 @@ #define DPAA_DEBUG_FQ_TX_ERROR 1 #define DPAA_RSS_OFFLOAD_ALL ( \ - ETH_RSS_FRAG_IPV4 | \ - ETH_RSS_NONFRAG_IPV4_TCP | \ - ETH_RSS_NONFRAG_IPV4_UDP | \ - ETH_RSS_NONFRAG_IPV4_SCTP | \ - ETH_RSS_FRAG_IPV6 | \ - ETH_RSS_NONFRAG_IPV6_TCP | \ - ETH_RSS_NONFRAG_IPV6_UDP | \ - ETH_RSS_NONFRAG_IPV6_SCTP) + ETH_RSS_L2_PAYLOAD | \ + ETH_RSS_IP | \ + ETH_RSS_UDP | \ + ETH_RSS_TCP | \ + ETH_RSS_SCTP) #define DPAA_TX_CKSUM_OFFLOAD_MASK ( \ PKT_TX_IP_CKSUM | \ @@ -105,6 +100,10 @@ #define DPAA_FD_CMD_CFQ 0x00ffffff /**< Confirmation Frame Queue */ +#define DPAA_DEFAULT_RXQ_VSP_ID 1 + +#define FMC_FILE "/tmp/fmc.bin" + /* Each network interface is represented by one of these */ struct dpaa_if { int valid; @@ -113,13 +112,20 @@ struct dpaa_if { struct qman_fq *rx_queues; struct qman_cgr *cgr_rx; struct qman_fq *tx_queues; + struct qman_cgr *cgr_tx; struct qman_fq debug_queues[2]; uint16_t nb_rx_queues; uint16_t nb_tx_queues; uint32_t ifid; - struct fman_if *fif; struct dpaa_bp_info *bp_info; struct rte_eth_fc_conf *fc_conf; + void *port_handle; + void *netenv_handle; + void *scheme_handle[2]; + uint32_t scheme_count; + + void *vsp_handle[DPAA_VSP_PROFILE_MAX_NUM]; + uint32_t vsp_bpid[DPAA_VSP_PROFILE_MAX_NUM]; }; struct dpaa_if_stats { @@ -162,12 +168,14 @@ struct dpaa_if_stats { uint64_t tund; /**>") + +#define DPAA_PMD_DEBUG(fmt, args...) \ + DPAA_PMD_LOG(DEBUG, fmt, ## args) +#define DPAA_PMD_ERR(fmt, args...) \ + DPAA_PMD_LOG(ERR, fmt, ## args) +#define DPAA_PMD_INFO(fmt, args...) \ + DPAA_PMD_LOG(INFO, fmt, ## args) +#define DPAA_PMD_WARN(fmt, args...) \ + DPAA_PMD_LOG(WARNING, fmt, ## args) + +/* DP Logs, toggled out at compile time if level lower than current level */ +#define DPAA_DP_LOG(level, fmt, args...) \ + RTE_LOG_DP(level, PMD, fmt, ## args) + #endif