X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fdpaa2%2Fdpaa2_ethdev.c;h=73d17f7b3c61bac25b0f96fb907be9793413c1a6;hb=d61138d4f0e2927cc1d0fef6d810fa7f5d1161a1;hp=7bd3208a19dd2aa86150d360021979de65f3501b;hpb=5964d36a2904d7c887a1f5862760caf151bd7d6e;p=dpdk.git diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c index 7bd3208a19..73d17f7b3c 100644 --- a/drivers/net/dpaa2/dpaa2_ethdev.c +++ b/drivers/net/dpaa2/dpaa2_ethdev.c @@ -1,7 +1,7 @@ /* * SPDX-License-Identifier: BSD-3-Clause * * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved. - * Copyright 2016-2020 NXP + * Copyright 2016-2021 NXP * */ @@ -9,7 +9,7 @@ #include #include -#include +#include #include #include #include @@ -31,40 +31,48 @@ #define DRIVER_LOOPBACK_MODE "drv_loopback" #define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch" +#define DRIVER_TX_CONF "drv_tx_conf" +#define DRIVER_ERROR_QUEUE "drv_err_queue" +#define CHECK_INTERVAL 100 /* 100ms */ +#define MAX_REPEAT_TIME 90 /* 9s (90 * 100ms) in total */ /* Supported Rx offloads */ static uint64_t dev_rx_offloads_sup = - DEV_RX_OFFLOAD_CHECKSUM | - DEV_RX_OFFLOAD_SCTP_CKSUM | - DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | - DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | - DEV_RX_OFFLOAD_VLAN_STRIP | - DEV_RX_OFFLOAD_VLAN_FILTER | - DEV_RX_OFFLOAD_JUMBO_FRAME | - DEV_RX_OFFLOAD_TIMESTAMP; + RTE_ETH_RX_OFFLOAD_CHECKSUM | + RTE_ETH_RX_OFFLOAD_SCTP_CKSUM | + RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM | + RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM | + RTE_ETH_RX_OFFLOAD_VLAN_STRIP | + RTE_ETH_RX_OFFLOAD_VLAN_FILTER | + RTE_ETH_RX_OFFLOAD_TIMESTAMP; /* Rx offloads which cannot be disabled */ static uint64_t dev_rx_offloads_nodis = - DEV_RX_OFFLOAD_RSS_HASH | - DEV_RX_OFFLOAD_SCATTER; + RTE_ETH_RX_OFFLOAD_RSS_HASH | + RTE_ETH_RX_OFFLOAD_SCATTER; /* Supported Tx offloads */ static uint64_t dev_tx_offloads_sup = - DEV_TX_OFFLOAD_VLAN_INSERT | - DEV_TX_OFFLOAD_IPV4_CKSUM | - DEV_TX_OFFLOAD_UDP_CKSUM | - DEV_TX_OFFLOAD_TCP_CKSUM | - DEV_TX_OFFLOAD_SCTP_CKSUM | - DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | - DEV_TX_OFFLOAD_MT_LOCKFREE | - DEV_TX_OFFLOAD_MBUF_FAST_FREE; + RTE_ETH_TX_OFFLOAD_VLAN_INSERT | + RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | + RTE_ETH_TX_OFFLOAD_UDP_CKSUM | + RTE_ETH_TX_OFFLOAD_TCP_CKSUM | + RTE_ETH_TX_OFFLOAD_SCTP_CKSUM | + RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | + RTE_ETH_TX_OFFLOAD_MT_LOCKFREE | + RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE; /* Tx offloads which cannot be disabled */ static uint64_t dev_tx_offloads_nodis = - DEV_TX_OFFLOAD_MULTI_SEGS; + RTE_ETH_TX_OFFLOAD_MULTI_SEGS; /* enable timestamp in mbuf */ bool dpaa2_enable_ts[RTE_MAX_ETHPORTS]; +uint64_t dpaa2_timestamp_rx_dynflag; +int dpaa2_timestamp_dynfield_offset = -1; + +/* Enable error queue */ +bool dpaa2_enable_err_queue; struct rte_dpaa2_xstats_name_off { char name[RTE_ETH_XSTATS_NAME_SIZE]; @@ -90,14 +98,6 @@ static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = { {"cgr_reject_bytes", 4, 1}, }; -static const enum rte_filter_op dpaa2_supported_filter_ops[] = { - RTE_ETH_FILTER_ADD, - RTE_ETH_FILTER_DELETE, - RTE_ETH_FILTER_UPDATE, - RTE_ETH_FILTER_FLUSH, - RTE_ETH_FILTER_GET -}; - static struct rte_dpaa2_driver rte_dpaa2_pmd; static int dpaa2_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete); @@ -142,7 +142,7 @@ dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask) PMD_INIT_FUNC_TRACE(); - if (mask & ETH_VLAN_FILTER_MASK) { + if (mask & RTE_ETH_VLAN_FILTER_MASK) { /* VLAN Filter not avaialble */ if (!priv->max_vlan_filters) { DPAA2_PMD_INFO("VLAN filter not available"); @@ -150,7 +150,7 @@ dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask) } if (dev->data->dev_conf.rxmode.offloads & - DEV_RX_OFFLOAD_VLAN_FILTER) + RTE_ETH_RX_OFFLOAD_VLAN_FILTER) ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW, priv->token, true); else @@ -225,9 +225,11 @@ dpaa2_fw_version_get(struct rte_eth_dev *dev, mc_ver_info.major, mc_ver_info.minor, mc_ver_info.revision); + if (ret < 0) + return -EINVAL; ret += 1; /* add the size of '\0' */ - if (fw_size < (uint32_t)ret) + if (fw_size < (size_t)ret) return ret; else return 0; @@ -249,13 +251,13 @@ dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) dev_rx_offloads_nodis; dev_info->tx_offload_capa = dev_tx_offloads_sup | dev_tx_offloads_nodis; - dev_info->speed_capa = ETH_LINK_SPEED_1G | - ETH_LINK_SPEED_2_5G | - ETH_LINK_SPEED_10G; + dev_info->speed_capa = RTE_ETH_LINK_SPEED_1G | + RTE_ETH_LINK_SPEED_2_5G | + RTE_ETH_LINK_SPEED_10G; dev_info->max_hash_mac_addrs = 0; dev_info->max_vfs = 0; - dev_info->max_vmdq_pools = ETH_16_POOLS; + dev_info->max_vmdq_pools = RTE_ETH_16_POOLS; dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL; dev_info->default_rxportconf.burst_size = dpaa2_dqrr_size; @@ -268,10 +270,10 @@ dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) dev_info->default_rxportconf.ring_size = DPAA2_RX_DEFAULT_NBDESC; if (dpaa2_svr_family == SVR_LX2160A) { - dev_info->speed_capa |= ETH_LINK_SPEED_25G | - ETH_LINK_SPEED_40G | - ETH_LINK_SPEED_50G | - ETH_LINK_SPEED_100G; + dev_info->speed_capa |= RTE_ETH_LINK_SPEED_25G | + RTE_ETH_LINK_SPEED_40G | + RTE_ETH_LINK_SPEED_50G | + RTE_ETH_LINK_SPEED_100G; } return 0; @@ -289,16 +291,15 @@ dpaa2_dev_rx_burst_mode_get(struct rte_eth_dev *dev, uint64_t flags; const char *output; } rx_offload_map[] = { - {DEV_RX_OFFLOAD_CHECKSUM, " Checksum,"}, - {DEV_RX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"}, - {DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, - {DEV_RX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP csum,"}, - {DEV_RX_OFFLOAD_VLAN_STRIP, " VLAN strip,"}, - {DEV_RX_OFFLOAD_VLAN_FILTER, " VLAN filter,"}, - {DEV_RX_OFFLOAD_JUMBO_FRAME, " Jumbo frame,"}, - {DEV_RX_OFFLOAD_TIMESTAMP, " Timestamp,"}, - {DEV_RX_OFFLOAD_RSS_HASH, " RSS,"}, - {DEV_RX_OFFLOAD_SCATTER, " Scattered,"} + {RTE_ETH_RX_OFFLOAD_CHECKSUM, " Checksum,"}, + {RTE_ETH_RX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"}, + {RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, + {RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP csum,"}, + {RTE_ETH_RX_OFFLOAD_VLAN_STRIP, " VLAN strip,"}, + {RTE_ETH_RX_OFFLOAD_VLAN_FILTER, " VLAN filter,"}, + {RTE_ETH_RX_OFFLOAD_TIMESTAMP, " Timestamp,"}, + {RTE_ETH_RX_OFFLOAD_RSS_HASH, " RSS,"}, + {RTE_ETH_RX_OFFLOAD_SCATTER, " Scattered,"} }; /* Update Rx offload info */ @@ -325,15 +326,15 @@ dpaa2_dev_tx_burst_mode_get(struct rte_eth_dev *dev, uint64_t flags; const char *output; } tx_offload_map[] = { - {DEV_TX_OFFLOAD_VLAN_INSERT, " VLAN Insert,"}, - {DEV_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"}, - {DEV_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"}, - {DEV_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"}, - {DEV_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"}, - {DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, - {DEV_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"}, - {DEV_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"}, - {DEV_TX_OFFLOAD_MULTI_SEGS, " Scattered,"} + {RTE_ETH_TX_OFFLOAD_VLAN_INSERT, " VLAN Insert,"}, + {RTE_ETH_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"}, + {RTE_ETH_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"}, + {RTE_ETH_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"}, + {RTE_ETH_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"}, + {RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, + {RTE_ETH_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"}, + {RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"}, + {RTE_ETH_TX_OFFLOAD_MULTI_SEGS, " Scattered,"} }; /* Update Tx offload info */ @@ -363,7 +364,7 @@ dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev) PMD_INIT_FUNC_TRACE(); num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc); - if (priv->tx_conf_en) + if (priv->flags & DPAA2_TX_CONF_ENABLE) tot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues; else tot_queues = priv->nb_rx_queues + priv->nb_tx_queues; @@ -390,6 +391,25 @@ dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev) goto fail; } + if (dpaa2_enable_err_queue) { + priv->rx_err_vq = rte_zmalloc("dpni_rx_err", + sizeof(struct dpaa2_queue), 0); + + dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq; + dpaa2_q->q_storage = rte_malloc("err_dq_storage", + sizeof(struct queue_storage_info_t) * + RTE_MAX_LCORE, + RTE_CACHE_LINE_SIZE); + if (!dpaa2_q->q_storage) + goto fail; + + memset(dpaa2_q->q_storage, 0, + sizeof(struct queue_storage_info_t)); + for (i = 0; i < RTE_MAX_LCORE; i++) + if (dpaa2_alloc_dq_storage(&dpaa2_q->q_storage[i])) + goto fail; + } + for (i = 0; i < priv->nb_tx_queues; i++) { mc_q->eth_data = dev->data; mc_q->flow_id = 0xffff; @@ -401,7 +421,7 @@ dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev) goto fail_tx; } - if (priv->tx_conf_en) { + if (priv->flags & DPAA2_TX_CONF_ENABLE) { /*Setup tx confirmation queues*/ for (i = 0; i < priv->nb_tx_queues; i++) { mc_q->eth_data = dev->data; @@ -457,6 +477,14 @@ fail: rte_free(dpaa2_q->q_storage); priv->rx_vq[i--] = NULL; } + + if (dpaa2_enable_err_queue) { + dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq; + if (dpaa2_q->q_storage) + dpaa2_free_dq_storage(dpaa2_q->q_storage); + rte_free(dpaa2_q->q_storage); + } + rte_free(mc_q); return -1; } @@ -483,7 +511,7 @@ dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev) dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; rte_free(dpaa2_q->cscn); } - if (priv->tx_conf_en) { + if (priv->flags & DPAA2_TX_CONF_ENABLE) { /* cleanup tx conf queue storage */ for (i = 0; i < priv->nb_tx_queues; i++) { dpaa2_q = (struct dpaa2_queue *) @@ -510,6 +538,7 @@ dpaa2_eth_dev_configure(struct rte_eth_dev *dev) int tx_l3_csum_offload = false; int tx_l4_csum_offload = false; int ret, tc_index; + uint32_t max_rx_pktlen; PMD_INIT_FUNC_TRACE(); @@ -529,26 +558,22 @@ dpaa2_eth_dev_configure(struct rte_eth_dev *dev) tx_offloads, dev_tx_offloads_nodis); } - if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { - if (eth_conf->rxmode.max_rx_pkt_len <= DPAA2_MAX_RX_PKT_LEN) { - ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, - priv->token, eth_conf->rxmode.max_rx_pkt_len - - RTE_ETHER_CRC_LEN); - if (ret) { - DPAA2_PMD_ERR( - "Unable to set mtu. check config"); - return ret; - } - dev->data->mtu = - dev->data->dev_conf.rxmode.max_rx_pkt_len - - RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - - VLAN_TAG_SIZE; - } else { - return -1; + max_rx_pktlen = eth_conf->rxmode.mtu + RTE_ETHER_HDR_LEN + + RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE; + if (max_rx_pktlen <= DPAA2_MAX_RX_PKT_LEN) { + ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, + priv->token, max_rx_pktlen - RTE_ETHER_CRC_LEN); + if (ret != 0) { + DPAA2_PMD_ERR("Unable to set mtu. check config"); + return ret; } + DPAA2_PMD_INFO("MTU configured for the device: %d", + dev->data->mtu); + } else { + return -1; } - if (eth_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) { + if (eth_conf->rxmode.mq_mode == RTE_ETH_MQ_RX_RSS) { for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) { ret = dpaa2_setup_flow_dist(dev, eth_conf->rx_adv_conf.rss_conf.rss_hf, @@ -562,12 +587,12 @@ dpaa2_eth_dev_configure(struct rte_eth_dev *dev) } } - if (rx_offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) + if (rx_offloads & RTE_ETH_RX_OFFLOAD_IPV4_CKSUM) rx_l3_csum_offload = true; - if ((rx_offloads & DEV_RX_OFFLOAD_UDP_CKSUM) || - (rx_offloads & DEV_RX_OFFLOAD_TCP_CKSUM) || - (rx_offloads & DEV_RX_OFFLOAD_SCTP_CKSUM)) + if ((rx_offloads & RTE_ETH_RX_OFFLOAD_UDP_CKSUM) || + (rx_offloads & RTE_ETH_RX_OFFLOAD_TCP_CKSUM) || + (rx_offloads & RTE_ETH_RX_OFFLOAD_SCTP_CKSUM)) rx_l4_csum_offload = true; ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, @@ -585,16 +610,25 @@ dpaa2_eth_dev_configure(struct rte_eth_dev *dev) } #if !defined(RTE_LIBRTE_IEEE1588) - if (rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) + if (rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) #endif + { + ret = rte_mbuf_dyn_rx_timestamp_register( + &dpaa2_timestamp_dynfield_offset, + &dpaa2_timestamp_rx_dynflag); + if (ret != 0) { + DPAA2_PMD_ERR("Error to register timestamp field/flag"); + return -rte_errno; + } dpaa2_enable_ts[dev->data->port_id] = true; + } - if (tx_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM) + if (tx_offloads & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM) tx_l3_csum_offload = true; - if ((tx_offloads & DEV_TX_OFFLOAD_UDP_CKSUM) || - (tx_offloads & DEV_TX_OFFLOAD_TCP_CKSUM) || - (tx_offloads & DEV_TX_OFFLOAD_SCTP_CKSUM)) + if ((tx_offloads & RTE_ETH_TX_OFFLOAD_UDP_CKSUM) || + (tx_offloads & RTE_ETH_TX_OFFLOAD_TCP_CKSUM) || + (tx_offloads & RTE_ETH_TX_OFFLOAD_SCTP_CKSUM)) tx_l4_csum_offload = true; ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, @@ -626,8 +660,10 @@ dpaa2_eth_dev_configure(struct rte_eth_dev *dev) } } - if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) - dpaa2_vlan_offload_set(dev, ETH_VLAN_FILTER_MASK); + if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) + dpaa2_vlan_offload_set(dev, RTE_ETH_VLAN_FILTER_MASK); + + dpaa2_tm_init(dev); return 0; } @@ -846,7 +882,7 @@ dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev, if (tx_queue_id == 0) { /*Set tx-conf and error configuration*/ - if (priv->tx_conf_en) + if (priv->flags & DPAA2_TX_CONF_ENABLE) ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW, priv->token, DPNI_CONF_AFFINE); @@ -879,9 +915,9 @@ dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev, cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES; cong_notif_cfg.threshold_entry = nb_tx_desc; /* Notify that the queue is not congested when the data in - * the queue is below this thershold. + * the queue is below this thershold.(90% of value) */ - cong_notif_cfg.threshold_exit = nb_tx_desc - 24; + cong_notif_cfg.threshold_exit = (nb_tx_desc * 9) / 10; cong_notif_cfg.message_ctx = 0; cong_notif_cfg.message_iova = (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn); @@ -907,7 +943,7 @@ dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev, dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf; dev->data->tx_queues[tx_queue_id] = dpaa2_q; - if (priv->tx_conf_en) { + if (priv->flags & DPAA2_TX_CONF_ENABLE) { dpaa2_q->tx_conf_queue = dpaa2_tx_conf_q; options = options | DPNI_QUEUE_OPT_USER_CTX; tx_conf_cfg.user_context = (size_t)(dpaa2_q); @@ -935,9 +971,9 @@ dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev, } static void -dpaa2_dev_rx_queue_release(void *q __rte_unused) +dpaa2_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t rx_queue_id) { - struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)q; + struct dpaa2_queue *dpaa2_q = dev->data->rx_queues[rx_queue_id]; struct dpaa2_dev_priv *priv = dpaa2_q->eth_data->dev_private; struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->eth_dev->process_private; @@ -963,17 +999,10 @@ dpaa2_dev_rx_queue_release(void *q __rte_unused) } } -static void -dpaa2_dev_tx_queue_release(void *q __rte_unused) -{ - PMD_INIT_FUNC_TRACE(); -} - static uint32_t -dpaa2_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id) +dpaa2_dev_rx_queue_count(void *rx_queue) { int32_t ret; - struct dpaa2_dev_priv *priv = dev->data->dev_private; struct dpaa2_queue *dpaa2_q; struct qbman_swp *swp; struct qbman_fq_query_np_rslt state; @@ -990,12 +1019,12 @@ dpaa2_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id) } swp = DPAA2_PER_LCORE_PORTAL; - dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id]; + dpaa2_q = rx_queue; if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) { frame_cnt = qbman_fq_state_frame_count(&state); - DPAA2_PMD_DP_DEBUG("RX frame count for q(%d) is %u", - rx_queue_id, frame_cnt); + DPAA2_PMD_DP_DEBUG("RX frame count for q(%p) is %u", + rx_queue, frame_cnt); } return frame_cnt; } @@ -1116,7 +1145,7 @@ dpaa2_dev_start(struct rte_eth_dev *dev) struct rte_intr_handle *intr_handle; dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device); - intr_handle = &dpaa2_dev->intr_handle; + intr_handle = dpaa2_dev->intr_handle; PMD_INIT_FUNC_TRACE(); @@ -1151,11 +1180,31 @@ dpaa2_dev_start(struct rte_eth_dev *dev) dpaa2_q->fqid = qid.fqid; } - /*checksum errors, send them to normal path and set it in annotation */ - err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE; - err_cfg.errors |= DPNI_ERROR_PHE; + if (dpaa2_enable_err_queue) { + ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token, + DPNI_QUEUE_RX_ERR, 0, 0, &cfg, &qid); + if (ret) { + DPAA2_PMD_ERR("Error getting rx err flow information: err=%d", + ret); + return ret; + } + dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq; + dpaa2_q->fqid = qid.fqid; + dpaa2_q->eth_data = dev->data; + + err_cfg.errors = DPNI_ERROR_DISC; + err_cfg.error_action = DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE; + } else { + /* checksum errors, send them to normal path + * and set it in annotation + */ + err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE; - err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE; + /* if packet with parse error are not to be dropped */ + err_cfg.errors |= DPNI_ERROR_PHE; + + err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE; + } err_cfg.set_frame_annotation = true; ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW, @@ -1167,8 +1216,8 @@ dpaa2_dev_start(struct rte_eth_dev *dev) } /* if the interrupts were configured on this devices*/ - if (intr_handle && (intr_handle->fd) && - (dev->data->dev_conf.intr_conf.lsc != 0)) { + if (intr_handle && rte_intr_fd_get(intr_handle) && + dev->data->dev_conf.intr_conf.lsc != 0) { /* Registering LSC interrupt handler */ rte_intr_callback_register(intr_handle, dpaa2_interrupt_handler, @@ -1195,7 +1244,7 @@ dpaa2_dev_start(struct rte_eth_dev *dev) * This routine disables all traffic on the adapter by issuing a * global reset on the MAC. */ -static void +static int dpaa2_dev_stop(struct rte_eth_dev *dev) { struct dpaa2_dev_priv *priv = dev->data->dev_private; @@ -1207,8 +1256,8 @@ dpaa2_dev_stop(struct rte_eth_dev *dev) PMD_INIT_FUNC_TRACE(); /* reset interrupt callback */ - if (intr_handle && (intr_handle->fd) && - (dev->data->dev_conf.intr_conf.lsc != 0)) { + if (intr_handle && rte_intr_fd_get(intr_handle) && + dev->data->dev_conf.intr_conf.lsc != 0) { /*disable dpni irqs */ dpaa2_eth_setup_irqs(dev, 0); @@ -1227,12 +1276,14 @@ dpaa2_dev_stop(struct rte_eth_dev *dev) if (ret) { DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev", ret, priv->hw_id); - return; + return ret; } /* clear the recorded link status */ memset(&link, 0, sizeof(link)); rte_eth_linkstatus_set(dev, &link); + + return 0; } static int @@ -1253,6 +1304,7 @@ dpaa2_dev_close(struct rte_eth_dev *dev) return -1; } + dpaa2_tm_deinit(dev); dpaa2_flow_clean(dev); /* Clean the device first */ ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token); @@ -1284,10 +1336,6 @@ dpaa2_dev_close(struct rte_eth_dev *dev) if (priv->extract.qos_extract_param) rte_free((void *)(size_t)priv->extract.qos_extract_param); - dev->dev_ops = NULL; - dev->rx_pkt_burst = NULL; - dev->tx_pkt_burst = NULL; - DPAA2_PMD_INFO("%s: netdev deleted", dev->data->name); return 0; } @@ -1411,19 +1459,6 @@ dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) return -EINVAL; } - /* check that mtu is within the allowed range */ - if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA2_MAX_RX_PKT_LEN) - return -EINVAL; - - if (frame_size > RTE_ETHER_MAX_LEN) - dev->data->dev_conf.rxmode.offloads |= - DEV_RX_OFFLOAD_JUMBO_FRAME; - else - dev->data->dev_conf.rxmode.offloads &= - ~DEV_RX_OFFLOAD_JUMBO_FRAME; - - dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; - /* Set the Max Rx frame length as 'mtu' + * Maximum Ethernet header length */ @@ -1735,8 +1770,8 @@ dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, static int dpaa2_xstats_get_names_by_id( struct rte_eth_dev *dev, - struct rte_eth_xstat_name *xstats_names, const uint64_t *ids, + struct rte_eth_xstat_name *xstats_names, unsigned int limit) { unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); @@ -1800,23 +1835,32 @@ error: /* return 0 means link status changed, -1 means not changed */ static int dpaa2_dev_link_update(struct rte_eth_dev *dev, - int wait_to_complete __rte_unused) + int wait_to_complete) { int ret; struct dpaa2_dev_priv *priv = dev->data->dev_private; struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; struct rte_eth_link link; struct dpni_link_state state = {0}; + uint8_t count; if (dpni == NULL) { DPAA2_PMD_ERR("dpni is NULL"); return 0; } - ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); - if (ret < 0) { - DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret); - return -1; + for (count = 0; count <= MAX_REPEAT_TIME; count++) { + ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, + &state); + if (ret < 0) { + DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret); + return -1; + } + if (state.up == RTE_ETH_LINK_DOWN && + wait_to_complete) + rte_delay_ms(CHECK_INTERVAL); + else + break; } memset(&link, 0, sizeof(struct rte_eth_link)); @@ -1824,9 +1868,9 @@ dpaa2_dev_link_update(struct rte_eth_dev *dev, link.link_speed = state.rate; if (state.options & DPNI_LINK_OPT_HALF_DUPLEX) - link.link_duplex = ETH_LINK_HALF_DUPLEX; + link.link_duplex = RTE_ETH_LINK_HALF_DUPLEX; else - link.link_duplex = ETH_LINK_FULL_DUPLEX; + link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX; ret = rte_eth_linkstatus_set(dev, &link); if (ret == -1) @@ -1987,9 +2031,9 @@ dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) * No TX side flow control (send Pause frame disabled) */ if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE)) - fc_conf->mode = RTE_FC_FULL; + fc_conf->mode = RTE_ETH_FC_FULL; else - fc_conf->mode = RTE_FC_RX_PAUSE; + fc_conf->mode = RTE_ETH_FC_RX_PAUSE; } else { /* DPNI_LINK_OPT_PAUSE not set * if ASYM_PAUSE set, @@ -1999,9 +2043,9 @@ dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) * Flow control disabled */ if (state.options & DPNI_LINK_OPT_ASYM_PAUSE) - fc_conf->mode = RTE_FC_TX_PAUSE; + fc_conf->mode = RTE_ETH_FC_TX_PAUSE; else - fc_conf->mode = RTE_FC_NONE; + fc_conf->mode = RTE_ETH_FC_NONE; } return ret; @@ -2045,14 +2089,14 @@ dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) /* update cfg with fc_conf */ switch (fc_conf->mode) { - case RTE_FC_FULL: + case RTE_ETH_FC_FULL: /* Full flow control; * OPT_PAUSE set, ASYM_PAUSE not set */ cfg.options |= DPNI_LINK_OPT_PAUSE; cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE; break; - case RTE_FC_TX_PAUSE: + case RTE_ETH_FC_TX_PAUSE: /* Enable RX flow control * OPT_PAUSE not set; * ASYM_PAUSE set; @@ -2060,7 +2104,7 @@ dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE; cfg.options &= ~DPNI_LINK_OPT_PAUSE; break; - case RTE_FC_RX_PAUSE: + case RTE_ETH_FC_RX_PAUSE: /* Enable TX Flow control * OPT_PAUSE set * ASYM_PAUSE set @@ -2068,7 +2112,7 @@ dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) cfg.options |= DPNI_LINK_OPT_PAUSE; cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE; break; - case RTE_FC_NONE: + case RTE_ETH_FC_NONE: /* Disable Flow control * OPT_PAUSE not set * ASYM_PAUSE not set @@ -2204,7 +2248,7 @@ int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev, ret = dpni_set_opr(dpni, CMD_PRI_LOW, eth_priv->token, dpaa2_ethq->tc_index, flow_id, - OPR_OPT_CREATE, &ocfg); + OPR_OPT_CREATE, &ocfg, 0); if (ret) { DPAA2_PMD_ERR("Error setting opr: ret: %d\n", ret); return ret; @@ -2251,45 +2295,15 @@ int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev, return ret; } -static inline int -dpaa2_dev_verify_filter_ops(enum rte_filter_op filter_op) -{ - unsigned int i; - - for (i = 0; i < RTE_DIM(dpaa2_supported_filter_ops); i++) { - if (dpaa2_supported_filter_ops[i] == filter_op) - return 0; - } - return -ENOTSUP; -} - static int -dpaa2_dev_flow_ctrl(struct rte_eth_dev *dev, - enum rte_filter_type filter_type, - enum rte_filter_op filter_op, - void *arg) +dpaa2_dev_flow_ops_get(struct rte_eth_dev *dev, + const struct rte_flow_ops **ops) { - int ret = 0; - if (!dev) return -ENODEV; - switch (filter_type) { - case RTE_ETH_FILTER_GENERIC: - if (dpaa2_dev_verify_filter_ops(filter_op) < 0) { - ret = -ENOTSUP; - break; - } - *(const void **)arg = &dpaa2_flow_ops; - dpaa2_filter_type |= filter_type; - break; - default: - RTE_LOG(ERR, PMD, "Filter type (%d) not supported", - filter_type); - ret = -ENOTSUP; - break; - } - return ret; + *ops = &dpaa2_flow_ops; + return 0; } static void @@ -2297,12 +2311,18 @@ dpaa2_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, struct rte_eth_rxq_info *qinfo) { struct dpaa2_queue *rxq; + struct dpaa2_dev_priv *priv = dev->data->dev_private; + struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; + uint16_t max_frame_length; rxq = (struct dpaa2_queue *)dev->data->rx_queues[queue_id]; qinfo->mp = rxq->mb_pool; qinfo->scattered_rx = dev->data->scattered_rx; qinfo->nb_desc = rxq->nb_desc; + if (dpni_get_max_frame_length(dpni, CMD_PRI_LOW, priv->token, + &max_frame_length) == 0) + qinfo->rx_buf_size = max_frame_length; qinfo->conf.rx_free_thresh = 1; qinfo->conf.rx_drop_en = 1; @@ -2329,6 +2349,30 @@ dpaa2_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, qinfo->conf.tx_deferred_start = 0; } +static int +dpaa2_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops) +{ + *(const void **)ops = &dpaa2_tm_ops; + + return 0; +} + +void +rte_pmd_dpaa2_thread_init(void) +{ + int ret; + + if (unlikely(!DPAA2_PER_LCORE_DPIO)) { + ret = dpaa2_affine_qbman_swp(); + if (ret) { + DPAA2_PMD_ERR( + "Failed to allocate IO portal, tid: %d\n", + rte_gettid()); + return; + } + } +} + static struct eth_dev_ops dpaa2_ethdev_ops = { .dev_configure = dpaa2_eth_dev_configure, .dev_start = dpaa2_dev_start, @@ -2358,7 +2402,6 @@ static struct eth_dev_ops dpaa2_ethdev_ops = { .rx_queue_setup = dpaa2_dev_rx_queue_setup, .rx_queue_release = dpaa2_dev_rx_queue_release, .tx_queue_setup = dpaa2_dev_tx_queue_setup, - .tx_queue_release = dpaa2_dev_tx_queue_release, .rx_burst_mode_get = dpaa2_dev_rx_burst_mode_get, .tx_burst_mode_get = dpaa2_dev_tx_burst_mode_get, .flow_ctrl_get = dpaa2_flow_ctrl_get, @@ -2368,9 +2411,10 @@ static struct eth_dev_ops dpaa2_ethdev_ops = { .mac_addr_set = dpaa2_dev_set_mac_addr, .rss_hash_update = dpaa2_dev_rss_hash_update, .rss_hash_conf_get = dpaa2_dev_rss_hash_conf_get, - .filter_ctrl = dpaa2_dev_flow_ctrl, + .flow_ops_get = dpaa2_dev_flow_ops_get, .rxq_info_get = dpaa2_rxq_info_get, .txq_info_get = dpaa2_txq_info_get, + .tm_ops_get = dpaa2_tm_ops_get, #if defined(RTE_LIBRTE_IEEE1588) .timesync_enable = dpaa2_timesync_enable, .timesync_disable = dpaa2_timesync_disable, @@ -2586,10 +2630,19 @@ dpaa2_dev_init(struct rte_eth_dev *eth_dev) priv->max_vlan_filters = attr.vlan_filter_entries; priv->flags = 0; #if defined(RTE_LIBRTE_IEEE1588) - priv->tx_conf_en = 1; -#else - priv->tx_conf_en = 0; + printf("DPDK IEEE1588 is enabled\n"); + priv->flags |= DPAA2_TX_CONF_ENABLE; #endif + /* Used with ``fslmc:dpni.1,drv_tx_conf=1`` */ + if (dpaa2_get_devargs(dev->devargs, DRIVER_TX_CONF)) { + priv->flags |= DPAA2_TX_CONF_ENABLE; + DPAA2_PMD_INFO("TX_CONF Enabled"); + } + + if (dpaa2_get_devargs(dev->devargs, DRIVER_ERROR_QUEUE)) { + dpaa2_enable_err_queue = 1; + DPAA2_PMD_INFO("Enable error queue"); + } /* Allocate memory for hardware structure for queues */ ret = dpaa2_alloc_rx_tx_queues(eth_dev); @@ -2622,7 +2675,7 @@ dpaa2_dev_init(struct rte_eth_dev *eth_dev) /* ... tx buffer layout ... */ memset(&layout, 0, sizeof(struct dpni_buffer_layout)); - if (priv->tx_conf_en) { + if (priv->flags & DPAA2_TX_CONF_ENABLE) { layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS | DPNI_BUF_LAYOUT_OPT_TIMESTAMP; layout.pass_timestamp = true; @@ -2639,13 +2692,11 @@ dpaa2_dev_init(struct rte_eth_dev *eth_dev) /* ... tx-conf and error buffer layout ... */ memset(&layout, 0, sizeof(struct dpni_buffer_layout)); - if (priv->tx_conf_en) { - layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS | - DPNI_BUF_LAYOUT_OPT_TIMESTAMP; + if (priv->flags & DPAA2_TX_CONF_ENABLE) { + layout.options = DPNI_BUF_LAYOUT_OPT_TIMESTAMP; layout.pass_timestamp = true; - } else { - layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS; } + layout.options |= DPNI_BUF_LAYOUT_OPT_FRAME_STATUS; layout.pass_frame_status = 1; ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX_CONFIRM, &layout); @@ -2745,6 +2796,11 @@ init_err: return ret; } +int dpaa2_dev_is_dpaa2(struct rte_eth_dev *dev) +{ + return dev->device->driver == &rte_dpaa2_pmd.driver; +} + static int rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv, struct rte_dpaa2_device *dpaa2_dev) @@ -2779,7 +2835,6 @@ rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv, eth_dev->data->dev_private = (void *)dev_priv; /* Store a pointer to eth_dev in dev_private */ dev_priv->eth_dev = eth_dev; - dev_priv->tx_conf_en = 0; } else { eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name); if (!eth_dev) { @@ -2793,10 +2848,11 @@ rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv, dpaa2_dev->eth_dev = eth_dev; eth_dev->data->rx_mbuf_alloc_failed = 0; - eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC) eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC; + eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; + /* Invoke PMD device initialization function */ diag = dpaa2_dev_init(eth_dev); if (diag == 0) { @@ -2828,8 +2884,10 @@ static struct rte_dpaa2_driver rte_dpaa2_pmd = { .remove = rte_dpaa2_remove, }; -RTE_PMD_REGISTER_DPAA2(net_dpaa2, rte_dpaa2_pmd); -RTE_PMD_REGISTER_PARAM_STRING(net_dpaa2, +RTE_PMD_REGISTER_DPAA2(NET_DPAA2_PMD_DRIVER_NAME, rte_dpaa2_pmd); +RTE_PMD_REGISTER_PARAM_STRING(NET_DPAA2_PMD_DRIVER_NAME, DRIVER_LOOPBACK_MODE "= " - DRIVER_NO_PREFETCH_MODE "="); -RTE_LOG_REGISTER(dpaa2_logtype_pmd, pmd.net.dpaa2, NOTICE); + DRIVER_NO_PREFETCH_MODE "=" + DRIVER_TX_CONF "=" + DRIVER_ERROR_QUEUE "="); +RTE_LOG_REGISTER_DEFAULT(dpaa2_logtype_pmd, NOTICE);