X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fdpaa2%2Fdpaa2_ethdev.h;h=e577355d57085c78628b46681546ef2ca675ef73;hb=4defbc8cbb6d5b520f13ee7f2396b0a31516d370;hp=0ef1bf3685453286b46fbc3ef991ace21120f5bf;hpb=fe2b986ac662c5df6435c4515cbc7083dd267cb1;p=dpdk.git

diff --git a/drivers/net/dpaa2/dpaa2_ethdev.h b/drivers/net/dpaa2/dpaa2_ethdev.h
index 0ef1bf3685..e577355d57 100644
--- a/drivers/net/dpaa2/dpaa2_ethdev.h
+++ b/drivers/net/dpaa2/dpaa2_ethdev.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  *
  *   Copyright (c) 2015-2016 Freescale Semiconductor, Inc. All rights reserved.
- *   Copyright 2016 NXP
+ *   Copyright 2016-2020 NXP
  *
  */
 
@@ -22,6 +22,9 @@
 #define MAX_TCS			DPNI_MAX_TC
 #define MAX_RX_QUEUES		128
 #define MAX_TX_QUEUES		16
+#define MAX_DPNI		8
+
+#define DPAA2_RX_DEFAULT_NBDESC 512
 
 /*default tc to be used for ,congestion, distribution etc configuration. */
 #define DPAA2_DEF_TC		0
@@ -37,9 +40,9 @@
 #define CONG_RETRY_COUNT 18000
 
 /* RX queue tail drop threshold
- * currently considering 32 KB packets
+ * currently considering 64 KB packets
  */
-#define CONG_THRESHOLD_RX_Q  (64 * 1024)
+#define CONG_THRESHOLD_RX_BYTES_Q  (64 * 1024)
 #define CONG_RX_OAL	128
 
 /* Size of the input SMMU mapped memory required by MC */
@@ -54,6 +57,7 @@
 #define DPAA2_RX_TAILDROP_OFF	0x04
 
 #define DPAA2_RSS_OFFLOAD_ALL ( \
+	ETH_RSS_L2_PAYLOAD | \
 	ETH_RSS_IP | \
 	ETH_RSS_UDP | \
 	ETH_RSS_TCP | \
@@ -87,15 +91,45 @@
 #define DPAA2_PKT_TYPE_VLAN_2		0x0260
 
 /* enable timestamp in mbuf*/
-extern enum pmd_dpaa2_ts dpaa2_enable_ts;
+extern bool dpaa2_enable_ts[];
 
 #define DPAA2_QOS_TABLE_RECONFIGURE	1
 #define DPAA2_FS_TABLE_RECONFIGURE	2
 
+#define DPAA2_QOS_TABLE_IPADDR_EXTRACT 4
+#define DPAA2_FS_TABLE_IPADDR_EXTRACT 8
+
+#define DPAA2_FLOW_MAX_KEY_SIZE		16
+
 /*Externaly defined*/
 extern const struct rte_flow_ops dpaa2_flow_ops;
 extern enum rte_filter_type dpaa2_filter_type;
 
+#define IP_ADDRESS_OFFSET_INVALID (-1)
+
+struct dpaa2_key_info {
+	uint8_t key_offset[DPKG_MAX_NUM_OF_EXTRACTS];
+	uint8_t key_size[DPKG_MAX_NUM_OF_EXTRACTS];
+	/* Special for IP address. */
+	int ipv4_src_offset;
+	int ipv4_dst_offset;
+	int ipv6_src_offset;
+	int ipv6_dst_offset;
+	uint8_t key_total_size;
+};
+
+struct dpaa2_key_extract {
+	struct dpkg_profile_cfg dpkg;
+	struct dpaa2_key_info key_info;
+};
+
+struct extract_s {
+	struct dpaa2_key_extract qos_key_extract;
+	struct dpaa2_key_extract tc_key_extract[MAX_TCS];
+	uint64_t qos_extract_param;
+	uint64_t tc_extract_param[MAX_TCS];
+};
+
 struct dpaa2_dev_priv {
 	void *hw;
 	int32_t hw_id;
@@ -106,47 +140,65 @@ struct dpaa2_dev_priv {
 	uint32_t options;
 	void *rx_vq[MAX_RX_QUEUES];
 	void *tx_vq[MAX_TX_QUEUES];
-
 	struct dpaa2_bp_list *bp_list; /**<Attached buffer pool list */
+	void *tx_conf_vq[MAX_TX_QUEUES];
+	uint8_t tx_conf_en;
 	uint8_t max_mac_filters;
 	uint8_t max_vlan_filters;
 	uint8_t num_rx_tc;
+	uint16_t qos_entries;
+	uint16_t fs_entries;
+	uint8_t dist_queues;
 	uint8_t flags; /*dpaa2 config flags */
 	uint8_t en_ordered;
 	uint8_t en_loose_ordered;
-
-	struct pattern_s {
-		uint8_t item_count;
-		uint8_t pattern_type[DPKG_MAX_NUM_OF_EXTRACTS];
-	} pattern[MAX_TCS + 1];
-
-	struct extract_s {
-		struct dpkg_profile_cfg qos_key_cfg;
-		struct dpkg_profile_cfg fs_key_cfg[MAX_TCS];
-		uint64_t qos_extract_param;
-		uint64_t fs_extract_param[MAX_TCS];
-	} extract;
+	uint8_t max_cgs;
+	uint8_t cgid_in_use[MAX_RX_QUEUES];
+
+	struct extract_s extract;
+
+	uint16_t ss_offset;
+	uint64_t ss_iova;
+	uint64_t ss_param_iova;
+#if defined(RTE_LIBRTE_IEEE1588)
+	/*stores timestamp of last received packet on dev*/
+	uint64_t rx_timestamp;
+	/*stores timestamp of last received tx confirmation packet on dev*/
+	uint64_t tx_timestamp;
+	/* stores pointer to next tx_conf queue that should be processed,
+	 * it corresponds to last packet transmitted
+	 */
+	struct dpaa2_queue *next_tx_conf_queue;
+#endif
+
+	struct rte_eth_dev *eth_dev; /**< Pointer back to holding ethdev */
+
+	LIST_HEAD(, rte_flow) flows; /**< Configured flow rule handles. */
 };
 
 int dpaa2_distset_to_dpkg_profile_cfg(uint64_t req_dist_set,
 				      struct dpkg_profile_cfg *kg_cfg);
 
 int dpaa2_setup_flow_dist(struct rte_eth_dev *eth_dev,
-			  uint64_t req_dist_set);
+		uint64_t req_dist_set, int tc_index);
 
 int dpaa2_remove_flow_dist(struct rte_eth_dev *eth_dev,
 			   uint8_t tc_index);
 
 int dpaa2_attach_bp_list(struct dpaa2_dev_priv *priv, void *blist);
 
+__rte_internal
 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
 		int eth_rx_queue_id,
-		uint16_t dpcon_id,
+		struct dpaa2_dpcon_dev *dpcon,
 		const struct rte_event_eth_rx_adapter_queue_conf *queue_conf);
 
+__rte_internal
 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
 		int eth_rx_queue_id);
 
+uint16_t dpaa2_dev_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);
+
 uint16_t dpaa2_dev_loopback_rx(void *queue, struct rte_mbuf **bufs,
 				uint16_t nb_pkts);
 
@@ -172,5 +224,21 @@ uint16_t dpaa2_dev_tx_ordered(void *queue, struct rte_mbuf **bufs,
 			      uint16_t nb_pkts);
 uint16_t dummy_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);
 void dpaa2_dev_free_eqresp_buf(uint16_t eqresp_ci);
-
+void dpaa2_flow_clean(struct rte_eth_dev *dev);
+uint16_t dpaa2_dev_tx_conf(void *queue)  __rte_unused;
+
+#if defined(RTE_LIBRTE_IEEE1588)
+int dpaa2_timesync_enable(struct rte_eth_dev *dev);
+int dpaa2_timesync_disable(struct rte_eth_dev *dev);
+int dpaa2_timesync_read_time(struct rte_eth_dev *dev,
+					struct timespec *timestamp);
+int dpaa2_timesync_write_time(struct rte_eth_dev *dev,
+					const struct timespec *timestamp);
+int dpaa2_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
+int dpaa2_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
+						struct timespec *timestamp,
+						uint32_t flags __rte_unused);
+int dpaa2_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
+					  struct timespec *timestamp);
+#endif
 #endif /* _DPAA2_ETHDEV_H */