X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fe1000%2Fem_rxtx.c;h=49c53712a2a538812729e5a4d6849a7d2f4825c3;hb=4710e16a4a7b53c9f2cf38e6f6af945e9af59c26;hp=6f40b45a30eb73f4e2b17044f970d8c80a4bbe8f;hpb=1fc9701238edcf0541289b9ae15565b6d9d7ab30;p=dpdk.git

diff --git a/drivers/net/e1000/em_rxtx.c b/drivers/net/e1000/em_rxtx.c
index 6f40b45a30..49c53712a2 100644
--- a/drivers/net/e1000/em_rxtx.c
+++ b/drivers/net/e1000/em_rxtx.c
@@ -2049,13 +2049,12 @@ e1000_flush_tx_ring(struct rte_eth_dev *dev)
 		tx_desc->lower.data = rte_cpu_to_le_32(txd_lower | size);
 		tx_desc->upper.data = 0;
 
-		rte_wmb();
+		rte_cio_wmb();
 		txq->tx_tail++;
 		if (txq->tx_tail == txq->nb_tx_desc)
 			txq->tx_tail = 0;
-		rte_io_wmb();
 		tdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_TDT(i));
-		E1000_PCI_REG_WRITE_RELAXED(tdt_reg_addr, txq->tx_tail);
+		E1000_PCI_REG_WRITE(tdt_reg_addr, txq->tx_tail);
 		usec_delay(250);
 	}
 }
@@ -2109,20 +2108,32 @@ em_flush_desc_rings(struct rte_eth_dev *dev)
 	struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 	struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 	uint16_t pci_cfg_status = 0;
+	int ret;
 
 	fextnvm11 = E1000_READ_REG(hw, E1000_FEXTNVM11);
 	E1000_WRITE_REG(hw, E1000_FEXTNVM11,
 			fextnvm11 | E1000_FEXTNVM11_DISABLE_MULR_FIX);
 	tdlen = E1000_READ_REG(hw, E1000_TDLEN(0));
-	rte_pci_read_config(pci_dev, &pci_cfg_status, sizeof(pci_cfg_status),
-				PCI_CFG_STATUS_REG);
+	ret = rte_pci_read_config(pci_dev, &pci_cfg_status,
+		   sizeof(pci_cfg_status), PCI_CFG_STATUS_REG);
+	if (ret < 0) {
+		PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
+			    PCI_CFG_STATUS_REG);
+		return;
+	}
 
 	/* do nothing if we're not in faulty state, or if the queue is empty */
 	if ((pci_cfg_status & FLUSH_DESC_REQUIRED) && tdlen) {
 		/* flush desc ring */
 		e1000_flush_tx_ring(dev);
-		rte_pci_read_config(pci_dev, &pci_cfg_status,
+		ret = rte_pci_read_config(pci_dev, &pci_cfg_status,
 				sizeof(pci_cfg_status), PCI_CFG_STATUS_REG);
+		if (ret < 0) {
+			PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
+					PCI_CFG_STATUS_REG);
+			return;
+		}
+
 		if (pci_cfg_status & FLUSH_DESC_REQUIRED)
 			e1000_flush_rx_ring(dev);
 	}