X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fena%2Fbase%2Fena_plat_dpdk.h;h=9e1492cac4c7ba0e65e1cb9e6258a3e6fe8db63a;hb=b5fedaedfcf272d1a86802132a1691ac5485f31d;hp=b1ed80c7028d82665ad5e979b549e8700f903dc4;hpb=3d3edc265fc88853752720a44a7d7f1e36f1f7e7;p=dpdk.git diff --git a/drivers/net/ena/base/ena_plat_dpdk.h b/drivers/net/ena/base/ena_plat_dpdk.h index b1ed80c702..9e1492cac4 100644 --- a/drivers/net/ena/base/ena_plat_dpdk.h +++ b/drivers/net/ena/base/ena_plat_dpdk.h @@ -1,35 +1,7 @@ -/*- -* BSD LICENSE -* -* Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* * Neither the name of copyright holder nor the names of its -* contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (c) 2015-2019 Amazon.com, Inc. or its affiliates. + * All rights reserved. + */ #ifndef DPDK_ENA_COM_ENA_PLAT_DPDK_H_ #define DPDK_ENA_COM_ENA_PLAT_DPDK_H_ @@ -44,9 +16,11 @@ #include #include #include +#include #include #include #include +#include #include #include @@ -62,7 +36,7 @@ typedef uint64_t dma_addr_t; #endif #define ena_atomic32_t rte_atomic32_t -#define ena_mem_handle_t void * +#define ena_mem_handle_t const struct rte_memzone * #define SZ_256 (256U) #define SZ_4K (4096U) @@ -72,10 +46,10 @@ typedef uint64_t dma_addr_t; #define ENA_COM_INVAL -EINVAL #define ENA_COM_NO_SPACE -ENOSPC #define ENA_COM_NO_DEVICE -ENODEV -#define ENA_COM_PERMISSION -EPERM #define ENA_COM_TIMER_EXPIRED -ETIME #define ENA_COM_FAULT -EFAULT #define ENA_COM_TRY_AGAIN -EAGAIN +#define ENA_COM_UNSUPPORTED -EOPNOTSUPP #define ____cacheline_aligned __rte_cache_aligned @@ -87,19 +61,22 @@ typedef uint64_t dma_addr_t; #define ENA_TOUCH(x) ((void)(x)) #define memcpy_toio memcpy #define wmb rte_wmb -#define rmb rte_wmb +#define rmb rte_rmb #define mb rte_mb +#define mmiowb rte_io_wmb #define __iomem #define US_PER_S 1000000 #define ENA_GET_SYSTEM_USECS() \ (rte_get_timer_cycles() * US_PER_S / rte_get_timer_hz()) -#if RTE_LOG_LEVEL >= RTE_LOG_DEBUG +extern int ena_logtype_com; +#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG #define ENA_ASSERT(cond, format, arg...) \ do { \ if (unlikely(!(cond))) { \ - RTE_LOG(ERR, PMD, format, ##arg); \ + rte_log(RTE_LOGTYPE_ERR, ena_logtype_com, \ + format, ##arg); \ rte_panic("line %d\tassert \"" #cond "\"" \ "failed\n", __LINE__); \ } \ @@ -115,21 +92,23 @@ typedef uint64_t dma_addr_t; #define ENA_MIN16(x, y) RTE_MIN((x), (y)) #define ENA_MIN8(x, y) RTE_MIN((x), (y)) +#define BITS_PER_LONG_LONG (__SIZEOF_LONG_LONG__ * 8) #define U64_C(x) x ## ULL #define BIT(nr) (1UL << (nr)) #define BITS_PER_LONG (__SIZEOF_LONG__ * 8) #define GENMASK(h, l) (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) -#define GENMASK_ULL(h, l) (((U64_C(1) << ((h) - (l) + 1)) - 1) << (l)) +#define GENMASK_ULL(h, l) (((~0ULL) - (1ULL << (l)) + 1) & \ + (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h)))) #ifdef RTE_LIBRTE_ENA_COM_DEBUG -#define ena_trc_dbg(format, arg...) \ - RTE_LOG(DEBUG, PMD, "[ENA_COM: %s] " format, __func__, ##arg) -#define ena_trc_info(format, arg...) \ - RTE_LOG(INFO, PMD, "[ENA_COM: %s] " format, __func__, ##arg) -#define ena_trc_warn(format, arg...) \ - RTE_LOG(ERR, PMD, "[ENA_COM: %s] " format, __func__, ##arg) -#define ena_trc_err(format, arg...) \ - RTE_LOG(ERR, PMD, "[ENA_COM: %s] " format, __func__, ##arg) +#define ena_trc_log(level, fmt, arg...) \ + rte_log(RTE_LOG_ ## level, ena_logtype_com, \ + "[ENA_COM: %s]" fmt, __func__, ##arg) + +#define ena_trc_dbg(format, arg...) ena_trc_log(DEBUG, format, ##arg) +#define ena_trc_info(format, arg...) ena_trc_log(INFO, format, ##arg) +#define ena_trc_warn(format, arg...) ena_trc_log(WARNING, format, ##arg) +#define ena_trc_err(format, arg...) ena_trc_log(ERR, format, ##arg) #else #define ena_trc_dbg(format, arg...) do { } while (0) #define ena_trc_info(format, arg...) do { } while (0) @@ -137,6 +116,15 @@ typedef uint64_t dma_addr_t; #define ena_trc_err(format, arg...) do { } while (0) #endif /* RTE_LIBRTE_ENA_COM_DEBUG */ +#define ENA_WARN(cond, format, arg...) \ +do { \ + if (unlikely(cond)) { \ + ena_trc_err( \ + "Warn failed on %s:%s:%d:" format, \ + __FILE__, __func__, __LINE__, ##arg); \ + } \ +} while (0) + /* Spinlock related methods */ #define ena_spinlock_t rte_spinlock_t #define ENA_SPINLOCK_INIT(spinlock) rte_spinlock_init(&spinlock) @@ -144,6 +132,7 @@ typedef uint64_t dma_addr_t; ({(void)flags; rte_spinlock_lock(&spinlock); }) #define ENA_SPINLOCK_UNLOCK(spinlock, flags) \ ({(void)flags; rte_spinlock_unlock(&(spinlock)); }) +#define ENA_SPINLOCK_DESTROY(spinlock) ((void)spinlock) #define q_waitqueue_t \ struct { \ @@ -176,10 +165,21 @@ typedef uint64_t dma_addr_t; #define ENA_WAIT_EVENT_SIGNAL(waitevent) pthread_cond_signal(&waitevent.cond) /* pthread condition doesn't need to be rearmed after usage */ #define ENA_WAIT_EVENT_CLEAR(...) +#define ENA_WAIT_EVENT_DESTROY(waitqueue) ((void)(waitqueue)) #define ena_wait_event_t ena_wait_queue_t #define ENA_MIGHT_SLEEP() +#define ENA_TIME_EXPIRE(timeout) (timeout < rte_get_timer_cycles()) +#define ENA_GET_SYSTEM_TIMEOUT(timeout_us) \ + (timeout_us * rte_get_timer_hz() / 1000000 + rte_get_timer_cycles()) + +/* + * Each rte_memzone should have unique name. + * To satisfy it, count number of allocations and add it to name. + */ +extern uint32_t ena_alloc_cnt; + #define ENA_MEM_ALLOC_COHERENT(dmadev, size, virt, phys, handle) \ do { \ const struct rte_memzone *mz; \ @@ -187,53 +187,61 @@ typedef uint64_t dma_addr_t; ENA_TOUCH(dmadev); ENA_TOUCH(handle); \ snprintf(z_name, sizeof(z_name), \ "ena_alloc_%d", ena_alloc_cnt++); \ - mz = rte_memzone_reserve(z_name, size, SOCKET_ID_ANY, 0); \ - virt = mz->addr; \ - phys = mz->phys_addr; \ + mz = rte_memzone_reserve(z_name, size, SOCKET_ID_ANY, \ + RTE_MEMZONE_IOVA_CONTIG); \ + handle = mz; \ + if (mz == NULL) { \ + virt = NULL; \ + phys = 0; \ + } else { \ + memset(mz->addr, 0, size); \ + virt = mz->addr; \ + phys = mz->iova; \ + } \ } while (0) #define ENA_MEM_FREE_COHERENT(dmadev, size, virt, phys, handle) \ ({ ENA_TOUCH(size); ENA_TOUCH(phys); \ ENA_TOUCH(dmadev); \ - rte_free(virt); }) + rte_memzone_free(handle); }) -#define ENA_MEM_ALLOC_COHERENT_NODE(dmadev, size, virt, phys, node, dev_node) \ +#define ENA_MEM_ALLOC_COHERENT_NODE( \ + dmadev, size, virt, phys, mem_handle, node, dev_node) \ do { \ const struct rte_memzone *mz; \ char z_name[RTE_MEMZONE_NAMESIZE]; \ ENA_TOUCH(dmadev); ENA_TOUCH(dev_node); \ snprintf(z_name, sizeof(z_name), \ "ena_alloc_%d", ena_alloc_cnt++); \ - mz = rte_memzone_reserve(z_name, size, node, 0); \ - virt = mz->addr; \ - phys = mz->phys_addr; \ + mz = rte_memzone_reserve(z_name, size, node, \ + RTE_MEMZONE_IOVA_CONTIG); \ + mem_handle = mz; \ + if (mz == NULL) { \ + virt = NULL; \ + phys = 0; \ + } else { \ + memset(mz->addr, 0, size); \ + virt = mz->addr; \ + phys = mz->iova; \ + } \ } while (0) #define ENA_MEM_ALLOC_NODE(dmadev, size, virt, node, dev_node) \ do { \ - const struct rte_memzone *mz; \ - char z_name[RTE_MEMZONE_NAMESIZE]; \ ENA_TOUCH(dmadev); ENA_TOUCH(dev_node); \ - snprintf(z_name, sizeof(z_name), \ - "ena_alloc_%d", ena_alloc_cnt++); \ - mz = rte_memzone_reserve(z_name, size, node, 0); \ - virt = mz->addr; \ + virt = rte_zmalloc_socket(NULL, size, 0, node); \ } while (0) #define ENA_MEM_ALLOC(dmadev, size) rte_zmalloc(NULL, size, 1) #define ENA_MEM_FREE(dmadev, ptr) ({ENA_TOUCH(dmadev); rte_free(ptr); }) -static inline void writel(u32 value, volatile void *addr) -{ - *(volatile u32 *)addr = value; -} - -static inline u32 readl(const volatile void *addr) -{ - return *(const volatile u32 *)addr; -} +#define ENA_DB_SYNC(mem_handle) ((void)mem_handle) -#define ENA_REG_WRITE32(value, reg) writel((value), (reg)) -#define ENA_REG_READ32(reg) readl((reg)) +#define ENA_REG_WRITE32(bus, value, reg) \ + ({ (void)(bus); rte_write32((value), (reg)); }) +#define ENA_REG_WRITE32_RELAXED(bus, value, reg) \ + ({ (void)(bus); rte_write32_relaxed((value), (reg)); }) +#define ENA_REG_READ32(bus, reg) \ + ({ (void)(bus); rte_read32_relaxed((reg)); }) #define ATOMIC32_INC(i32_ptr) rte_atomic32_inc(i32_ptr) #define ATOMIC32_DEC(i32_ptr) rte_atomic32_dec(i32_ptr) @@ -243,10 +251,43 @@ static inline u32 readl(const volatile void *addr) #define msleep(x) rte_delay_us(x * 1000) #define udelay(x) rte_delay_us(x) +#define dma_rmb() rmb() + #define MAX_ERRNO 4095 #define IS_ERR(x) (((unsigned long)x) >= (unsigned long)-MAX_ERRNO) #define ERR_PTR(error) ((void *)(long)error) #define PTR_ERR(error) ((long)(void *)error) #define might_sleep() +#define prefetch(x) rte_prefetch0(x) + +#define lower_32_bits(x) ((uint32_t)(x)) +#define upper_32_bits(x) ((uint32_t)(((x) >> 16) >> 16)) + +#define ENA_TIME_EXPIRE(timeout) (timeout < rte_get_timer_cycles()) +#define ENA_GET_SYSTEM_TIMEOUT(timeout_us) \ + (timeout_us * rte_get_timer_hz() / 1000000 + rte_get_timer_cycles()) +#define ENA_WAIT_EVENT_DESTROY(waitqueue) ((void)(waitqueue)) + +#ifndef READ_ONCE +#define READ_ONCE(var) (*((volatile typeof(var) *)(&(var)))) +#endif + +#define READ_ONCE8(var) READ_ONCE(var) +#define READ_ONCE16(var) READ_ONCE(var) +#define READ_ONCE32(var) READ_ONCE(var) + +/* The size must be 8 byte align */ +#define ENA_MEMCPY_TO_DEVICE_64(dst, src, size) \ + do { \ + int count, i; \ + uint64_t *to = (uint64_t *)(dst); \ + const uint64_t *from = (const uint64_t *)(src); \ + count = (size) / 8; \ + for (i = 0; i < count; i++, from++, to++) \ + rte_write64_relaxed(*from, to); \ + } while(0) + +#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) + #endif /* DPDK_ENA_COM_ENA_PLAT_DPDK_H_ */