X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fena%2Fena_ethdev.c;h=f3b17d70c9a48e1188d28db5c1fb4522b242fa80;hb=292be511d2909c14db3c9ceaffa317f2beee67a0;hp=8c0dd30c0269c810f29838d052bcacc03e00b4e3;hpb=b142387b07600c320683255d237b9109299883d5;p=dpdk.git diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index 8c0dd30c02..f3b17d70c9 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -4,12 +4,6 @@ */ #include -#include -#include -#include -#include -#include -#include #include #include #include @@ -27,30 +21,23 @@ #include #define DRV_MODULE_VER_MAJOR 2 -#define DRV_MODULE_VER_MINOR 1 +#define DRV_MODULE_VER_MINOR 5 #define DRV_MODULE_VER_SUBMINOR 0 -#define ENA_IO_TXQ_IDX(q) (2 * (q)) -#define ENA_IO_RXQ_IDX(q) (2 * (q) + 1) -/*reverse version of ENA_IO_RXQ_IDX*/ -#define ENA_IO_RXQ_IDX_REV(q) ((q - 1) / 2) - #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l) -#define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift)) #define GET_L4_HDR_LEN(mbuf) \ ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *, \ mbuf->l3_len + mbuf->l2_len)->data_off) >> 4) -#define ENA_RX_RSS_TABLE_LOG_SIZE 7 -#define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE) -#define ENA_HASH_KEY_SIZE 40 #define ETH_GSTRING_LEN 32 -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#define ARRAY_SIZE(x) RTE_DIM(x) #define ENA_MIN_RING_DESC 128 +#define ENA_PTYPE_HAS_HASH (RTE_PTYPE_L4_TCP | RTE_PTYPE_L4_UDP) + enum ethtool_stringset { ETH_SS_TEST = 0, ETH_SS_STATS, @@ -85,7 +72,7 @@ struct ena_stats { * Each rte_memzone should have unique name. * To satisfy it, count number of allocation and add it to name. */ -rte_atomic32_t ena_alloc_cnt; +rte_atomic64_t ena_alloc_cnt; static const struct ena_stats ena_stats_global_strings[] = { ENA_STAT_GLOBAL_ENTRY(wd_expired), @@ -112,6 +99,7 @@ static const struct ena_stats ena_stats_tx_strings[] = { ENA_STAT_TX_ENTRY(doorbells), ENA_STAT_TX_ENTRY(bad_req_id), ENA_STAT_TX_ENTRY(available_desc), + ENA_STAT_TX_ENTRY(missed_tx), }; static const struct ena_stats ena_stats_rx_strings[] = { @@ -140,8 +128,8 @@ static const struct ena_stats ena_stats_rx_strings[] = { /** Vendor ID used by Amazon devices */ #define PCI_VENDOR_ID_AMAZON 0x1D0F /** Amazon devices */ -#define PCI_DEVICE_ID_ENA_VF 0xEC20 -#define PCI_DEVICE_ID_ENA_LLQ_VF 0xEC21 +#define PCI_DEVICE_ID_ENA_VF 0xEC20 +#define PCI_DEVICE_ID_ENA_VF_RSERV0 0xEC21 #define ENA_TX_OFFLOAD_MASK (\ PKT_TX_L4_MASK | \ @@ -153,15 +141,33 @@ static const struct ena_stats ena_stats_rx_strings[] = { #define ENA_TX_OFFLOAD_NOTSUP_MASK \ (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK) +/** HW specific offloads capabilities. */ +/* IPv4 checksum offload. */ +#define ENA_L3_IPV4_CSUM 0x0001 +/* TCP/UDP checksum offload for IPv4 packets. */ +#define ENA_L4_IPV4_CSUM 0x0002 +/* TCP/UDP checksum offload for IPv4 packets with pseudo header checksum. */ +#define ENA_L4_IPV4_CSUM_PARTIAL 0x0004 +/* TCP/UDP checksum offload for IPv6 packets. */ +#define ENA_L4_IPV6_CSUM 0x0008 +/* TCP/UDP checksum offload for IPv6 packets with pseudo header checksum. */ +#define ENA_L4_IPV6_CSUM_PARTIAL 0x0010 +/* TSO support for IPv4 packets. */ +#define ENA_IPV4_TSO 0x0020 + +/* Device supports setting RSS hash. */ +#define ENA_RX_RSS_HASH 0x0040 + static const struct rte_pci_id pci_id_ena_map[] = { { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) }, - { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF_RSERV0) }, { .device_id = 0 }, }; static struct ena_aenq_handlers aenq_handlers; static int ena_device_init(struct ena_com_dev *ena_dev, + struct rte_pci_device *pdev, struct ena_com_dev_get_features_ctx *get_feat_ctx, bool *wd_state); static int ena_dev_configure(struct rte_eth_dev *dev); @@ -198,34 +204,32 @@ static void ena_init_rings(struct ena_adapter *adapter, bool disable_meta_caching); static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); static int ena_start(struct rte_eth_dev *dev); -static void ena_stop(struct rte_eth_dev *dev); +static int ena_stop(struct rte_eth_dev *dev); static int ena_close(struct rte_eth_dev *dev); static int ena_dev_reset(struct rte_eth_dev *dev); static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); static void ena_rx_queue_release_all(struct rte_eth_dev *dev); static void ena_tx_queue_release_all(struct rte_eth_dev *dev); -static void ena_rx_queue_release(void *queue); -static void ena_tx_queue_release(void *queue); +static void ena_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid); +static void ena_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid); static void ena_rx_queue_release_bufs(struct ena_ring *ring); static void ena_tx_queue_release_bufs(struct ena_ring *ring); static int ena_link_update(struct rte_eth_dev *dev, int wait_to_complete); -static int ena_create_io_queue(struct ena_ring *ring); +static int ena_create_io_queue(struct rte_eth_dev *dev, struct ena_ring *ring); static void ena_queue_stop(struct ena_ring *ring); static void ena_queue_stop_all(struct rte_eth_dev *dev, enum ena_ring_type ring_type); -static int ena_queue_start(struct ena_ring *ring); +static int ena_queue_start(struct rte_eth_dev *dev, struct ena_ring *ring); static int ena_queue_start_all(struct rte_eth_dev *dev, enum ena_ring_type ring_type); static void ena_stats_restart(struct rte_eth_dev *dev); +static uint64_t ena_get_rx_port_offloads(struct ena_adapter *adapter); +static uint64_t ena_get_tx_port_offloads(struct ena_adapter *adapter); +static uint64_t ena_get_rx_queue_offloads(struct ena_adapter *adapter); +static uint64_t ena_get_tx_queue_offloads(struct ena_adapter *adapter); static int ena_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info); -static int ena_rss_reta_update(struct rte_eth_dev *dev, - struct rte_eth_rss_reta_entry64 *reta_conf, - uint16_t reta_size); -static int ena_rss_reta_query(struct rte_eth_dev *dev, - struct rte_eth_rss_reta_entry64 *reta_conf, - uint16_t reta_size); static void ena_interrupt_handler_rte(void *cb_arg); static void ena_timer_wd_callback(struct rte_timer *timer, void *arg); static void ena_destroy_device(struct rte_eth_dev *eth_dev); @@ -246,6 +250,11 @@ static int ena_process_bool_devarg(const char *key, static int ena_parse_devargs(struct ena_adapter *adapter, struct rte_devargs *devargs); static int ena_copy_eni_stats(struct ena_adapter *adapter); +static int ena_setup_rx_intr(struct rte_eth_dev *dev); +static int ena_rx_queue_intr_enable(struct rte_eth_dev *dev, + uint16_t queue_id); +static int ena_rx_queue_intr_disable(struct rte_eth_dev *dev, + uint16_t queue_id); static const struct eth_dev_ops ena_dev_ops = { .dev_configure = ena_dev_configure, @@ -266,27 +275,15 @@ static const struct eth_dev_ops ena_dev_ops = { .dev_reset = ena_dev_reset, .reta_update = ena_rss_reta_update, .reta_query = ena_rss_reta_query, + .rx_queue_intr_enable = ena_rx_queue_intr_enable, + .rx_queue_intr_disable = ena_rx_queue_intr_disable, + .rss_hash_update = ena_rss_hash_update, + .rss_hash_conf_get = ena_rss_hash_conf_get, }; -void ena_rss_key_fill(void *key, size_t size) -{ - static bool key_generated; - static uint8_t default_key[ENA_HASH_KEY_SIZE]; - size_t i; - - RTE_ASSERT(size <= ENA_HASH_KEY_SIZE); - - if (!key_generated) { - for (i = 0; i < ENA_HASH_KEY_SIZE; ++i) - default_key[i] = rte_rand() & 0xff; - key_generated = true; - } - - rte_memcpy(key, default_key, size); -} - static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf, - struct ena_com_rx_ctx *ena_rx_ctx) + struct ena_com_rx_ctx *ena_rx_ctx, + bool fill_hash) { uint64_t ol_flags = 0; uint32_t packet_type = 0; @@ -296,21 +293,29 @@ static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf, else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP) packet_type |= RTE_PTYPE_L4_UDP; - if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) + if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) { packet_type |= RTE_PTYPE_L3_IPV4; - else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) + if (unlikely(ena_rx_ctx->l3_csum_err)) + ol_flags |= PKT_RX_IP_CKSUM_BAD; + else + ol_flags |= PKT_RX_IP_CKSUM_GOOD; + } else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) { packet_type |= RTE_PTYPE_L3_IPV6; + } - if (!ena_rx_ctx->l4_csum_checked) + if (!ena_rx_ctx->l4_csum_checked || ena_rx_ctx->frag) ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN; else - if (unlikely(ena_rx_ctx->l4_csum_err) && !ena_rx_ctx->frag) + if (unlikely(ena_rx_ctx->l4_csum_err)) ol_flags |= PKT_RX_L4_CKSUM_BAD; else - ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN; + ol_flags |= PKT_RX_L4_CKSUM_GOOD; - if (unlikely(ena_rx_ctx->l3_csum_err)) - ol_flags |= PKT_RX_IP_CKSUM_BAD; + if (fill_hash && + likely((packet_type & ENA_PTYPE_HAS_HASH) && !ena_rx_ctx->frag)) { + ol_flags |= PKT_RX_RSS_HASH; + mbuf->hash.rss = ena_rx_ctx->hash; + } mbuf->ol_flags = ol_flags; mbuf->packet_type = packet_type; @@ -378,20 +383,6 @@ static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf, } } -static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id) -{ - if (likely(req_id < rx_ring->ring_size)) - return 0; - - PMD_DRV_LOG(ERR, "Invalid rx req_id: %hu\n", req_id); - - rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID; - rx_ring->adapter->trigger_reset = true; - ++rx_ring->rx_stats.bad_req_id; - - return -EFAULT; -} - static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id) { struct ena_tx_buffer *tx_info = NULL; @@ -403,9 +394,9 @@ static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id) } if (tx_info) - PMD_DRV_LOG(ERR, "tx_info doesn't have valid mbuf\n"); + PMD_TX_LOG(ERR, "tx_info doesn't have valid mbuf\n"); else - PMD_DRV_LOG(ERR, "Invalid req_id: %hu\n", req_id); + PMD_TX_LOG(ERR, "Invalid req_id: %hu\n", req_id); /* Trigger device reset */ ++tx_ring->tx_stats.bad_req_id; @@ -443,7 +434,8 @@ static void ena_config_host_info(struct ena_com_dev *ena_dev) host_info->num_cpus = rte_lcore_count(); host_info->driver_supported_features = - ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK; + ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK | + ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK; rc = ena_com_set_host_attributes(ena_dev); if (rc) { @@ -462,11 +454,11 @@ err: } /* This function calculates the number of xstats based on the current config */ -static unsigned int ena_xstats_calc_num(struct rte_eth_dev *dev) +static unsigned int ena_xstats_calc_num(struct rte_eth_dev_data *data) { return ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENI + - (dev->data->nb_tx_queues * ENA_STATS_ARRAY_TX) + - (dev->data->nb_rx_queues * ENA_STATS_ARRAY_RX); + (data->nb_tx_queues * ENA_STATS_ARRAY_TX) + + (data->nb_rx_queues * ENA_STATS_ARRAY_RX); } static void ena_config_debug_area(struct ena_adapter *adapter) @@ -474,7 +466,7 @@ static void ena_config_debug_area(struct ena_adapter *adapter) u32 debug_area_size; int rc, ss_count; - ss_count = ena_xstats_calc_num(adapter->rte_dev); + ss_count = ena_xstats_calc_num(adapter->edev_data); /* allocate 32 bytes for each string and 64bit for the value */ debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count; @@ -505,9 +497,13 @@ static int ena_close(struct rte_eth_dev *dev) struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; struct ena_adapter *adapter = dev->data->dev_private; + int ret = 0; + + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return 0; if (adapter->state == ENA_ADAPTER_STATE_RUNNING) - ena_stop(dev); + ret = ena_stop(dev); adapter->state = ENA_ADAPTER_STATE_CLOSED; ena_rx_queue_release_all(dev); @@ -519,7 +515,7 @@ static int ena_close(struct rte_eth_dev *dev) rte_intr_disable(intr_handle); rte_intr_callback_unregister(intr_handle, ena_interrupt_handler_rte, - adapter); + dev); /* * MAC is not allocated dynamically. Setting NULL should prevent from @@ -527,7 +523,7 @@ static int ena_close(struct rte_eth_dev *dev) */ dev->data->mac_addrs = NULL; - return 0; + return ret; } static int @@ -535,182 +531,41 @@ ena_dev_reset(struct rte_eth_dev *dev) { int rc = 0; + /* Cannot release memory in secondary process */ + if (rte_eal_process_type() != RTE_PROC_PRIMARY) { + PMD_DRV_LOG(WARNING, "dev_reset not supported in secondary.\n"); + return -EPERM; + } + ena_destroy_device(dev); rc = eth_ena_dev_init(dev); if (rc) - PMD_INIT_LOG(CRIT, "Cannot initialize device"); - - return rc; -} - -static int ena_rss_reta_update(struct rte_eth_dev *dev, - struct rte_eth_rss_reta_entry64 *reta_conf, - uint16_t reta_size) -{ - struct ena_adapter *adapter = dev->data->dev_private; - struct ena_com_dev *ena_dev = &adapter->ena_dev; - int rc, i; - u16 entry_value; - int conf_idx; - int idx; - - if ((reta_size == 0) || (reta_conf == NULL)) - return -EINVAL; - - if (reta_size > ENA_RX_RSS_TABLE_SIZE) { - PMD_DRV_LOG(WARNING, - "indirection table %d is bigger than supported (%d)\n", - reta_size, ENA_RX_RSS_TABLE_SIZE); - return -EINVAL; - } - - for (i = 0 ; i < reta_size ; i++) { - /* each reta_conf is for 64 entries. - * to support 128 we use 2 conf of 64 - */ - conf_idx = i / RTE_RETA_GROUP_SIZE; - idx = i % RTE_RETA_GROUP_SIZE; - if (TEST_BIT(reta_conf[conf_idx].mask, idx)) { - entry_value = - ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]); - - rc = ena_com_indirect_table_fill_entry(ena_dev, - i, - entry_value); - if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) { - PMD_DRV_LOG(ERR, - "Cannot fill indirect table\n"); - return rc; - } - } - } - - rte_spinlock_lock(&adapter->admin_lock); - rc = ena_com_indirect_table_set(ena_dev); - rte_spinlock_unlock(&adapter->admin_lock); - if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) { - PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n"); - return rc; - } - - PMD_DRV_LOG(DEBUG, "%s(): RSS configured %d entries for port %d\n", - __func__, reta_size, adapter->rte_dev->data->port_id); - - return 0; -} - -/* Query redirection table. */ -static int ena_rss_reta_query(struct rte_eth_dev *dev, - struct rte_eth_rss_reta_entry64 *reta_conf, - uint16_t reta_size) -{ - struct ena_adapter *adapter = dev->data->dev_private; - struct ena_com_dev *ena_dev = &adapter->ena_dev; - int rc; - int i; - u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0}; - int reta_conf_idx; - int reta_idx; - - if (reta_size == 0 || reta_conf == NULL || - (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL))) - return -EINVAL; - - rte_spinlock_lock(&adapter->admin_lock); - rc = ena_com_indirect_table_get(ena_dev, indirect_table); - rte_spinlock_unlock(&adapter->admin_lock); - if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) { - PMD_DRV_LOG(ERR, "cannot get indirect table\n"); - return -ENOTSUP; - } - - for (i = 0 ; i < reta_size ; i++) { - reta_conf_idx = i / RTE_RETA_GROUP_SIZE; - reta_idx = i % RTE_RETA_GROUP_SIZE; - if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx)) - reta_conf[reta_conf_idx].reta[reta_idx] = - ENA_IO_RXQ_IDX_REV(indirect_table[i]); - } - - return 0; -} - -static int ena_rss_init_default(struct ena_adapter *adapter) -{ - struct ena_com_dev *ena_dev = &adapter->ena_dev; - uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues; - int rc, i; - u32 val; - - rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE); - if (unlikely(rc)) { - PMD_DRV_LOG(ERR, "Cannot init indirect table\n"); - goto err_rss_init; - } - - for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) { - val = i % nb_rx_queues; - rc = ena_com_indirect_table_fill_entry(ena_dev, i, - ENA_IO_RXQ_IDX(val)); - if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { - PMD_DRV_LOG(ERR, "Cannot fill indirect table\n"); - goto err_fill_indir; - } - } - - rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL, - ENA_HASH_KEY_SIZE, 0xFFFFFFFF); - if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { - PMD_DRV_LOG(INFO, "Cannot fill hash function\n"); - goto err_fill_indir; - } - - rc = ena_com_set_default_hash_ctrl(ena_dev); - if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { - PMD_DRV_LOG(INFO, "Cannot fill hash control\n"); - goto err_fill_indir; - } - - rc = ena_com_indirect_table_set(ena_dev); - if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { - PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n"); - goto err_fill_indir; - } - PMD_DRV_LOG(DEBUG, "RSS configured for port %d\n", - adapter->rte_dev->data->port_id); - - return 0; - -err_fill_indir: - ena_com_rss_destroy(ena_dev); -err_rss_init: + PMD_INIT_LOG(CRIT, "Cannot initialize device\n"); return rc; } static void ena_rx_queue_release_all(struct rte_eth_dev *dev) { - struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues; int nb_queues = dev->data->nb_rx_queues; int i; for (i = 0; i < nb_queues; i++) - ena_rx_queue_release(queues[i]); + ena_rx_queue_release(dev, i); } static void ena_tx_queue_release_all(struct rte_eth_dev *dev) { - struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues; int nb_queues = dev->data->nb_tx_queues; int i; for (i = 0; i < nb_queues; i++) - ena_tx_queue_release(queues[i]); + ena_tx_queue_release(dev, i); } -static void ena_rx_queue_release(void *queue) +static void ena_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid) { - struct ena_ring *ring = (struct ena_ring *)queue; + struct ena_ring *ring = dev->data->rx_queues[qid]; /* Free ring resources */ if (ring->rx_buffer_info) @@ -727,13 +582,13 @@ static void ena_rx_queue_release(void *queue) ring->configured = 0; - PMD_DRV_LOG(NOTICE, "RX Queue %d:%d released\n", + PMD_DRV_LOG(NOTICE, "Rx queue %d:%d released\n", ring->port_id, ring->id); } -static void ena_tx_queue_release(void *queue) +static void ena_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid) { - struct ena_ring *ring = (struct ena_ring *)queue; + struct ena_ring *ring = dev->data->tx_queues[qid]; /* Free ring resources */ if (ring->push_buf_intermediate_buf) @@ -751,7 +606,7 @@ static void ena_tx_queue_release(void *queue) ring->configured = 0; - PMD_DRV_LOG(NOTICE, "TX Queue %d:%d released\n", + PMD_DRV_LOG(NOTICE, "Tx queue %d:%d released\n", ring->port_id, ring->id); } @@ -775,8 +630,10 @@ static void ena_tx_queue_release_bufs(struct ena_ring *ring) for (i = 0; i < ring->ring_size; ++i) { struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i]; - if (tx_buf->mbuf) + if (tx_buf->mbuf) { rte_pktmbuf_free(tx_buf->mbuf); + tx_buf->mbuf = NULL; + } } } @@ -814,19 +671,19 @@ static int ena_queue_start_all(struct rte_eth_dev *dev, if (ring_type == ENA_RING_TYPE_RX) { ena_assert_msg( dev->data->rx_queues[i] == &queues[i], - "Inconsistent state of rx queues\n"); + "Inconsistent state of Rx queues\n"); } else { ena_assert_msg( dev->data->tx_queues[i] == &queues[i], - "Inconsistent state of tx queues\n"); + "Inconsistent state of Tx queues\n"); } - rc = ena_queue_start(&queues[i]); + rc = ena_queue_start(dev, &queues[i]); if (rc) { PMD_INIT_LOG(ERR, - "failed to start queue %d type(%d)", - i, ring_type); + "Failed to start queue[%d] of type(%d)\n", + i, ring_type); goto err; } } @@ -842,26 +699,14 @@ err: return rc; } -static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter) -{ - uint32_t max_frame_len = adapter->max_mtu; - - if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads & - DEV_RX_OFFLOAD_JUMBO_FRAME) - max_frame_len = - adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len; - - return max_frame_len; -} - static int ena_check_valid_conf(struct ena_adapter *adapter) { - uint32_t max_frame_len = ena_get_mtu_conf(adapter); + uint32_t mtu = adapter->edev_data->mtu; - if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) { - PMD_INIT_LOG(ERR, "Unsupported MTU of %d. " - "max mtu: %d, min mtu: %d", - max_frame_len, adapter->max_mtu, ENA_MIN_MTU); + if (mtu > adapter->max_mtu || mtu < ENA_MIN_MTU) { + PMD_INIT_LOG(ERR, + "Unsupported MTU of %d. Max MTU: %d, min MTU: %d\n", + mtu, adapter->max_mtu, ENA_MIN_MTU); return ENA_COM_UNSUPPORTED; } @@ -930,7 +775,7 @@ ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx, ENA_ADMIN_PLACEMENT_POLICY_DEV)) { max_tx_queue_size /= 2; PMD_INIT_LOG(INFO, - "Forcing large headers and decreasing maximum TX queue size to %d\n", + "Forcing large headers and decreasing maximum Tx queue size to %d\n", max_tx_queue_size); } else { PMD_INIT_LOG(ERR, @@ -939,7 +784,7 @@ ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx, } if (unlikely(max_rx_queue_size == 0 || max_tx_queue_size == 0)) { - PMD_INIT_LOG(ERR, "Invalid queue size"); + PMD_INIT_LOG(ERR, "Invalid queue size\n"); return -EFAULT; } @@ -1034,11 +879,10 @@ static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) ena_dev = &adapter->ena_dev; ena_assert_msg(ena_dev != NULL, "Uninitialized device\n"); - if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) { + if (mtu > adapter->max_mtu || mtu < ENA_MIN_MTU) { PMD_DRV_LOG(ERR, - "Invalid MTU setting. new_mtu: %d " - "max mtu: %d min mtu: %d\n", - mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU); + "Invalid MTU setting. New MTU: %d, max MTU: %d, min MTU: %d\n", + mtu, adapter->max_mtu, ENA_MIN_MTU); return -EINVAL; } @@ -1046,7 +890,7 @@ static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) if (rc) PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu); else - PMD_DRV_LOG(NOTICE, "Set MTU: %d\n", mtu); + PMD_DRV_LOG(NOTICE, "MTU set to: %d\n", mtu); return rc; } @@ -1057,10 +901,20 @@ static int ena_start(struct rte_eth_dev *dev) uint64_t ticks; int rc = 0; + /* Cannot allocate memory in secondary process */ + if (rte_eal_process_type() != RTE_PROC_PRIMARY) { + PMD_DRV_LOG(WARNING, "dev_start not supported in secondary.\n"); + return -EPERM; + } + rc = ena_check_valid_conf(adapter); if (rc) return rc; + rc = ena_setup_rx_intr(dev); + if (rc) + return rc; + rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX); if (rc) return rc; @@ -1069,9 +923,8 @@ static int ena_start(struct rte_eth_dev *dev) if (rc) goto err_start_tx; - if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode & - ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) { - rc = ena_rss_init_default(adapter); + if (adapter->edev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) { + rc = ena_rss_configure(adapter); if (rc) goto err_rss_init; } @@ -1083,7 +936,7 @@ static int ena_start(struct rte_eth_dev *dev) ticks = rte_get_timer_hz(); rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(), - ena_timer_wd_callback, adapter); + ena_timer_wd_callback, dev); ++adapter->dev_stats.dev_start; adapter->state = ENA_ADAPTER_STATE_RUNNING; @@ -1097,12 +950,20 @@ err_start_tx: return rc; } -static void ena_stop(struct rte_eth_dev *dev) +static int ena_stop(struct rte_eth_dev *dev) { struct ena_adapter *adapter = dev->data->dev_private; struct ena_com_dev *ena_dev = &adapter->ena_dev; + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); + struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; int rc; + /* Cannot free memory in secondary process */ + if (rte_eal_process_type() != RTE_PROC_PRIMARY) { + PMD_DRV_LOG(WARNING, "dev_stop not supported in secondary.\n"); + return -EPERM; + } + rte_timer_stop_sync(&adapter->timer_wd); ena_queue_stop_all(dev, ENA_RING_TYPE_TX); ena_queue_stop_all(dev, ENA_RING_TYPE_RX); @@ -1110,17 +971,32 @@ static void ena_stop(struct rte_eth_dev *dev) if (adapter->trigger_reset) { rc = ena_com_dev_reset(ena_dev, adapter->reset_reason); if (rc) - PMD_DRV_LOG(ERR, "Device reset failed rc=%d\n", rc); + PMD_DRV_LOG(ERR, "Device reset failed, rc: %d\n", rc); } + rte_intr_disable(intr_handle); + + rte_intr_efd_disable(intr_handle); + if (intr_handle->intr_vec != NULL) { + rte_free(intr_handle->intr_vec); + intr_handle->intr_vec = NULL; + } + + rte_intr_enable(intr_handle); + ++adapter->dev_stats.dev_stop; adapter->state = ENA_ADAPTER_STATE_STOPPED; + dev->data->dev_started = 0; + + return 0; } -static int ena_create_io_queue(struct ena_ring *ring) +static int ena_create_io_queue(struct rte_eth_dev *dev, struct ena_ring *ring) { - struct ena_adapter *adapter; - struct ena_com_dev *ena_dev; + struct ena_adapter *adapter = ring->adapter; + struct ena_com_dev *ena_dev = &adapter->ena_dev; + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); + struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; struct ena_com_create_io_ctx ctx = /* policy set to _HOST just to satisfy icc compiler */ { ENA_ADMIN_PLACEMENT_POLICY_HOST, @@ -1129,9 +1005,7 @@ static int ena_create_io_queue(struct ena_ring *ring) unsigned int i; int rc; - adapter = ring->adapter; - ena_dev = &adapter->ena_dev; - + ctx.msix_vector = -1; if (ring->type == ENA_RING_TYPE_TX) { ena_qid = ENA_IO_TXQ_IDX(ring->id); ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX; @@ -1141,18 +1015,19 @@ static int ena_create_io_queue(struct ena_ring *ring) } else { ena_qid = ENA_IO_RXQ_IDX(ring->id); ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX; + if (rte_intr_dp_is_en(intr_handle)) + ctx.msix_vector = intr_handle->intr_vec[ring->id]; for (i = 0; i < ring->ring_size; i++) ring->empty_rx_reqs[i] = i; } ctx.queue_size = ring->ring_size; ctx.qid = ena_qid; - ctx.msix_vector = -1; /* interrupts not used */ ctx.numa_node = ring->numa_socket_id; rc = ena_com_create_io_queue(ena_dev, &ctx); if (rc) { PMD_DRV_LOG(ERR, - "failed to create io queue #%d (qid:%d) rc: %d\n", + "Failed to create IO queue[%d] (qid:%d), rc: %d\n", ring->id, ena_qid, rc); return rc; } @@ -1162,7 +1037,7 @@ static int ena_create_io_queue(struct ena_ring *ring) &ring->ena_com_io_cq); if (rc) { PMD_DRV_LOG(ERR, - "Failed to get io queue handlers. queue num %d rc: %d\n", + "Failed to get IO queue[%d] handlers, rc: %d\n", ring->id, rc); ena_com_destroy_io_queue(ena_dev, ena_qid); return rc; @@ -1171,6 +1046,10 @@ static int ena_create_io_queue(struct ena_ring *ring) if (ring->type == ENA_RING_TYPE_TX) ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node); + /* Start with Rx interrupts being masked. */ + if (ring->type == ENA_RING_TYPE_RX && rte_intr_dp_is_en(intr_handle)) + ena_rx_queue_intr_disable(dev, ring->id); + return 0; } @@ -1207,16 +1086,16 @@ static void ena_queue_stop_all(struct rte_eth_dev *dev, ena_queue_stop(&queues[i]); } -static int ena_queue_start(struct ena_ring *ring) +static int ena_queue_start(struct rte_eth_dev *dev, struct ena_ring *ring) { int rc, bufs_num; ena_assert_msg(ring->configured == 1, "Trying to start unconfigured queue\n"); - rc = ena_create_io_queue(ring); + rc = ena_create_io_queue(dev, ring); if (rc) { - PMD_INIT_LOG(ERR, "Failed to create IO queue!"); + PMD_INIT_LOG(ERR, "Failed to create IO queue\n"); return rc; } @@ -1234,9 +1113,13 @@ static int ena_queue_start(struct ena_ring *ring) if (rc != bufs_num) { ena_com_destroy_io_queue(&ring->adapter->ena_dev, ENA_IO_RXQ_IDX(ring->id)); - PMD_INIT_LOG(ERR, "Failed to populate rx ring !"); + PMD_INIT_LOG(ERR, "Failed to populate Rx ring\n"); return ENA_COM_FAULT; } + /* Flush per-core RX buffers pools cache as they can be used on other + * cores as well. + */ + rte_mempool_cache_flush(NULL, ring->mb_pool); return 0; } @@ -1250,64 +1133,68 @@ static int ena_tx_queue_setup(struct rte_eth_dev *dev, struct ena_ring *txq = NULL; struct ena_adapter *adapter = dev->data->dev_private; unsigned int i; + uint16_t dyn_thresh; txq = &adapter->tx_ring[queue_idx]; if (txq->configured) { PMD_DRV_LOG(CRIT, - "API violation. Queue %d is already configured\n", + "API violation. Queue[%d] is already configured\n", queue_idx); return ENA_COM_FAULT; } if (!rte_is_power_of_2(nb_desc)) { PMD_DRV_LOG(ERR, - "Unsupported size of TX queue: %d is not a power of 2.\n", + "Unsupported size of Tx queue: %d is not a power of 2.\n", nb_desc); return -EINVAL; } if (nb_desc > adapter->max_tx_ring_size) { PMD_DRV_LOG(ERR, - "Unsupported size of TX queue (max size: %d)\n", + "Unsupported size of Tx queue (max size: %d)\n", adapter->max_tx_ring_size); return -EINVAL; } - if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE) - nb_desc = adapter->max_tx_ring_size; - txq->port_id = dev->data->port_id; txq->next_to_clean = 0; txq->next_to_use = 0; txq->ring_size = nb_desc; txq->size_mask = nb_desc - 1; txq->numa_socket_id = socket_id; + txq->pkts_without_db = false; + txq->last_cleanup_ticks = 0; - txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info", - sizeof(struct ena_tx_buffer) * - txq->ring_size, - RTE_CACHE_LINE_SIZE); + txq->tx_buffer_info = rte_zmalloc_socket("txq->tx_buffer_info", + sizeof(struct ena_tx_buffer) * txq->ring_size, + RTE_CACHE_LINE_SIZE, + socket_id); if (!txq->tx_buffer_info) { - PMD_DRV_LOG(ERR, "failed to alloc mem for tx buffer info\n"); + PMD_DRV_LOG(ERR, + "Failed to allocate memory for Tx buffer info\n"); return -ENOMEM; } - txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs", - sizeof(u16) * txq->ring_size, - RTE_CACHE_LINE_SIZE); + txq->empty_tx_reqs = rte_zmalloc_socket("txq->empty_tx_reqs", + sizeof(uint16_t) * txq->ring_size, + RTE_CACHE_LINE_SIZE, + socket_id); if (!txq->empty_tx_reqs) { - PMD_DRV_LOG(ERR, "failed to alloc mem for tx reqs\n"); + PMD_DRV_LOG(ERR, + "Failed to allocate memory for empty Tx requests\n"); rte_free(txq->tx_buffer_info); return -ENOMEM; } txq->push_buf_intermediate_buf = - rte_zmalloc("txq->push_buf_intermediate_buf", - txq->tx_max_header_size, - RTE_CACHE_LINE_SIZE); + rte_zmalloc_socket("txq->push_buf_intermediate_buf", + txq->tx_max_header_size, + RTE_CACHE_LINE_SIZE, + socket_id); if (!txq->push_buf_intermediate_buf) { - PMD_DRV_LOG(ERR, "failed to alloc push buff for LLQ\n"); + PMD_DRV_LOG(ERR, "Failed to alloc push buffer for LLQ\n"); rte_free(txq->tx_buffer_info); rte_free(txq->empty_tx_reqs); return -ENOMEM; @@ -1316,10 +1203,21 @@ static int ena_tx_queue_setup(struct rte_eth_dev *dev, for (i = 0; i < txq->ring_size; i++) txq->empty_tx_reqs[i] = i; - if (tx_conf != NULL) { - txq->offloads = - tx_conf->offloads | dev->data->dev_conf.txmode.offloads; + txq->offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads; + + /* Check if caller provided the Tx cleanup threshold value. */ + if (tx_conf->tx_free_thresh != 0) { + txq->tx_free_thresh = tx_conf->tx_free_thresh; + } else { + dyn_thresh = txq->ring_size - + txq->ring_size / ENA_REFILL_THRESH_DIVIDER; + txq->tx_free_thresh = RTE_MAX(dyn_thresh, + txq->ring_size - ENA_REFILL_THRESH_PACKET); } + + txq->missing_tx_completion_threshold = + RTE_MIN(txq->ring_size / 2, ENA_DEFAULT_MISSING_COMP); + /* Store pointer to this queue in upper layer */ txq->configured = 1; dev->data->tx_queues[queue_idx] = txq; @@ -1331,35 +1229,33 @@ static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, uint16_t nb_desc, unsigned int socket_id, - __rte_unused const struct rte_eth_rxconf *rx_conf, + const struct rte_eth_rxconf *rx_conf, struct rte_mempool *mp) { struct ena_adapter *adapter = dev->data->dev_private; struct ena_ring *rxq = NULL; size_t buffer_size; int i; + uint16_t dyn_thresh; rxq = &adapter->rx_ring[queue_idx]; if (rxq->configured) { PMD_DRV_LOG(CRIT, - "API violation. Queue %d is already configured\n", + "API violation. Queue[%d] is already configured\n", queue_idx); return ENA_COM_FAULT; } - if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE) - nb_desc = adapter->max_rx_ring_size; - if (!rte_is_power_of_2(nb_desc)) { PMD_DRV_LOG(ERR, - "Unsupported size of RX queue: %d is not a power of 2.\n", + "Unsupported size of Rx queue: %d is not a power of 2.\n", nb_desc); return -EINVAL; } if (nb_desc > adapter->max_rx_ring_size) { PMD_DRV_LOG(ERR, - "Unsupported size of RX queue (max size: %d)\n", + "Unsupported size of Rx queue (max size: %d)\n", adapter->max_rx_ring_size); return -EINVAL; } @@ -1368,7 +1264,7 @@ static int ena_rx_queue_setup(struct rte_eth_dev *dev, buffer_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM; if (buffer_size < ENA_RX_BUF_MIN_SIZE) { PMD_DRV_LOG(ERR, - "Unsupported size of RX buffer: %zu (min size: %d)\n", + "Unsupported size of Rx buffer: %zu (min size: %d)\n", buffer_size, ENA_RX_BUF_MIN_SIZE); return -EINVAL; } @@ -1381,30 +1277,35 @@ static int ena_rx_queue_setup(struct rte_eth_dev *dev, rxq->numa_socket_id = socket_id; rxq->mb_pool = mp; - rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info", + rxq->rx_buffer_info = rte_zmalloc_socket("rxq->buffer_info", sizeof(struct ena_rx_buffer) * nb_desc, - RTE_CACHE_LINE_SIZE); + RTE_CACHE_LINE_SIZE, + socket_id); if (!rxq->rx_buffer_info) { - PMD_DRV_LOG(ERR, "failed to alloc mem for rx buffer info\n"); + PMD_DRV_LOG(ERR, + "Failed to allocate memory for Rx buffer info\n"); return -ENOMEM; } - rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer", - sizeof(struct rte_mbuf *) * nb_desc, - RTE_CACHE_LINE_SIZE); - + rxq->rx_refill_buffer = rte_zmalloc_socket("rxq->rx_refill_buffer", + sizeof(struct rte_mbuf *) * nb_desc, + RTE_CACHE_LINE_SIZE, + socket_id); if (!rxq->rx_refill_buffer) { - PMD_DRV_LOG(ERR, "failed to alloc mem for rx refill buffer\n"); + PMD_DRV_LOG(ERR, + "Failed to allocate memory for Rx refill buffer\n"); rte_free(rxq->rx_buffer_info); rxq->rx_buffer_info = NULL; return -ENOMEM; } - rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs", - sizeof(uint16_t) * nb_desc, - RTE_CACHE_LINE_SIZE); + rxq->empty_rx_reqs = rte_zmalloc_socket("rxq->empty_rx_reqs", + sizeof(uint16_t) * nb_desc, + RTE_CACHE_LINE_SIZE, + socket_id); if (!rxq->empty_rx_reqs) { - PMD_DRV_LOG(ERR, "failed to alloc mem for empty rx reqs\n"); + PMD_DRV_LOG(ERR, + "Failed to allocate memory for empty Rx requests\n"); rte_free(rxq->rx_buffer_info); rxq->rx_buffer_info = NULL; rte_free(rxq->rx_refill_buffer); @@ -1415,6 +1316,16 @@ static int ena_rx_queue_setup(struct rte_eth_dev *dev, for (i = 0; i < nb_desc; i++) rxq->empty_rx_reqs[i] = i; + rxq->offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads; + + if (rx_conf->rx_free_thresh != 0) { + rxq->rx_free_thresh = rx_conf->rx_free_thresh; + } else { + dyn_thresh = rxq->ring_size / ENA_REFILL_THRESH_DIVIDER; + rxq->rx_free_thresh = RTE_MIN(dyn_thresh, + (uint16_t)(ENA_REFILL_THRESH_PACKET)); + } + /* Store pointer to this queue in upper layer */ rxq->configured = 1; dev->data->rx_queues[queue_idx] = rxq; @@ -1435,7 +1346,7 @@ static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq, /* pass resource to device */ rc = ena_com_add_single_rx_desc(io_sq, &ebuf, id); if (unlikely(rc != 0)) - PMD_DRV_LOG(WARNING, "failed adding rx desc\n"); + PMD_RX_LOG(WARNING, "Failed adding Rx desc\n"); return rc; } @@ -1445,23 +1356,28 @@ static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count) unsigned int i; int rc; uint16_t next_to_use = rxq->next_to_use; - uint16_t in_use, req_id; + uint16_t req_id; +#ifdef RTE_ETHDEV_DEBUG_RX + uint16_t in_use; +#endif struct rte_mbuf **mbufs = rxq->rx_refill_buffer; if (unlikely(!count)) return 0; +#ifdef RTE_ETHDEV_DEBUG_RX in_use = rxq->ring_size - 1 - ena_com_free_q_entries(rxq->ena_com_io_sq); - ena_assert_msg(((in_use + count) < rxq->ring_size), - "bad ring state\n"); + if (unlikely((in_use + count) >= rxq->ring_size)) + PMD_RX_LOG(ERR, "Bad Rx ring state\n"); +#endif /* get resources for incoming packets */ - rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count); + rc = rte_pktmbuf_alloc_bulk(rxq->mb_pool, mbufs, count); if (unlikely(rc < 0)) { rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf); ++rxq->rx_stats.mbuf_alloc_fail; - PMD_RX_LOG(DEBUG, "there are no enough free buffers"); + PMD_RX_LOG(DEBUG, "There are not enough free buffers\n"); return 0; } @@ -1473,10 +1389,6 @@ static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count) rte_prefetch0(mbufs[i + 4]); req_id = rxq->empty_rx_reqs[next_to_use]; - rc = validate_rx_req_id(rxq, req_id); - if (unlikely(rc)) - break; - rx_info = &rxq->rx_buffer_info[req_id]; rc = ena_add_single_rx_desc(rxq->ena_com_io_sq, mbuf, req_id); @@ -1488,10 +1400,10 @@ static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count) } if (unlikely(i < count)) { - PMD_DRV_LOG(WARNING, "refilled rx qid %d with only %d " - "buffers (from %d)\n", rxq->id, i, count); - rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]), - count - i); + PMD_RX_LOG(WARNING, + "Refilled Rx queue[%d] with only %d/%d buffers\n", + rxq->id, i, count); + rte_pktmbuf_free_bulk(&mbufs[i], count - i); ++rxq->rx_stats.refill_partial; } @@ -1507,6 +1419,7 @@ static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count) } static int ena_device_init(struct ena_com_dev *ena_dev, + struct rte_pci_device *pdev, struct ena_com_dev_get_features_ctx *get_feat_ctx, bool *wd_state) { @@ -1517,29 +1430,27 @@ static int ena_device_init(struct ena_com_dev *ena_dev, /* Initialize mmio registers */ rc = ena_com_mmio_reg_read_request_init(ena_dev); if (rc) { - PMD_DRV_LOG(ERR, "failed to init mmio read less\n"); + PMD_DRV_LOG(ERR, "Failed to init MMIO read less\n"); return rc; } /* The PCIe configuration space revision id indicate if mmio reg * read is disabled. */ - readless_supported = - !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id - & ENA_MMIO_DISABLE_REG_READ); + readless_supported = !(pdev->id.class_id & ENA_MMIO_DISABLE_REG_READ); ena_com_set_mmio_read_mode(ena_dev, readless_supported); /* reset device */ rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL); if (rc) { - PMD_DRV_LOG(ERR, "cannot reset device\n"); + PMD_DRV_LOG(ERR, "Cannot reset device\n"); goto err_mmio_read_less; } /* check FW version */ rc = ena_com_validate_version(ena_dev); if (rc) { - PMD_DRV_LOG(ERR, "device version is too low\n"); + PMD_DRV_LOG(ERR, "Device version is too low\n"); goto err_mmio_read_less; } @@ -1549,7 +1460,7 @@ static int ena_device_init(struct ena_com_dev *ena_dev, rc = ena_com_admin_init(ena_dev, &aenq_handlers); if (rc) { PMD_DRV_LOG(ERR, - "cannot initialize ena admin queue with device\n"); + "Cannot initialize ENA admin queue\n"); goto err_mmio_read_less; } @@ -1565,7 +1476,7 @@ static int ena_device_init(struct ena_com_dev *ena_dev, rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx); if (rc) { PMD_DRV_LOG(ERR, - "cannot get attribute for ena device rc= %d\n", rc); + "Cannot get attribute for ENA device, rc: %d\n", rc); goto err_admin_init; } @@ -1578,7 +1489,7 @@ static int ena_device_init(struct ena_com_dev *ena_dev, aenq_groups &= get_feat_ctx->aenq.supported_groups; rc = ena_com_set_aenq_config(ena_dev, aenq_groups); if (rc) { - PMD_DRV_LOG(ERR, "Cannot configure aenq groups rc: %d\n", rc); + PMD_DRV_LOG(ERR, "Cannot configure AENQ groups, rc: %d\n", rc); goto err_admin_init; } @@ -1597,12 +1508,13 @@ err_mmio_read_less: static void ena_interrupt_handler_rte(void *cb_arg) { - struct ena_adapter *adapter = cb_arg; + struct rte_eth_dev *dev = cb_arg; + struct ena_adapter *adapter = dev->data->dev_private; struct ena_com_dev *ena_dev = &adapter->ena_dev; ena_com_admin_q_comp_intr_handler(ena_dev); if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED)) - ena_com_aenq_intr_handler(ena_dev, adapter); + ena_com_aenq_intr_handler(ena_dev, dev); } static void check_for_missing_keep_alive(struct ena_adapter *adapter) @@ -1626,20 +1538,102 @@ static void check_for_missing_keep_alive(struct ena_adapter *adapter) static void check_for_admin_com_state(struct ena_adapter *adapter) { if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) { - PMD_DRV_LOG(ERR, "ENA admin queue is not in running state!\n"); + PMD_DRV_LOG(ERR, "ENA admin queue is not in running state\n"); adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO; adapter->trigger_reset = true; } } +static int check_for_tx_completion_in_queue(struct ena_adapter *adapter, + struct ena_ring *tx_ring) +{ + struct ena_tx_buffer *tx_buf; + uint64_t timestamp; + uint64_t completion_delay; + uint32_t missed_tx = 0; + unsigned int i; + int rc = 0; + + for (i = 0; i < tx_ring->ring_size; ++i) { + tx_buf = &tx_ring->tx_buffer_info[i]; + timestamp = tx_buf->timestamp; + + if (timestamp == 0) + continue; + + completion_delay = rte_get_timer_cycles() - timestamp; + if (completion_delay > adapter->missing_tx_completion_to) { + if (unlikely(!tx_buf->print_once)) { + PMD_TX_LOG(WARNING, + "Found a Tx that wasn't completed on time, qid %d, index %d. " + "Missing Tx outstanding for %" PRIu64 " msecs.\n", + tx_ring->id, i, completion_delay / + rte_get_timer_hz() * 1000); + tx_buf->print_once = true; + } + ++missed_tx; + } + } + + if (unlikely(missed_tx > tx_ring->missing_tx_completion_threshold)) { + PMD_DRV_LOG(ERR, + "The number of lost Tx completions is above the threshold (%d > %d). " + "Trigger the device reset.\n", + missed_tx, + tx_ring->missing_tx_completion_threshold); + adapter->reset_reason = ENA_REGS_RESET_MISS_TX_CMPL; + adapter->trigger_reset = true; + rc = -EIO; + } + + tx_ring->tx_stats.missed_tx += missed_tx; + + return rc; +} + +static void check_for_tx_completions(struct ena_adapter *adapter) +{ + struct ena_ring *tx_ring; + uint64_t tx_cleanup_delay; + size_t qid; + int budget; + uint16_t nb_tx_queues = adapter->edev_data->nb_tx_queues; + + if (adapter->missing_tx_completion_to == ENA_HW_HINTS_NO_TIMEOUT) + return; + + nb_tx_queues = adapter->edev_data->nb_tx_queues; + budget = adapter->missing_tx_completion_budget; + + qid = adapter->last_tx_comp_qid; + while (budget-- > 0) { + tx_ring = &adapter->tx_ring[qid]; + + /* Tx cleanup is called only by the burst function and can be + * called dynamically by the application. Also cleanup is + * limited by the threshold. To avoid false detection of the + * missing HW Tx completion, get the delay since last cleanup + * function was called. + */ + tx_cleanup_delay = rte_get_timer_cycles() - + tx_ring->last_cleanup_ticks; + if (tx_cleanup_delay < adapter->tx_cleanup_stall_delay) + check_for_tx_completion_in_queue(adapter, tx_ring); + qid = (qid + 1) % nb_tx_queues; + } + + adapter->last_tx_comp_qid = qid; +} + static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer, void *arg) { - struct ena_adapter *adapter = arg; - struct rte_eth_dev *dev = adapter->rte_dev; + struct rte_eth_dev *dev = arg; + struct ena_adapter *adapter = dev->data->dev_private; check_for_missing_keep_alive(adapter); check_for_admin_com_state(adapter); + check_for_tx_completions(adapter); if (unlikely(adapter->trigger_reset)) { PMD_DRV_LOG(ERR, "Trigger reset is on\n"); @@ -1689,8 +1683,8 @@ ena_set_queues_placement_policy(struct ena_adapter *adapter, rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations); if (unlikely(rc)) { - PMD_INIT_LOG(WARNING, "Failed to config dev mode. " - "Fallback to host mode policy."); + PMD_INIT_LOG(WARNING, + "Failed to config dev mode. Fallback to host mode policy.\n"); ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; return 0; } @@ -1700,8 +1694,8 @@ ena_set_queues_placement_policy(struct ena_adapter *adapter, return 0; if (!adapter->dev_mem_base) { - PMD_DRV_LOG(ERR, "Unable to access LLQ bar resource. " - "Fallback to host mode policy.\n."); + PMD_DRV_LOG(ERR, + "Unable to access LLQ BAR resource. Fallback to host mode policy.\n"); ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; return 0; } @@ -1741,13 +1735,57 @@ static uint32_t ena_calc_max_io_queue_num(struct ena_com_dev *ena_dev, max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_cq_num); if (unlikely(max_num_io_queues == 0)) { - PMD_DRV_LOG(ERR, "Number of IO queues should not be 0\n"); + PMD_DRV_LOG(ERR, "Number of IO queues cannot not be 0\n"); return -EFAULT; } return max_num_io_queues; } +static void +ena_set_offloads(struct ena_offloads *offloads, + struct ena_admin_feature_offload_desc *offload_desc) +{ + if (offload_desc->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) + offloads->tx_offloads |= ENA_IPV4_TSO; + + /* Tx IPv4 checksum offloads */ + if (offload_desc->tx & + ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK) + offloads->tx_offloads |= ENA_L3_IPV4_CSUM; + if (offload_desc->tx & + ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK) + offloads->tx_offloads |= ENA_L4_IPV4_CSUM; + if (offload_desc->tx & + ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) + offloads->tx_offloads |= ENA_L4_IPV4_CSUM_PARTIAL; + + /* Tx IPv6 checksum offloads */ + if (offload_desc->tx & + ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK) + offloads->tx_offloads |= ENA_L4_IPV6_CSUM; + if (offload_desc->tx & + ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK) + offloads->tx_offloads |= ENA_L4_IPV6_CSUM_PARTIAL; + + /* Rx IPv4 checksum offloads */ + if (offload_desc->rx_supported & + ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK) + offloads->rx_offloads |= ENA_L3_IPV4_CSUM; + if (offload_desc->rx_supported & + ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) + offloads->rx_offloads |= ENA_L4_IPV4_CSUM; + + /* Rx IPv6 checksum offloads */ + if (offload_desc->rx_supported & + ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK) + offloads->rx_offloads |= ENA_L4_IPV6_CSUM; + + if (offload_desc->rx_supported & + ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK) + offloads->rx_offloads |= ENA_RX_RSS_HASH; +} + static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) { struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 }; @@ -1772,16 +1810,16 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) if (rte_eal_process_type() != RTE_PROC_PRIMARY) return 0; + eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; + memset(adapter, 0, sizeof(struct ena_adapter)); ena_dev = &adapter->ena_dev; - adapter->rte_eth_dev_data = eth_dev->data; - adapter->rte_dev = eth_dev; + adapter->edev_data = eth_dev->data; pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); - adapter->pdev = pci_dev; - PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d", + PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d\n", pci_dev->addr.domain, pci_dev->addr.bus, pci_dev->addr.devid, @@ -1793,13 +1831,14 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr; if (!adapter->regs) { - PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)", + PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)\n", ENA_REGS_BAR); return -ENXIO; } ena_dev->reg_bar = adapter->regs; - ena_dev->dmadev = adapter->pdev; + /* This is a dummy pointer for ena_com functions. */ + ena_dev->dmadev = adapter; adapter->id_number = adapters_found; @@ -1813,9 +1852,9 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) } /* device specific initialization routine */ - rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state); + rc = ena_device_init(ena_dev, pci_dev, &get_feat_ctx, &wd_state); if (rc) { - PMD_INIT_LOG(CRIT, "Failed to init ENA device"); + PMD_INIT_LOG(CRIT, "Failed to init ENA device\n"); goto err; } adapter->wd_state = wd_state; @@ -1825,7 +1864,7 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) rc = ena_set_queues_placement_policy(adapter, ena_dev, &get_feat_ctx.llq, &llq_config); if (unlikely(rc)) { - PMD_INIT_LOG(CRIT, "Failed to set placement policy"); + PMD_INIT_LOG(CRIT, "Failed to set placement policy\n"); return rc; } @@ -1868,14 +1907,7 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) /* Set max MTU for this device */ adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu; - /* set device support for offloads */ - adapter->offloads.tso4_supported = (get_feat_ctx.offload.tx & - ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0; - adapter->offloads.tx_csum_supported = (get_feat_ctx.offload.tx & - ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) != 0; - adapter->offloads.rx_csum_supported = - (get_feat_ctx.offload.rx_supported & - ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) != 0; + ena_set_offloads(&adapter->offloads, &get_feat_ctx.offload); /* Copy MAC address and point DPDK to it */ eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr; @@ -1883,26 +1915,27 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) get_feat_ctx.dev_attr.mac_addr, (struct rte_ether_addr *)adapter->mac_addr); - /* - * Pass the information to the rte_eth_dev_close() that it should also - * release the private port resources. - */ - eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; + rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE); + if (unlikely(rc != 0)) { + PMD_DRV_LOG(ERR, "Failed to initialize RSS in ENA device\n"); + goto err_delete_debug_area; + } adapter->drv_stats = rte_zmalloc("adapter stats", sizeof(*adapter->drv_stats), RTE_CACHE_LINE_SIZE); if (!adapter->drv_stats) { - PMD_DRV_LOG(ERR, "failed to alloc mem for adapter stats\n"); + PMD_DRV_LOG(ERR, + "Failed to allocate memory for adapter statistics\n"); rc = -ENOMEM; - goto err_delete_debug_area; + goto err_rss_destroy; } rte_spinlock_init(&adapter->admin_lock); rte_intr_callback_register(intr_handle, ena_interrupt_handler_rte, - adapter); + eth_dev); rte_intr_enable(intr_handle); ena_com_set_admin_polling_mode(ena_dev, false); ena_com_admin_aenq_enable(ena_dev); @@ -1916,6 +1949,8 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) return 0; +err_rss_destroy: + ena_com_rss_destroy(ena_dev); err_delete_debug_area: ena_com_delete_debug_area(ena_dev); @@ -1940,6 +1975,8 @@ static void ena_destroy_device(struct rte_eth_dev *eth_dev) if (adapter->state != ENA_ADAPTER_STATE_CLOSED) ena_close(eth_dev); + ena_com_rss_destroy(ena_dev); + ena_com_delete_debug_area(ena_dev); ena_com_delete_host_info(ena_dev); @@ -1958,11 +1995,6 @@ static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev) ena_destroy_device(eth_dev); - eth_dev->dev_ops = NULL; - eth_dev->rx_pkt_burst = NULL; - eth_dev->tx_pkt_burst = NULL; - eth_dev->tx_pkt_prepare = NULL; - return 0; } @@ -1972,8 +2004,32 @@ static int ena_dev_configure(struct rte_eth_dev *dev) adapter->state = ENA_ADAPTER_STATE_CONFIG; + if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) + dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; + dev->data->dev_conf.txmode.offloads |= DEV_TX_OFFLOAD_MULTI_SEGS; + + /* Scattered Rx cannot be turned off in the HW, so this capability must + * be forced. + */ + dev->data->scattered_rx = 1; + + adapter->last_tx_comp_qid = 0; + + adapter->missing_tx_completion_budget = + RTE_MIN(ENA_MONITORED_TX_QUEUES, dev->data->nb_tx_queues); + + adapter->missing_tx_completion_to = ENA_TX_TIMEOUT; + /* To avoid detection of the spurious Tx completion timeout due to + * application not calling the Tx cleanup function, set timeout for the + * Tx queue which should be half of the missing completion timeout for a + * safety. If there will be a lot of missing Tx completions in the + * queue, they will be detected sooner or later. + */ + adapter->tx_cleanup_stall_delay = adapter->missing_tx_completion_to / 2; + adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads; adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads; + return 0; } @@ -2006,12 +2062,65 @@ static void ena_init_rings(struct ena_adapter *adapter, } } +static uint64_t ena_get_rx_port_offloads(struct ena_adapter *adapter) +{ + uint64_t port_offloads = 0; + + if (adapter->offloads.rx_offloads & ENA_L3_IPV4_CSUM) + port_offloads |= DEV_RX_OFFLOAD_IPV4_CKSUM; + + if (adapter->offloads.rx_offloads & + (ENA_L4_IPV4_CSUM | ENA_L4_IPV6_CSUM)) + port_offloads |= + DEV_RX_OFFLOAD_UDP_CKSUM | DEV_RX_OFFLOAD_TCP_CKSUM; + + if (adapter->offloads.rx_offloads & ENA_RX_RSS_HASH) + port_offloads |= DEV_RX_OFFLOAD_RSS_HASH; + + port_offloads |= DEV_RX_OFFLOAD_SCATTER; + + return port_offloads; +} + +static uint64_t ena_get_tx_port_offloads(struct ena_adapter *adapter) +{ + uint64_t port_offloads = 0; + + if (adapter->offloads.tx_offloads & ENA_IPV4_TSO) + port_offloads |= DEV_TX_OFFLOAD_TCP_TSO; + + if (adapter->offloads.tx_offloads & ENA_L3_IPV4_CSUM) + port_offloads |= DEV_TX_OFFLOAD_IPV4_CKSUM; + if (adapter->offloads.tx_offloads & + (ENA_L4_IPV4_CSUM_PARTIAL | ENA_L4_IPV4_CSUM | + ENA_L4_IPV6_CSUM | ENA_L4_IPV6_CSUM_PARTIAL)) + port_offloads |= + DEV_TX_OFFLOAD_UDP_CKSUM | DEV_TX_OFFLOAD_TCP_CKSUM; + + port_offloads |= DEV_TX_OFFLOAD_MULTI_SEGS; + + return port_offloads; +} + +static uint64_t ena_get_rx_queue_offloads(struct ena_adapter *adapter) +{ + RTE_SET_USED(adapter); + + return 0; +} + +static uint64_t ena_get_tx_queue_offloads(struct ena_adapter *adapter) +{ + RTE_SET_USED(adapter); + + return 0; +} + static int ena_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) { struct ena_adapter *adapter; struct ena_com_dev *ena_dev; - uint64_t rx_feat = 0, tx_feat = 0; ena_assert_msg(dev->data != NULL, "Uninitialized device\n"); ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n"); @@ -2030,42 +2139,26 @@ static int ena_infos_get(struct rte_eth_dev *dev, ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G; - /* Set Tx & Rx features available for device */ - if (adapter->offloads.tso4_supported) - tx_feat |= DEV_TX_OFFLOAD_TCP_TSO; - - if (adapter->offloads.tx_csum_supported) - tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM | - DEV_TX_OFFLOAD_UDP_CKSUM | - DEV_TX_OFFLOAD_TCP_CKSUM; - - if (adapter->offloads.rx_csum_supported) - rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM | - DEV_RX_OFFLOAD_UDP_CKSUM | - DEV_RX_OFFLOAD_TCP_CKSUM; - - rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME; - /* Inform framework about available features */ - dev_info->rx_offload_capa = rx_feat; - dev_info->rx_queue_offload_capa = rx_feat; - dev_info->tx_offload_capa = tx_feat; - dev_info->tx_queue_offload_capa = tx_feat; + dev_info->rx_offload_capa = ena_get_rx_port_offloads(adapter); + dev_info->tx_offload_capa = ena_get_tx_port_offloads(adapter); + dev_info->rx_queue_offload_capa = ena_get_rx_queue_offloads(adapter); + dev_info->tx_queue_offload_capa = ena_get_tx_queue_offloads(adapter); - dev_info->flow_type_rss_offloads = ETH_RSS_IP | ETH_RSS_TCP | - ETH_RSS_UDP; + dev_info->flow_type_rss_offloads = ENA_ALL_RSS_HF; + dev_info->hash_key_size = ENA_HASH_KEY_SIZE; dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN; - dev_info->max_rx_pktlen = adapter->max_mtu; + dev_info->max_rx_pktlen = adapter->max_mtu + RTE_ETHER_HDR_LEN + + RTE_ETHER_CRC_LEN; + dev_info->min_mtu = ENA_MIN_MTU; + dev_info->max_mtu = adapter->max_mtu; dev_info->max_mac_addrs = 1; dev_info->max_rx_queues = adapter->max_num_io_queues; dev_info->max_tx_queues = adapter->max_num_io_queues; dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE; - adapter->tx_supported_offloads = tx_feat; - adapter->rx_supported_offloads = rx_feat; - dev_info->rx_desc_lim.nb_max = adapter->max_rx_ring_size; dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC; dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, @@ -2080,6 +2173,9 @@ static int ena_infos_get(struct rte_eth_dev *dev, dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, adapter->max_tx_sgl_size); + dev_info->default_rxportconf.ring_size = ENA_DEFAULT_RING_SIZE; + dev_info->default_txportconf.ring_size = ENA_DEFAULT_RING_SIZE; + return 0; } @@ -2110,8 +2206,6 @@ static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring, len = ena_bufs[buf].len; req_id = ena_bufs[buf].req_id; - if (unlikely(validate_rx_req_id(rx_ring, req_id))) - return NULL; rx_info = &rx_ring->rx_buffer_info[req_id]; @@ -2135,10 +2229,6 @@ static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring, ++buf; len = ena_bufs[buf].len; req_id = ena_bufs[buf].req_id; - if (unlikely(validate_rx_req_id(rx_ring, req_id))) { - rte_mbuf_raw_free(mbuf_head); - return NULL; - } rx_info = &rx_ring->rx_buffer_info[req_id]; RTE_ASSERT(rx_info->mbuf != NULL); @@ -2196,20 +2286,24 @@ static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, { struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue); unsigned int free_queue_entries; - unsigned int refill_threshold; uint16_t next_to_clean = rx_ring->next_to_clean; uint16_t descs_in_use; struct rte_mbuf *mbuf; uint16_t completed; struct ena_com_rx_ctx ena_rx_ctx; int i, rc = 0; + bool fill_hash; +#ifdef RTE_ETHDEV_DEBUG_RX /* Check adapter state */ if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) { - PMD_DRV_LOG(ALERT, + PMD_RX_LOG(ALERT, "Trying to receive pkts while device is NOT running\n"); return 0; } +#endif + + fill_hash = rx_ring->offloads & DEV_RX_OFFLOAD_RSS_HASH; descs_in_use = rx_ring->ring_size - ena_com_free_q_entries(rx_ring->ena_com_io_sq) - 1; @@ -2225,11 +2319,19 @@ static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, rx_ring->ena_com_io_sq, &ena_rx_ctx); if (unlikely(rc)) { - PMD_DRV_LOG(ERR, "ena_com_rx_pkt error %d\n", rc); - rx_ring->adapter->reset_reason = - ENA_REGS_RESET_TOO_MANY_RX_DESCS; + PMD_RX_LOG(ERR, + "Failed to get the packet from the device, rc: %d\n", + rc); + if (rc == ENA_COM_NO_SPACE) { + ++rx_ring->rx_stats.bad_desc_num; + rx_ring->adapter->reset_reason = + ENA_REGS_RESET_TOO_MANY_RX_DESCS; + } else { + ++rx_ring->rx_stats.bad_req_id; + rx_ring->adapter->reset_reason = + ENA_REGS_RESET_INV_RX_REQ_ID; + } rx_ring->adapter->trigger_reset = true; - ++rx_ring->rx_stats.bad_desc_num; return 0; } @@ -2249,7 +2351,7 @@ static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, } /* fill mbuf attributes if any */ - ena_rx_mbuf_prepare(mbuf, &ena_rx_ctx); + ena_rx_mbuf_prepare(mbuf, &ena_rx_ctx, fill_hash); if (unlikely(mbuf->ol_flags & (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD))) { @@ -2257,8 +2359,6 @@ static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, ++rx_ring->rx_stats.bad_csum; } - mbuf->hash.rss = ena_rx_ctx.hash; - rx_pkts[completed] = mbuf; rx_ring->rx_stats.bytes += mbuf->pkt_len; } @@ -2267,12 +2367,9 @@ static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, rx_ring->next_to_clean = next_to_clean; free_queue_entries = ena_com_free_q_entries(rx_ring->ena_com_io_sq); - refill_threshold = - RTE_MIN(rx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER, - (unsigned int)ENA_REFILL_THRESH_PACKET); /* Burst refill to save doorbells, memory barriers, const interval */ - if (free_queue_entries > refill_threshold) { + if (free_queue_entries >= rx_ring->rx_free_thresh) { ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq); ena_populate_rx_queue(rx_ring, free_queue_entries); } @@ -2288,45 +2385,60 @@ eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint32_t i; struct rte_mbuf *m; struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue); + struct ena_adapter *adapter = tx_ring->adapter; struct rte_ipv4_hdr *ip_hdr; uint64_t ol_flags; + uint64_t l4_csum_flag; + uint64_t dev_offload_capa; uint16_t frag_field; + bool need_pseudo_csum; + dev_offload_capa = adapter->offloads.tx_offloads; for (i = 0; i != nb_pkts; i++) { m = tx_pkts[i]; ol_flags = m->ol_flags; - if (!(ol_flags & PKT_TX_IPV4)) + /* Check if any offload flag was set */ + if (ol_flags == 0) continue; - /* If there was not L2 header length specified, assume it is - * length of the ethernet header. - */ - if (unlikely(m->l2_len == 0)) - m->l2_len = sizeof(struct rte_ether_hdr); - - ip_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *, - m->l2_len); - frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset); - - if ((frag_field & RTE_IPV4_HDR_DF_FLAG) != 0) { - m->packet_type |= RTE_PTYPE_L4_NONFRAG; - - /* If IPv4 header has DF flag enabled and TSO support is - * disabled, partial chcecksum should not be calculated. - */ - if (!tx_ring->adapter->offloads.tso4_supported) - continue; - } - - if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 || - (ol_flags & PKT_TX_L4_MASK) == - PKT_TX_SCTP_CKSUM) { + l4_csum_flag = ol_flags & PKT_TX_L4_MASK; + /* SCTP checksum offload is not supported by the ENA. */ + if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) || + l4_csum_flag == PKT_TX_SCTP_CKSUM) { + PMD_TX_LOG(DEBUG, + "mbuf[%" PRIu32 "] has unsupported offloads flags set: 0x%" PRIu64 "\n", + i, ol_flags); rte_errno = ENOTSUP; return i; } #ifdef RTE_LIBRTE_ETHDEV_DEBUG + /* Check if requested offload is also enabled for the queue */ + if ((ol_flags & PKT_TX_IP_CKSUM && + !(tx_ring->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)) || + (l4_csum_flag == PKT_TX_TCP_CKSUM && + !(tx_ring->offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) || + (l4_csum_flag == PKT_TX_UDP_CKSUM && + !(tx_ring->offloads & DEV_TX_OFFLOAD_UDP_CKSUM))) { + PMD_TX_LOG(DEBUG, + "mbuf[%" PRIu32 "]: requested offloads: %" PRIu16 " are not enabled for the queue[%u]\n", + i, m->nb_segs, tx_ring->id); + rte_errno = EINVAL; + return i; + } + + /* The caller is obligated to set l2 and l3 len if any cksum + * offload is enabled. + */ + if (unlikely(ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK) && + (m->l2_len == 0 || m->l3_len == 0))) { + PMD_TX_LOG(DEBUG, + "mbuf[%" PRIu32 "]: l2_len or l3_len values are 0 while the offload was requested\n", + i); + rte_errno = EINVAL; + return i; + } ret = rte_validate_tx_offload(m); if (ret != 0) { rte_errno = -ret; @@ -2334,16 +2446,76 @@ eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, } #endif - /* In case we are supposed to TSO and have DF not set (DF=0) - * hardware must be provided with partial checksum, otherwise - * it will take care of necessary calculations. + /* Verify HW support for requested offloads and determine if + * pseudo header checksum is needed. */ + need_pseudo_csum = false; + if (ol_flags & PKT_TX_IPV4) { + if (ol_flags & PKT_TX_IP_CKSUM && + !(dev_offload_capa & ENA_L3_IPV4_CSUM)) { + rte_errno = ENOTSUP; + return i; + } - ret = rte_net_intel_cksum_flags_prepare(m, - ol_flags & ~PKT_TX_TCP_SEG); - if (ret != 0) { - rte_errno = -ret; - return i; + if (ol_flags & PKT_TX_TCP_SEG && + !(dev_offload_capa & ENA_IPV4_TSO)) { + rte_errno = ENOTSUP; + return i; + } + + /* Check HW capabilities and if pseudo csum is needed + * for L4 offloads. + */ + if (l4_csum_flag != PKT_TX_L4_NO_CKSUM && + !(dev_offload_capa & ENA_L4_IPV4_CSUM)) { + if (dev_offload_capa & + ENA_L4_IPV4_CSUM_PARTIAL) { + need_pseudo_csum = true; + } else { + rte_errno = ENOTSUP; + return i; + } + } + + /* Parse the DF flag */ + ip_hdr = rte_pktmbuf_mtod_offset(m, + struct rte_ipv4_hdr *, m->l2_len); + frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset); + if (frag_field & RTE_IPV4_HDR_DF_FLAG) { + m->packet_type |= RTE_PTYPE_L4_NONFRAG; + } else if (ol_flags & PKT_TX_TCP_SEG) { + /* In case we are supposed to TSO and have DF + * not set (DF=0) hardware must be provided with + * partial checksum. + */ + need_pseudo_csum = true; + } + } else if (ol_flags & PKT_TX_IPV6) { + /* There is no support for IPv6 TSO as for now. */ + if (ol_flags & PKT_TX_TCP_SEG) { + rte_errno = ENOTSUP; + return i; + } + + /* Check HW capabilities and if pseudo csum is needed */ + if (l4_csum_flag != PKT_TX_L4_NO_CKSUM && + !(dev_offload_capa & ENA_L4_IPV6_CSUM)) { + if (dev_offload_capa & + ENA_L4_IPV6_CSUM_PARTIAL) { + need_pseudo_csum = true; + } else { + rte_errno = ENOTSUP; + return i; + } + } + } + + if (need_pseudo_csum) { + ret = rte_net_intel_cksum_flags_prepare(m, ol_flags); + if (ret != 0) { + rte_errno = -ret; + return i; + } } } @@ -2362,6 +2534,20 @@ static void ena_update_hints(struct ena_adapter *adapter, adapter->ena_dev.mmio_read.reg_read_to = hints->mmio_read_timeout * 1000; + if (hints->missing_tx_completion_timeout) { + if (hints->missing_tx_completion_timeout == + ENA_HW_HINTS_NO_TIMEOUT) { + adapter->missing_tx_completion_to = + ENA_HW_HINTS_NO_TIMEOUT; + } else { + /* Convert from msecs to ticks */ + adapter->missing_tx_completion_to = rte_get_timer_hz() * + hints->missing_tx_completion_timeout / 1000; + adapter->tx_cleanup_stall_delay = + adapter->missing_tx_completion_to / 2; + } + } + if (hints->driver_watchdog_timeout) { if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT) adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT; @@ -2373,8 +2559,8 @@ static void ena_update_hints(struct ena_adapter *adapter, } } -static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring, - struct rte_mbuf *mbuf) +static int ena_check_space_and_linearize_mbuf(struct ena_ring *tx_ring, + struct rte_mbuf *mbuf) { struct ena_com_dev *ena_dev; int num_segments, header_len, rc; @@ -2384,23 +2570,43 @@ static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring, header_len = mbuf->data_len; if (likely(num_segments < tx_ring->sgl_size)) - return 0; + goto checkspace; if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV && (num_segments == tx_ring->sgl_size) && (header_len < tx_ring->tx_max_header_size)) - return 0; + goto checkspace; + /* Checking for space for 2 additional metadata descriptors due to + * possible header split and metadata descriptor. Linearization will + * be needed so we reduce the segments number from num_segments to 1 + */ + if (!ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq, 3)) { + PMD_TX_LOG(DEBUG, "Not enough space in the Tx queue\n"); + return ENA_COM_NO_MEM; + } ++tx_ring->tx_stats.linearize; rc = rte_pktmbuf_linearize(mbuf); if (unlikely(rc)) { - PMD_DRV_LOG(WARNING, "Mbuf linearize failed\n"); + PMD_TX_LOG(WARNING, "Mbuf linearize failed\n"); rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors); ++tx_ring->tx_stats.linearize_failed; return rc; } - return rc; + return 0; + +checkspace: + /* Checking for space for 2 additional metadata descriptors due to + * possible header split and metadata descriptor + */ + if (!ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq, + num_segments + 2)) { + PMD_TX_LOG(DEBUG, "Not enough space in the Tx queue\n"); + return ENA_COM_NO_MEM; + } + + return 0; } static void ena_tx_map_mbuf(struct ena_ring *tx_ring, @@ -2487,7 +2693,7 @@ static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf) int nb_hw_desc; int rc; - rc = ena_check_and_linearize_mbuf(tx_ring, mbuf); + rc = ena_check_space_and_linearize_mbuf(tx_ring, mbuf); if (unlikely(rc)) return rc; @@ -2511,21 +2717,28 @@ static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf) if (unlikely(ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq, &ena_tx_ctx))) { - PMD_DRV_LOG(DEBUG, - "llq tx max burst size of queue %d achieved, writing doorbell to send burst\n", + PMD_TX_LOG(DEBUG, + "LLQ Tx max burst size of queue %d achieved, writing doorbell to send burst\n", tx_ring->id); ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); + tx_ring->tx_stats.doorbells++; + tx_ring->pkts_without_db = false; } /* prepare the packet's descriptors to dma engine */ rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx, &nb_hw_desc); if (unlikely(rc)) { + PMD_DRV_LOG(ERR, "Failed to prepare Tx buffers, rc: %d\n", rc); ++tx_ring->tx_stats.prepare_ctx_err; + tx_ring->adapter->reset_reason = + ENA_REGS_RESET_DRIVER_INVALID_STATE; + tx_ring->adapter->trigger_reset = true; return rc; } tx_info->tx_descs = nb_hw_desc; + tx_info->timestamp = rte_get_timer_cycles(); tx_ring->tx_stats.cnt++; tx_ring->tx_stats.bytes += mbuf->pkt_len; @@ -2538,12 +2751,12 @@ static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf) static void ena_tx_cleanup(struct ena_ring *tx_ring) { - unsigned int cleanup_budget; unsigned int total_tx_descs = 0; + uint16_t cleanup_budget; uint16_t next_to_clean = tx_ring->next_to_clean; - cleanup_budget = RTE_MIN(tx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER, - (unsigned int)ENA_REFILL_THRESH_PACKET); + /* Attempt to release all Tx descriptors (ring_size - 1 -> size_mask) */ + cleanup_budget = tx_ring->size_mask; while (likely(total_tx_descs < cleanup_budget)) { struct rte_mbuf *mbuf; @@ -2558,6 +2771,7 @@ static void ena_tx_cleanup(struct ena_ring *tx_ring) /* Get Tx info & store how many descs were processed */ tx_info = &tx_ring->tx_buffer_info[req_id]; + tx_info->timestamp = 0; mbuf = tx_info->mbuf; rte_pktmbuf_free(mbuf); @@ -2578,43 +2792,48 @@ static void ena_tx_cleanup(struct ena_ring *tx_ring) ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs); ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq); } + + /* Notify completion handler that the cleanup was just called */ + tx_ring->last_cleanup_ticks = rte_get_timer_cycles(); } static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) { struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue); + int available_desc; uint16_t sent_idx = 0; +#ifdef RTE_ETHDEV_DEBUG_TX /* Check adapter state */ if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) { - PMD_DRV_LOG(ALERT, + PMD_TX_LOG(ALERT, "Trying to xmit pkts while device is NOT running\n"); return 0; } - - nb_pkts = RTE_MIN(ena_com_free_q_entries(tx_ring->ena_com_io_sq), - nb_pkts); +#endif for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) { if (ena_xmit_mbuf(tx_ring, tx_pkts[sent_idx])) break; - + tx_ring->pkts_without_db = true; rte_prefetch0(tx_pkts[ENA_IDX_ADD_MASKED(sent_idx, 4, tx_ring->size_mask)]); } - tx_ring->tx_stats.available_desc = - ena_com_free_q_entries(tx_ring->ena_com_io_sq); + available_desc = ena_com_free_q_entries(tx_ring->ena_com_io_sq); + tx_ring->tx_stats.available_desc = available_desc; /* If there are ready packets to be xmitted... */ - if (sent_idx > 0) { + if (likely(tx_ring->pkts_without_db)) { /* ...let HW do its best :-) */ ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); tx_ring->tx_stats.doorbells++; + tx_ring->pkts_without_db = false; } - ena_tx_cleanup(tx_ring); + if (available_desc < tx_ring->tx_free_thresh) + ena_tx_cleanup(tx_ring); tx_ring->tx_stats.available_desc = ena_com_free_q_entries(tx_ring->ena_com_io_sq); @@ -2634,10 +2853,10 @@ int ena_copy_eni_stats(struct ena_adapter *adapter) if (rc != 0) { if (rc == ENA_COM_UNSUPPORTED) { PMD_DRV_LOG(DEBUG, - "Retrieving ENI metrics is not supported.\n"); + "Retrieving ENI metrics is not supported\n"); } else { PMD_DRV_LOG(WARNING, - "Failed to get ENI metrics: %d\n", rc); + "Failed to get ENI metrics, rc: %d\n", rc); } return rc; } @@ -2665,7 +2884,7 @@ static int ena_xstats_get_names(struct rte_eth_dev *dev, struct rte_eth_xstat_name *xstats_names, unsigned int n) { - unsigned int xstats_count = ena_xstats_calc_num(dev); + unsigned int xstats_count = ena_xstats_calc_num(dev->data); unsigned int stat, i, count = 0; if (n < xstats_count || !xstats_names) @@ -2714,7 +2933,7 @@ static int ena_xstats_get(struct rte_eth_dev *dev, unsigned int n) { struct ena_adapter *adapter = dev->data->dev_private; - unsigned int xstats_count = ena_xstats_calc_num(dev); + unsigned int xstats_count = ena_xstats_calc_num(dev->data); unsigned int stat, i, count = 0; int stat_offset; void *stats_begin; @@ -2726,7 +2945,7 @@ static int ena_xstats_get(struct rte_eth_dev *dev, return 0; for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) { - stat_offset = ena_stats_rx_strings[stat].stat_offset; + stat_offset = ena_stats_global_strings[stat].stat_offset; stats_begin = &adapter->dev_stats; xstats[count].id = count; @@ -2857,7 +3076,7 @@ static int ena_process_bool_devarg(const char *key, } /* Now, assign it to the proper adapter field. */ - if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR)) + if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR) == 0) adapter->use_large_llq_hdr = bool_value; return 0; @@ -2868,6 +3087,7 @@ static int ena_parse_devargs(struct ena_adapter *adapter, { static const char * const allowed_args[] = { ENA_DEVARG_LARGE_LLQ_HDR, + NULL, }; struct rte_kvargs *kvlist; int rc; @@ -2890,6 +3110,100 @@ static int ena_parse_devargs(struct ena_adapter *adapter, return rc; } +static int ena_setup_rx_intr(struct rte_eth_dev *dev) +{ + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); + struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; + int rc; + uint16_t vectors_nb, i; + bool rx_intr_requested = dev->data->dev_conf.intr_conf.rxq; + + if (!rx_intr_requested) + return 0; + + if (!rte_intr_cap_multiple(intr_handle)) { + PMD_DRV_LOG(ERR, + "Rx interrupt requested, but it isn't supported by the PCI driver\n"); + return -ENOTSUP; + } + + /* Disable interrupt mapping before the configuration starts. */ + rte_intr_disable(intr_handle); + + /* Verify if there are enough vectors available. */ + vectors_nb = dev->data->nb_rx_queues; + if (vectors_nb > RTE_MAX_RXTX_INTR_VEC_ID) { + PMD_DRV_LOG(ERR, + "Too many Rx interrupts requested, maximum number: %d\n", + RTE_MAX_RXTX_INTR_VEC_ID); + rc = -ENOTSUP; + goto enable_intr; + } + + intr_handle->intr_vec = rte_zmalloc("intr_vec", + dev->data->nb_rx_queues * sizeof(*intr_handle->intr_vec), 0); + if (intr_handle->intr_vec == NULL) { + PMD_DRV_LOG(ERR, + "Failed to allocate interrupt vector for %d queues\n", + dev->data->nb_rx_queues); + rc = -ENOMEM; + goto enable_intr; + } + + rc = rte_intr_efd_enable(intr_handle, vectors_nb); + if (rc != 0) + goto free_intr_vec; + + if (!rte_intr_allow_others(intr_handle)) { + PMD_DRV_LOG(ERR, + "Not enough interrupts available to use both ENA Admin and Rx interrupts\n"); + goto disable_intr_efd; + } + + for (i = 0; i < vectors_nb; ++i) + intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + i; + + rte_intr_enable(intr_handle); + return 0; + +disable_intr_efd: + rte_intr_efd_disable(intr_handle); +free_intr_vec: + rte_free(intr_handle->intr_vec); + intr_handle->intr_vec = NULL; +enable_intr: + rte_intr_enable(intr_handle); + return rc; +} + +static void ena_rx_queue_intr_set(struct rte_eth_dev *dev, + uint16_t queue_id, + bool unmask) +{ + struct ena_adapter *adapter = dev->data->dev_private; + struct ena_ring *rxq = &adapter->rx_ring[queue_id]; + struct ena_eth_io_intr_reg intr_reg; + + ena_com_update_intr_reg(&intr_reg, 0, 0, unmask); + ena_com_unmask_intr(rxq->ena_com_io_cq, &intr_reg); +} + +static int ena_rx_queue_intr_enable(struct rte_eth_dev *dev, + uint16_t queue_id) +{ + ena_rx_queue_intr_set(dev, queue_id, true); + + return 0; +} + +static int ena_rx_queue_intr_disable(struct rte_eth_dev *dev, + uint16_t queue_id) +{ + ena_rx_queue_intr_set(dev, queue_id, false); + + return 0; +} + /********************************************************************* * PMD configuration *********************************************************************/ @@ -2917,20 +3231,15 @@ RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd); RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map); RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci"); RTE_PMD_REGISTER_PARAM_STRING(net_ena, ENA_DEVARG_LARGE_LLQ_HDR "=<0|1>"); -RTE_LOG_REGISTER(ena_logtype_init, pmd.net.ena.init, NOTICE); -RTE_LOG_REGISTER(ena_logtype_driver, pmd.net.ena.driver, NOTICE); -#ifdef RTE_LIBRTE_ENA_DEBUG_RX -RTE_LOG_REGISTER(ena_logtype_rx, pmd.net.ena.rx, NOTICE); -#endif -#ifdef RTE_LIBRTE_ENA_DEBUG_TX -RTE_LOG_REGISTER(ena_logtype_tx, pmd.net.ena.tx, NOTICE); +RTE_LOG_REGISTER_SUFFIX(ena_logtype_init, init, NOTICE); +RTE_LOG_REGISTER_SUFFIX(ena_logtype_driver, driver, NOTICE); +#ifdef RTE_ETHDEV_DEBUG_RX +RTE_LOG_REGISTER_SUFFIX(ena_logtype_rx, rx, DEBUG); #endif -#ifdef RTE_LIBRTE_ENA_DEBUG_TX_FREE -RTE_LOG_REGISTER(ena_logtype_tx_free, pmd.net.ena.tx_free, NOTICE); -#endif -#ifdef RTE_LIBRTE_ENA_COM_DEBUG -RTE_LOG_REGISTER(ena_logtype_com, pmd.net.ena.com, NOTICE); +#ifdef RTE_ETHDEV_DEBUG_TX +RTE_LOG_REGISTER_SUFFIX(ena_logtype_tx, tx, DEBUG); #endif +RTE_LOG_REGISTER_SUFFIX(ena_logtype_com, com, WARNING); /****************************************************************************** ******************************** AENQ Handlers ******************************* @@ -2938,14 +3247,12 @@ RTE_LOG_REGISTER(ena_logtype_com, pmd.net.ena.com, NOTICE); static void ena_update_on_link_change(void *adapter_data, struct ena_admin_aenq_entry *aenq_e) { - struct rte_eth_dev *eth_dev; - struct ena_adapter *adapter; + struct rte_eth_dev *eth_dev = adapter_data; + struct ena_adapter *adapter = eth_dev->data->dev_private; struct ena_admin_aenq_link_change_desc *aenq_link_desc; uint32_t status; - adapter = adapter_data; aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e; - eth_dev = adapter->rte_dev; status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc); adapter->link_status = status; @@ -2954,33 +3261,35 @@ static void ena_update_on_link_change(void *adapter_data, rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL); } -static void ena_notification(void *data, +static void ena_notification(void *adapter_data, struct ena_admin_aenq_entry *aenq_e) { - struct ena_adapter *adapter = data; + struct rte_eth_dev *eth_dev = adapter_data; + struct ena_adapter *adapter = eth_dev->data->dev_private; struct ena_admin_ena_hw_hints *hints; if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION) - PMD_DRV_LOG(WARNING, "Invalid group(%x) expected %x\n", + PMD_DRV_LOG(WARNING, "Invalid AENQ group: %x. Expected: %x\n", aenq_e->aenq_common_desc.group, ENA_ADMIN_NOTIFICATION); - switch (aenq_e->aenq_common_desc.syndrom) { + switch (aenq_e->aenq_common_desc.syndrome) { case ENA_ADMIN_UPDATE_HINTS: hints = (struct ena_admin_ena_hw_hints *) (&aenq_e->inline_data_w4); ena_update_hints(adapter, hints); break; default: - PMD_DRV_LOG(ERR, "Invalid aenq notification link state %d\n", - aenq_e->aenq_common_desc.syndrom); + PMD_DRV_LOG(ERR, "Invalid AENQ notification link state: %d\n", + aenq_e->aenq_common_desc.syndrome); } } static void ena_keep_alive(void *adapter_data, __rte_unused struct ena_admin_aenq_entry *aenq_e) { - struct ena_adapter *adapter = adapter_data; + struct rte_eth_dev *eth_dev = adapter_data; + struct ena_adapter *adapter = eth_dev->data->dev_private; struct ena_admin_aenq_keep_alive_desc *desc; uint64_t rx_drops; uint64_t tx_drops; @@ -3001,8 +3310,8 @@ static void ena_keep_alive(void *adapter_data, static void unimplemented_aenq_handler(__rte_unused void *data, __rte_unused struct ena_admin_aenq_entry *aenq_e) { - PMD_DRV_LOG(ERR, "Unknown event was received or event with " - "unimplemented handler\n"); + PMD_DRV_LOG(ERR, + "Unknown event was received or event with unimplemented handler\n"); } static struct ena_aenq_handlers aenq_handlers = {