X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Ffm10k%2Fbase%2Ffm10k_type.h;h=eedfe7408bf64ea048b813f3666c6cb6d0fd1fe2;hb=a5db0e800465ba192cddff3bd1bd7646290ee68d;hp=4ec18fb81355275a5bcd77aa9879568c54a60362;hpb=a177f52f90cdfe40cdcaca133ba00959b86929dc;p=dpdk.git diff --git a/drivers/net/fm10k/base/fm10k_type.h b/drivers/net/fm10k/base/fm10k_type.h index 4ec18fb813..eedfe7408b 100644 --- a/drivers/net/fm10k/base/fm10k_type.h +++ b/drivers/net/fm10k/base/fm10k_type.h @@ -50,6 +50,12 @@ struct fm10k_hw; #define FM10K_DEV_ID_SDI_FM10420_DA2 0x15D5 #endif /* ATWOOD_CHANNEL_HW */ +#ifndef LINUX_MACROS +#ifndef BIT +#define BIT(a) (1UL << (a)) +#endif +#endif /* LINUX_MACROS */ + #define FM10K_MAX_QUEUES 256 #define FM10K_MAX_QUEUES_PF 128 #define FM10K_MAX_QUEUES_POOL 16 @@ -115,15 +121,7 @@ struct fm10k_hw; #define FM10K_CTRL_BAR4_ALLOWED 0x00000004 #define FM10K_CTRL_EXT 0x0001 -#define FM10K_CTRL_EXT_NS_DIS 0x00000001 -#define FM10K_CTRL_EXT_RO_DIS 0x00000002 -#define FM10K_CTRL_EXT_SWITCH_LOOPBACK 0x00000004 -#define FM10K_EXVET 0x0002 -#define FM10K_EXVET_ETHERTYPE_MASK 0x000000FF -#define FM10K_EXVET_TAG_SIZE_SHIFT 16 -#define FM10K_EXVET_AFTER_VLAN 0x00040000 #define FM10K_GCR 0x0003 -#define FM10K_FACTPS 0x0004 #define FM10K_GCR_EXT 0x0005 /* Interrupt control registers */ @@ -190,7 +188,6 @@ struct fm10k_hw; #define FM10K_DGLORTDEC_INNERRSS_ENABLE 0x08000000 #define FM10K_TUNNEL_CFG 0x0040 #define FM10K_TUNNEL_CFG_NVGRE_SHIFT 16 -#define FM10K_TUNNEL_CFG_GENEVE 0x0041 #define FM10K_SWPRI_MAP(_n) ((_n) + 0x0050) #define FM10K_SWPRI_MAX 16 #define FM10K_RSSRK(_n, _m) (((_n) * 0x10) + (_m) + 0x0800) @@ -211,38 +208,24 @@ struct fm10k_hw; #define FM10K_TC_RATE_INTERVAL_4US_GEN1 0x00020000 #define FM10K_TC_RATE_INTERVAL_4US_GEN2 0x00040000 #define FM10K_TC_RATE_INTERVAL_4US_GEN3 0x00080000 -#define FM10K_TC_RATE_STATUS 0x20C0 -#define FM10K_PAUSE 0x20C2 /* DMA control registers */ #define FM10K_DMA_CTRL 0x20C3 #define FM10K_DMA_CTRL_TX_ENABLE 0x00000001 -#define FM10K_DMA_CTRL_TX_HOST_PENDING 0x00000002 -#define FM10K_DMA_CTRL_TX_DATA 0x00000004 #define FM10K_DMA_CTRL_TX_ACTIVE 0x00000008 #define FM10K_DMA_CTRL_RX_ENABLE 0x00000010 -#define FM10K_DMA_CTRL_RX_HOST_PENDING 0x00000020 -#define FM10K_DMA_CTRL_RX_DATA 0x00000040 #define FM10K_DMA_CTRL_RX_ACTIVE 0x00000080 #define FM10K_DMA_CTRL_RX_DESC_SIZE 0x00000100 #define FM10K_DMA_CTRL_MINMSS_SHIFT 9 #define FM10K_DMA_CTRL_MINMSS_64 0x00008000 -#define FM10K_DMA_CTRL_MAX_HOLD_TIME_SHIFT 23 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3 0x04800000 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2 0x04000000 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1 0x03800000 #define FM10K_DMA_CTRL_DATAPATH_RESET 0x20000000 -#define FM10K_DMA_CTRL_MAXNUMOFQ_MASK 0xC0000000 #define FM10K_DMA_CTRL_32_DESC 0x00000000 -#define FM10K_DMA_CTRL_64_DESC 0x40000000 -#define FM10K_DMA_CTRL_128_DESC 0x80000000 #define FM10K_DMA_CTRL2 0x20C4 -#define FM10K_DMA_CTRL2_TX_FRAME_SPACING_SHIFT 5 #define FM10K_DMA_CTRL2_SWITCH_READY 0x00002000 -#define FM10K_DMA_CTRL2_RX_DESC_READ_PRIO_SHIFT 14 -#define FM10K_DMA_CTRL2_TX_DESC_READ_PRIO_SHIFT 17 -#define FM10K_DMA_CTRL2_TX_DATA_READ_PRIO_SHIFT 20 /* TSO flags configuration * First packet contains all flags except for fin and psh @@ -255,7 +238,6 @@ struct fm10k_hw; #define FM10K_DTXTCPFLGH 0x20C6 #define FM10K_TPH_CTRL 0x20C7 -#define FM10K_TPH_CTRL_DISABLE_READ_HINT 0x00000080 #define FM10K_MRQC(_n) ((_n) + 0x2100) #define FM10K_MRQC_TCP_IPV4 0x00000001 #define FM10K_MRQC_IPV4 0x00000002 @@ -267,7 +249,6 @@ struct fm10k_hw; #define FM10K_TQMAP(_n) ((_n) + 0x2800) #define FM10K_TQMAP_TABLE_SIZE 2048 #define FM10K_RQMAP(_n) ((_n) + 0x3000) -#define FM10K_RQMAP_TABLE_SIZE 2048 /* Hardware Statistics */ #define FM10K_STATS_TIMEOUT 0x3800 @@ -280,16 +261,11 @@ struct fm10k_hw; #define FM10K_STATS_NODESC_DROP 0x3807 /* Timesync registers */ -#define FM10K_RRTIME_CFG 0x3808 -#define FM10K_RRTIME_LIMIT(_n) ((_n) + 0x380C) -#define FM10K_RRTIME_COUNT(_n) ((_n) + 0x3810) #define FM10K_SYSTIME 0x3814 -#define FM10K_SYSTIME0 0x3816 #define FM10K_SYSTIME_CFG 0x3818 #define FM10K_SYSTIME_CFG_STEP_MASK 0x0000000F /* PCIe state registers */ -#define FM10K_PFVFBME(_n) ((_n) + 0x381A) #define FM10K_PHYADDR 0x381C /* Rx ring registers */ @@ -298,8 +274,6 @@ struct fm10k_hw; #define FM10K_RDLEN(_n) ((0x40 * (_n)) + 0x4002) #define FM10K_TPH_RXCTRL(_n) ((0x40 * (_n)) + 0x4003) #define FM10K_TPH_RXCTRL_DESC_TPHEN 0x00000020 -#define FM10K_TPH_RXCTRL_HDR_TPHEN 0x00000040 -#define FM10K_TPH_RXCTRL_DATA_TPHEN 0x00000080 #define FM10K_TPH_RXCTRL_DESC_RROEN 0x00000200 #define FM10K_TPH_RXCTRL_DATA_WROEN 0x00002000 #define FM10K_TPH_RXCTRL_HDR_WROEN 0x00008000 @@ -313,27 +287,11 @@ struct fm10k_hw; #define FM10K_RXQCTL_ID_MASK (FM10K_RXQCTL_PF | FM10K_RXQCTL_VF) #define FM10K_RXDCTL(_n) ((0x40 * (_n)) + 0x4007) #define FM10K_RXDCTL_WRITE_BACK_MIN_DELAY 0x00000001 -#define FM10K_RXDCTL_WRITE_BACK_IMM 0x00000100 #define FM10K_RXDCTL_DROP_ON_EMPTY 0x00000200 #define FM10K_RXINT(_n) ((0x40 * (_n)) + 0x4008) #define FM10K_RXINT_TIMER_SHIFT 8 #define FM10K_SRRCTL(_n) ((0x40 * (_n)) + 0x4009) #define FM10K_SRRCTL_BSIZEPKT_SHIFT 8 /* shift _right_ */ -#define FM10K_SRRCTL_BSIZEHDR_SHIFT 2 /* shift _left_ */ -#define FM10K_SRRCTL_BSIZEHDR_MASK 0x00003F00 -#define FM10K_SRRCTL_DESCTYPE_HDR_SPLIT 0x00004000 -#define FM10K_SRRCTL_DESCTYPE_SIZE_SPLIT 0x00008000 -#define FM10K_SRRCTL_PSRTYPE_INNER_TCPHDR 0x00010000 -#define FM10K_SRRCTL_PSRTYPE_INNER_UDPHDR 0x00020000 -#define FM10K_SRRCTL_PSRTYPE_INNER_IPV4HDR 0x00040000 -#define FM10K_SRRCTL_PSRTYPE_INNER_IPV6HDR 0x00080000 -#define FM10K_SRRCTL_PSRTYPE_INNER_L2HDR 0x00100000 -#define FM10K_SRRCTL_PSRTYPE_ENCAPHDR 0x00200000 -#define FM10K_SRRCTL_PSRTYPE_TCPHDR 0x00400000 -#define FM10K_SRRCTL_PSRTYPE_UDPHDR 0x00800000 -#define FM10K_SRRCTL_PSRTYPE_IPV4HDR 0x01000000 -#define FM10K_SRRCTL_PSRTYPE_IPV6HDR 0x02000000 -#define FM10K_SRRCTL_PSRTYPE_L2HDR 0x04000000 #define FM10K_SRRCTL_LOOPBACK_SUPPRESS 0x40000000 #define FM10K_SRRCTL_BUFFER_CHAINING_EN 0x80000000 @@ -374,7 +332,6 @@ struct fm10k_hw; #define FM10K_TXDCTL(_n) ((0x40 * (_n)) + 0x8006) #define FM10K_TXDCTL_ENABLE 0x00004000 #define FM10K_TXDCTL_MAX_TIME_SHIFT 16 -#define FM10K_TXDCTL_PUSH_DESC 0x10000000 #define FM10K_TXQCTL(_n) ((0x40 * (_n)) + 0x8007) #define FM10K_TXQCTL_PF 0x0000003F #define FM10K_TXQCTL_VF 0x00000040 @@ -382,11 +339,9 @@ struct fm10k_hw; #define FM10K_TXQCTL_PC_SHIFT 7 #define FM10K_TXQCTL_PC_MASK 0x00000380 #define FM10K_TXQCTL_TC_SHIFT 10 -#define FM10K_TXQCTL_TC_MASK 0x0000FC00 #define FM10K_TXQCTL_VID_SHIFT 16 #define FM10K_TXQCTL_VID_MASK 0x0FFF0000 #define FM10K_TXQCTL_UNLIMITED_BW 0x10000000 -#define FM10K_TXQCTL_PUSHMODEDIS 0x20000000 #define FM10K_TXINT(_n) ((0x40 * (_n)) + 0x8008) #define FM10K_TXINT_TIMER_SHIFT 8 @@ -398,13 +353,7 @@ struct fm10k_hw; /* Tx Push registers */ #define FM10K_TQDLOC(_n) ((0x40 * (_n)) + 0x800C) #define FM10K_TQDLOC_BASE_32_DESC 0x08 -#define FM10K_TQDLOC_BASE_64_DESC 0x10 -#define FM10K_TQDLOC_BASE_128_DESC 0x20 #define FM10K_TQDLOC_SIZE_32_DESC 0x00050000 -#define FM10K_TQDLOC_SIZE_64_DESC 0x00060000 -#define FM10K_TQDLOC_SIZE_128_DESC 0x00070000 -#define FM10K_TQDLOC_SIZE_SHIFT 16 -#define FM10K_TX_DCACHE(_n, _m) ((0x400 * (_n)) + (0x4 * (_m)) + 0x40000) /* Tx GLORT registers */ #define FM10K_TX_SGLORT(_n) ((0x40 * (_n)) + 0x800D) @@ -412,50 +361,28 @@ struct fm10k_hw; #define FM10K_PFVTCTL_FTAG_DESC_ENABLE 0x00000001 /* Interrupt moderation and control registers */ -#define FM10K_PBACL(_n) ((_n) + 0x10000) #define FM10K_INT_MAP(_n) ((_n) + 0x10080) #define FM10K_INT_MAP_TIMER0 0x00000000 #define FM10K_INT_MAP_TIMER1 0x00000100 #define FM10K_INT_MAP_IMMEDIATE 0x00000200 #define FM10K_INT_MAP_DISABLE 0x00000300 -#define FM10K_MSIX_VECTOR_ADDR_LO(_n) ((0x4 * (_n)) + 0x11000) -#define FM10K_MSIX_VECTOR_ADDR_HI(_n) ((0x4 * (_n)) + 0x11001) -#define FM10K_MSIX_VECTOR_DATA(_n) ((0x4 * (_n)) + 0x11002) #define FM10K_MSIX_VECTOR_MASK(_n) ((0x4 * (_n)) + 0x11003) #define FM10K_INT_CTRL 0x12000 #define FM10K_INT_CTRL_ENABLEMODERATOR 0x00000400 #define FM10K_ITR(_n) ((_n) + 0x12400) #define FM10K_ITR_INTERVAL1_SHIFT 12 -#define FM10K_ITR_TIMER0_EXPIRED 0x01000000 -#define FM10K_ITR_TIMER1_EXPIRED 0x02000000 -#define FM10K_ITR_PENDING0 0x04000000 -#define FM10K_ITR_PENDING1 0x08000000 #define FM10K_ITR_PENDING2 0x10000000 #define FM10K_ITR_AUTOMASK 0x20000000 #define FM10K_ITR_MASK_SET 0x40000000 #define FM10K_ITR_MASK_CLEAR 0x80000000 #define FM10K_ITR2(_n) ((0x2 * (_n)) + 0x12800) -#define FM10K_ITR2_LP(_n) ((0x2 * (_n)) + 0x12801) #define FM10K_ITR_REG_COUNT 768 #define FM10K_ITR_REG_COUNT_PF 256 /* Switch manager interrupt registers */ #define FM10K_IP 0x13000 -#define FM10K_IP_HOT_RESET 0x00000001 -#define FM10K_IP_DEVICE_STATE_CHANGE 0x00000002 -#define FM10K_IP_MAILBOX 0x00000004 -#define FM10K_IP_VPD_REQUEST 0x00000008 -#define FM10K_IP_SRAMERROR 0x00000010 -#define FM10K_IP_PFLR 0x00000020 -#define FM10K_IP_DATAPATHRESET 0x00000040 -#define FM10K_IP_OUTOFRESET 0x00000080 #define FM10K_IP_NOTINRESET 0x00000100 -#define FM10K_IP_TIMEOUT 0x00000200 -#define FM10K_IP_VFLR 0x00000400 -#define FM10K_IM 0x13001 -#define FM10K_IB 0x13002 #define FM10K_SRAM_IP 0x13003 -#define FM10K_SRAM_IM 0x13004 /* VLAN registers */ #define FM10K_VLAN_TABLE(_n, _m) ((0x80 * (_n)) + (_m) + 0x14000) @@ -465,7 +392,8 @@ struct fm10k_hw; #define FM10K_VLAN_TABLE_VID_MAX 4096 #define FM10K_VLAN_TABLE_VSI_MAX 64 #define FM10K_VLAN_LENGTH_SHIFT 16 -#define FM10K_VLAN_CLEAR (1 << 15) +#define FM10K_VLAN_CLEAR BIT(15) +#define FM10K_VLAN_OVERRIDE FM10K_VLAN_CLEAR #define FM10K_VLAN_ALL \ ((FM10K_VLAN_TABLE_VID_MAX - 1) << FM10K_VLAN_LENGTH_SHIFT) @@ -493,12 +421,8 @@ struct fm10k_hw; #define FM10K_VFINT_MAP 0x00030 #define FM10K_VFSYSTIME 0x00040 #define FM10K_VFITR(_n) ((_n) + 0x00060) -#define FM10K_VFPBACL(_n) ((_n) + 0x00008) /* Registers contained in BAR 4 for Switch management */ -#define FM10K_SW_SYSTIME_CFG 0x0224C -#define FM10K_SW_SYSTIME_CFG_STEP_SHIFT 4 -#define FM10K_SW_SYSTIME_CFG_ADJUST_MASK 0xFF000000 #define FM10K_SW_SYSTIME_ADJUST 0x0224D #define FM10K_SW_SYSTIME_ADJUST_MASK 0x3FFFFFFF #define FM10K_SW_SYSTIME_ADJUST_DIR_POSITIVE 0x80000000 @@ -525,13 +449,13 @@ struct fm10k_hw; #endif enum fm10k_int_source { - fm10k_int_Mailbox = 0, - fm10k_int_PCIeFault = 1, - fm10k_int_SwitchUpDown = 2, - fm10k_int_SwitchEvent = 3, - fm10k_int_SRAM = 4, - fm10k_int_VFLR = 5, - fm10k_int_MaxHoldTime = 6, + fm10k_int_mailbox = 0, + fm10k_int_pcie_fault = 1, + fm10k_int_switch_up_down = 2, + fm10k_int_switch_event = 3, + fm10k_int_sram = 4, + fm10k_int_vflr = 5, + fm10k_int_max_hold_time = 6, fm10k_int_sources_max_pf }; @@ -673,7 +597,9 @@ struct fm10k_mac_ops { s32 (*stop_hw)(struct fm10k_hw *); s32 (*get_bus_info)(struct fm10k_hw *); s32 (*get_host_state)(struct fm10k_hw *, bool *); +#ifndef NO_IS_SLOT_APPROPRIATE_CHECK bool (*is_slot_appropriate)(struct fm10k_hw *); +#endif s32 (*update_vlan)(struct fm10k_hw *, u32, u8, bool); s32 (*read_mac_addr)(struct fm10k_hw *); s32 (*update_uc_addr)(struct fm10k_hw *, u16, const u8 *, @@ -688,7 +614,6 @@ struct fm10k_mac_ops { struct fm10k_dglort_cfg *); void (*set_dma_mask)(struct fm10k_hw *, u64); s32 (*get_fault)(struct fm10k_hw *, int, struct fm10k_fault *); - void (*request_lport_map)(struct fm10k_hw *); s32 (*adjust_systime)(struct fm10k_hw *, s32 ppb); s32 (*notify_offset)(struct fm10k_hw *, u64 offset); u64 (*read_systime)(struct fm10k_hw *); @@ -761,17 +686,18 @@ struct fm10k_vf_info { u8 vf_flags; /* flags indicating what modes * are supported for the port */ +#ifndef NO_FM10K_VF_TRUSTED_MODE + bool trusted; /* VF trust mode */ +#endif }; -#define FM10K_VF_FLAG_ALLMULTI_CAPABLE ((u8)1 << FM10K_XCAST_MODE_ALLMULTI) -#define FM10K_VF_FLAG_MULTI_CAPABLE ((u8)1 << FM10K_XCAST_MODE_MULTI) -#define FM10K_VF_FLAG_PROMISC_CAPABLE ((u8)1 << FM10K_XCAST_MODE_PROMISC) -#define FM10K_VF_FLAG_NONE_CAPABLE ((u8)1 << FM10K_XCAST_MODE_NONE) +#define FM10K_VF_FLAG_ALLMULTI_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_ALLMULTI)) +#define FM10K_VF_FLAG_MULTI_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_MULTI)) +#define FM10K_VF_FLAG_PROMISC_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_PROMISC)) +#define FM10K_VF_FLAG_NONE_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_NONE)) #define FM10K_VF_FLAG_CAPABLE(vf_info) ((vf_info)->vf_flags & (u8)0xF) #define FM10K_VF_FLAG_ENABLED(vf_info) ((vf_info)->vf_flags >> 4) #define FM10K_VF_FLAG_SET_MODE(mode) ((u8)0x10 << (mode)) -#define FM10K_VF_FLAG_ENABLED_MODE_SHIFT 4 -#define FM10K_VF_FLAG_SET_MODE_MASK ((u8)0xF0) #define FM10K_VF_FLAG_SET_MODE_NONE \ FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_NONE) #define FM10K_VF_FLAG_MULTI_ENABLED \ @@ -817,7 +743,7 @@ struct fm10k_hw { u16 subsystem_vendor_id; u8 revision_id; u32 flags; -#define FM10K_HW_FLAG_CLOCK_OWNER (u32)(1 << 0) +#define FM10K_HW_FLAG_CLOCK_OWNER BIT(0) }; /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ @@ -842,13 +768,11 @@ struct fm10k_tx_desc_cache { #define FM10K_TXD_FLAG_INT 0x01 #define FM10K_TXD_FLAG_TIME 0x02 #define FM10K_TXD_FLAG_CSUM 0x04 -#define FM10K_TXD_FLAG_CSUM2 0x08 #define FM10K_TXD_FLAG_FTAG 0x10 #define FM10K_TXD_FLAG_RS 0x20 #define FM10K_TXD_FLAG_LAST 0x40 #define FM10K_TXD_FLAG_DONE 0x80 -#define FM10K_TXD_VLAN_PRI_SHIFT 12 /* These macros are meant to enable optimal placement of the RS and INT * bits. It will point us to the last descriptor in the cache for either the @@ -857,8 +781,6 @@ struct fm10k_tx_desc_cache { * in the FIFO to prevent an unnecessary write. */ #define FM10K_TXD_WB_FIFO_SIZE 4 -#define FM10K_TXD_WB_IDX(idx) \ - (((idx) - 1) | (FM10K_TXD_WB_FIFO_SIZE - 1)) /* Receive Descriptor - 32B */ union fm10k_rx_desc { @@ -904,12 +826,7 @@ enum fm10k_rdesc_rss_type { }; #define FM10K_RXD_PKTTYPE_MASK 0x03F0 -#define FM10K_RXD_PKTTYPE_MASK_L3 0x0070 -#define FM10K_RXD_PKTTYPE_MASK_L4 0x0380 #define FM10K_RXD_PKTTYPE_SHIFT 4 -#define FM10K_RXD_PKTTYPE_INNER_MASK_L3 0x1C00 -#define FM10K_RXD_PKTTYPE_INNER_MASK_L4 0xE000 -#define FM10K_RXD_PKTTYPE_INNER_SHIFT 10 enum fm10k_rdesc_pkt_type { /* L3 type */ FM10K_PKTTYPE_OTHER = 0x00, @@ -934,20 +851,12 @@ enum fm10k_rxdesc_xc { FM10K_XC_BROADCAST = 0x6 }; -#define FM10K_RXD_HDR_INFO_LEN_SHIFT 5 -#define FM10K_RXD_HDR_INFO_SPH 0x8000 #define FM10K_RXD_STATUS_DD 0x0001 /* Descriptor done */ #define FM10K_RXD_STATUS_EOP 0x0002 /* End of packet */ -#define FM10K_RXD_STATUS_VEXT 0x0004 /* A VLAN tag is present */ #define FM10K_RXD_STATUS_IPCS 0x0008 /* Indicates IPv4 csum */ #define FM10K_RXD_STATUS_L4CS 0x0010 /* Indicates an L4 csum */ -#define FM10K_RXD_STATUS_IPCS2 0x0020 /* Inner header IPv4 csum */ #define FM10K_RXD_STATUS_L4CS2 0x0040 /* Inner header L4 csum */ -#define FM10K_RXD_STATUS_IPFRAG_MASK 0x0180 /* Fragment mask */ -#define FM10K_RXD_STATUS_IPFRAG_CSUM 0x0100 /* Fragment w/ CSUM field */ -#define FM10K_RXD_STATUS_VEXT2 0x0200 /* A custom tag is present */ -#define FM10K_RXD_STATUS_HBO 0x0400 /* header buffer overrun */ #define FM10K_RXD_STATUS_L4E2 0x0800 /* Inner header L4 csum err */ #define FM10K_RXD_STATUS_IPE2 0x1000 /* Inner header IPv4 csum err */ #define FM10K_RXD_STATUS_RXE 0x2000 /* Generic Rx error */ @@ -960,8 +869,6 @@ enum fm10k_rxdesc_xc { #define FM10K_RXD_ERR_SWITCH_READY 0x0008 /* Link transition mid-packet */ #define FM10K_RXD_ERR_TOO_BIG 0x0010 /* Pkt too big for single buf */ -#define FM10K_RXD_VLAN_ID_MASK 0x0FFF -#define FM10K_RXD_VLAN_PRI_SHIFT FM10K_TXD_VLAN_PRI_SHIFT struct fm10k_ftag { __be16 swpri_type_user;