X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fhns3%2Fhns3_cmd.c;h=0299072efbdd1ecb5bee589bc2f7c4cd716adccc;hb=3e66aafe5412a47a9e10a93b0228efe1bea3083a;hp=853b9fd6fe0f1cac95a25d995c5cd20a18c05150;hpb=737f30e1c3ab24c46b7a56b59f360517f85f0196;p=dpdk.git

diff --git a/drivers/net/hns3/hns3_cmd.c b/drivers/net/hns3/hns3_cmd.c
index 853b9fd6fe..0299072efb 100644
--- a/drivers/net/hns3/hns3_cmd.c
+++ b/drivers/net/hns3/hns3_cmd.c
@@ -22,6 +22,7 @@
 
 #include "hns3_ethdev.h"
 #include "hns3_regs.h"
+#include "hns3_intr.h"
 #include "hns3_logs.h"
 
 #define hns3_is_csq(ring) ((ring)->flag & HNS3_TYPE_CSQ)
@@ -216,7 +217,11 @@ hns3_cmd_csq_clean(struct hns3_hw *hw)
 	if (!is_valid_csq_clean_head(csq, head)) {
 		hns3_err(hw, "wrong cmd head (%u, %u-%u)", head,
 			    csq->next_to_use, csq->next_to_clean);
-		rte_atomic16_set(&hw->reset.disable_cmd, 1);
+		if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
+			rte_atomic16_set(&hw->reset.disable_cmd, 1);
+			hns3_schedule_delayed_reset(HNS3_DEV_HW_TO_ADAPTER(hw));
+		}
+
 		return -EIO;
 	}
 
@@ -284,7 +289,7 @@ hns3_cmd_convert_err_code(uint16_t desc_ret)
 	case HNS3_CMD_INVALID:
 		return -EBADR;
 	default:
-		return -EIO;
+		return -EREMOTEIO;
 	}
 }
 
@@ -317,6 +322,7 @@ hns3_cmd_get_hardware_reply(struct hns3_hw *hw,
 
 static int hns3_cmd_poll_reply(struct hns3_hw *hw)
 {
+	struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 	uint32_t timeout = 0;
 
 	do {
@@ -329,20 +335,37 @@ static int hns3_cmd_poll_reply(struct hns3_hw *hw)
 			return -EBUSY;
 		}
 
+		if (is_reset_pending(hns)) {
+			hns3_err(hw, "Don't wait for reply because of reset pending");
+			return -EIO;
+		}
+
 		rte_delay_us(1);
 		timeout++;
 	} while (timeout < hw->cmq.tx_timeout);
 	hns3_err(hw, "Wait for reply timeout");
-	return -EBADE;
+	return -ETIME;
 }
 
 /*
  * hns3_cmd_send - send command to command queue
- * @hw: pointer to the hw struct
- * @desc: prefilled descriptor for describing the command
- * @num : the number of descriptors to be sent
  *
- * This is the main send command for command queue, it
+ * @param hw
+ *   pointer to the hw struct
+ * @param desc
+ *   prefilled descriptor for describing the command
+ * @param num
+ *   the number of descriptors to be sent
+ * @return
+ *   - -EBUSY if detect device is in resetting
+ *   - -EIO   if detect cmd csq corrupted (due to reset) or
+ *            there is reset pending
+ *   - -ENOMEM/-ETIME/...(Non-Zero) if other error case
+ *   - Zero   if operation completed successfully
+ *
+ * Note -BUSY/-EIO only used in reset case
+ *
+ * Note this is the main send command for command queue, it
  * sends the queue, cleans the queue, etc
  */
 int
@@ -403,8 +426,29 @@ hns3_cmd_send(struct hns3_hw *hw, struct hns3_cmd_desc *desc, int num)
 	return retval;
 }
 
+static void hns3_parse_capability(struct hns3_hw *hw,
+				  struct hns3_query_version_cmd *cmd)
+{
+	uint32_t caps = rte_le_to_cpu_32(cmd->caps[0]);
+
+	if (hns3_get_bit(caps, HNS3_CAPS_UDP_GSO_B))
+		hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_UDP_GSO_B, 1);
+	if (hns3_get_bit(caps, HNS3_CAPS_ADQ_B))
+		hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_ADQ_B, 1);
+	if (hns3_get_bit(caps, HNS3_CAPS_PTP_B))
+		hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_PTP_B, 1);
+	if (hns3_get_bit(caps, HNS3_CAPS_TX_PUSH_B))
+		hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_TX_PUSH_B, 1);
+	if (hns3_get_bit(caps, HNS3_CAPS_PHY_IMP_B))
+		hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_COPPER_B, 1);
+	if (hns3_get_bit(caps, HNS3_CAPS_TQP_TXRX_INDEP_B))
+		hns3_set_bit(hw->capability, HNS3_CAPS_TQP_TXRX_INDEP_B, 1);
+	if (hns3_get_bit(caps, HNS3_CAPS_STASH_B))
+		hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_STASH_B, 1);
+}
+
 static enum hns3_cmd_status
-hns3_cmd_query_firmware_version(struct hns3_hw *hw, uint32_t *version)
+hns3_cmd_query_firmware_version_and_capability(struct hns3_hw *hw)
 {
 	struct hns3_query_version_cmd *resp;
 	struct hns3_cmd_desc desc;
@@ -415,10 +459,13 @@ hns3_cmd_query_firmware_version(struct hns3_hw *hw, uint32_t *version)
 
 	/* Initialize the cmd function */
 	ret = hns3_cmd_send(hw, &desc, 1);
-	if (ret == 0)
-		*version = rte_le_to_cpu_32(resp->firmware);
+	if (ret)
+		return ret;
 
-	return ret;
+	hw->fw_version = rte_le_to_cpu_32(resp->firmware);
+	hns3_parse_capability(hw, resp);
+
+	return 0;
 }
 
 int
@@ -467,6 +514,7 @@ err_crq:
 int
 hns3_cmd_init(struct hns3_hw *hw)
 {
+	uint32_t version;
 	int ret;
 
 	rte_spinlock_lock(&hw->cmq.csq.lock);
@@ -476,25 +524,46 @@ hns3_cmd_init(struct hns3_hw *hw)
 	hw->cmq.csq.next_to_use = 0;
 	hw->cmq.crq.next_to_clean = 0;
 	hw->cmq.crq.next_to_use = 0;
+	hw->mbx_resp.head = 0;
+	hw->mbx_resp.tail = 0;
+	hw->mbx_resp.lost = 0;
 	hns3_cmd_init_regs(hw);
 
 	rte_spinlock_unlock(&hw->cmq.crq.lock);
 	rte_spinlock_unlock(&hw->cmq.csq.lock);
 
+	/*
+	 * Check if there is new reset pending, because the higher level
+	 * reset may happen when lower level reset is being processed.
+	 */
+	if (is_reset_pending(HNS3_DEV_HW_TO_ADAPTER(hw))) {
+		PMD_INIT_LOG(ERR, "New reset pending, keep disable cmd");
+		ret = -EBUSY;
+		goto err_cmd_init;
+	}
 	rte_atomic16_clear(&hw->reset.disable_cmd);
 
-	ret = hns3_cmd_query_firmware_version(hw, &hw->fw_version);
+	ret = hns3_cmd_query_firmware_version_and_capability(hw);
 	if (ret) {
 		PMD_INIT_LOG(ERR, "firmware version query failed %d", ret);
 		goto err_cmd_init;
 	}
 
-	PMD_INIT_LOG(INFO, "The firmware version is %08x", hw->fw_version);
+	version = hw->fw_version;
+	PMD_INIT_LOG(INFO, "The firmware version is %lu.%lu.%lu.%lu",
+		     hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
+				    HNS3_FW_VERSION_BYTE3_S),
+		     hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
+				    HNS3_FW_VERSION_BYTE2_S),
+		     hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
+				    HNS3_FW_VERSION_BYTE1_S),
+		     hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
+				    HNS3_FW_VERSION_BYTE0_S));
 
 	return 0;
 
 err_cmd_init:
-	hns3_cmd_uninit(hw);
+	rte_atomic16_set(&hw->reset.disable_cmd, 1);
 	return ret;
 }