X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fhns3%2Fhns3_cmd.c;h=6a1e634684bb5ca0c11841080fed378c5bf7bf9b;hb=70d2f42110576c670a67abd35a4bb6a2d0b00980;hp=5beb3d97546c0968d5a01215395cc367bed94589;hpb=1f9d940d6d0b292937af7c1b7842ea68702f8e17;p=dpdk.git

diff --git a/drivers/net/hns3/hns3_cmd.c b/drivers/net/hns3/hns3_cmd.c
index 5beb3d9754..6a1e634684 100644
--- a/drivers/net/hns3/hns3_cmd.c
+++ b/drivers/net/hns3/hns3_cmd.c
@@ -44,10 +44,12 @@ static int
 hns3_allocate_dma_mem(struct hns3_hw *hw, struct hns3_cmq_ring *ring,
 		      uint64_t size, uint32_t alignment)
 {
+	static uint64_t hns3_dma_memzone_id;
 	const struct rte_memzone *mz = NULL;
 	char z_name[RTE_MEMZONE_NAMESIZE];
 
-	snprintf(z_name, sizeof(z_name), "hns3_dma_%" PRIu64, rte_rand());
+	snprintf(z_name, sizeof(z_name), "hns3_dma_%" PRIu64,
+		__atomic_fetch_add(&hns3_dma_memzone_id, 1, __ATOMIC_RELAXED));
 	mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
 					 RTE_MEMZONE_IOVA_CONTIG, alignment,
 					 RTE_PGSIZE_2M);
@@ -241,7 +243,7 @@ hns3_is_special_opcode(uint16_t opcode)
 				  HNS3_OPC_QUERY_ALL_ERR_INFO,};
 	uint32_t i;
 
-	for (i = 0; i < ARRAY_SIZE(spec_opcode); i++)
+	for (i = 0; i < RTE_DIM(spec_opcode); i++)
 		if (spec_opcode[i] == opcode)
 			return true;
 
@@ -272,7 +274,7 @@ hns3_cmd_convert_err_code(uint16_t desc_ret)
 
 	uint32_t i;
 
-	for (i = 0; i < ARRAY_SIZE(hns3_cmdq_status); i++)
+	for (i = 0; i < RTE_DIM(hns3_cmdq_status); i++)
 		if (hns3_cmdq_status[i].imp_errcode == desc_ret)
 			return hns3_cmdq_status[i].linux_errcode;
 
@@ -419,12 +421,8 @@ hns3_get_caps_name(uint32_t caps_id)
 		enum HNS3_CAPS_BITS caps;
 		const char *name;
 	} dev_caps[] = {
-		{ HNS3_CAPS_UDP_GSO_B,         "udp_gso"         },
-		{ HNS3_CAPS_ATR_B,             "atr"             },
 		{ HNS3_CAPS_FD_QUEUE_REGION_B, "fd_queue_region" },
 		{ HNS3_CAPS_PTP_B,             "ptp"             },
-		{ HNS3_CAPS_INT_QL_B,          "int_ql"          },
-		{ HNS3_CAPS_SIMPLE_BD_B,       "simple_bd"       },
 		{ HNS3_CAPS_TX_PUSH_B,         "tx_push"         },
 		{ HNS3_CAPS_PHY_IMP_B,         "phy_imp"         },
 		{ HNS3_CAPS_TQP_TXRX_INDEP_B,  "tqp_txrx_indep"  },
@@ -432,9 +430,8 @@ hns3_get_caps_name(uint32_t caps_id)
 		{ HNS3_CAPS_STASH_B,           "stash"           },
 		{ HNS3_CAPS_UDP_TUNNEL_CSUM_B, "udp_tunnel_csum" },
 		{ HNS3_CAPS_RAS_IMP_B,         "ras_imp"         },
-		{ HNS3_CAPS_FEC_B,             "fec"             },
-		{ HNS3_CAPS_PAUSE_B,           "pause"           },
-		{ HNS3_CAPS_RXD_ADV_LAYOUT_B,  "rxd_adv_layout"  }
+		{ HNS3_CAPS_RXD_ADV_LAYOUT_B,  "rxd_adv_layout"  },
+		{ HNS3_CAPS_TM_B,              "tm_capability"   }
 	};
 	uint32_t i;
 
@@ -480,8 +477,6 @@ hns3_parse_capability(struct hns3_hw *hw,
 {
 	uint32_t caps = rte_le_to_cpu_32(cmd->caps[0]);
 
-	if (hns3_get_bit(caps, HNS3_CAPS_UDP_GSO_B))
-		hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_UDP_GSO_B, 1);
 	if (hns3_get_bit(caps, HNS3_CAPS_FD_QUEUE_REGION_B))
 		hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B,
 			     1);
@@ -514,6 +509,8 @@ hns3_parse_capability(struct hns3_hw *hw,
 				HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B, 1);
 	if (hns3_get_bit(caps, HNS3_CAPS_RAS_IMP_B))
 		hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_RAS_IMP_B, 1);
+	if (hns3_get_bit(caps, HNS3_CAPS_TM_B))
+		hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_TM_B, 1);
 }
 
 static uint32_t