X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fhns3%2Fhns3_cmd.h;h=30aca82d320ac937b904f83577f9f34790964764;hb=6a11a1eac0b6dcd52580eef99cf6f09e3361cc3b;hp=e40293b309279b0bbd0f7c31d0710be2bde2794a;hpb=e5d179078b611035395317c80a9285c8a2de18a2;p=dpdk.git diff --git a/drivers/net/hns3/hns3_cmd.h b/drivers/net/hns3/hns3_cmd.h index e40293b309..30aca82d32 100644 --- a/drivers/net/hns3/hns3_cmd.h +++ b/drivers/net/hns3/hns3_cmd.h @@ -8,6 +8,7 @@ #include #define HNS3_CMDQ_TX_TIMEOUT 30000 +#define HNS3_CMDQ_CLEAR_WAIT_TIME 200 #define HNS3_CMDQ_RX_INVLD_B 0 #define HNS3_CMDQ_RX_OUTVLD_B 1 #define HNS3_CMD_DESC_ALIGNMENT 4096 @@ -52,6 +53,7 @@ enum hns3_cmd_return_status { HNS3_CMD_HILINK_ERR = 9, HNS3_CMD_QUEUE_ILLEGAL = 10, HNS3_CMD_INVALID = 11, + HNS3_CMD_ROH_CHECK_FAIL = 12 }; enum hns3_cmd_status { @@ -93,14 +95,32 @@ enum hns3_opcode_type { HNS3_OPC_QUERY_REG_NUM = 0x0040, HNS3_OPC_QUERY_32_BIT_REG = 0x0041, HNS3_OPC_QUERY_64_BIT_REG = 0x0042, + HNS3_OPC_DFX_BD_NUM = 0x0043, + HNS3_OPC_DFX_BIOS_COMMON_REG = 0x0044, + HNS3_OPC_DFX_SSU_REG_0 = 0x0045, + HNS3_OPC_DFX_SSU_REG_1 = 0x0046, + HNS3_OPC_DFX_IGU_EGU_REG = 0x0047, + HNS3_OPC_DFX_RPU_REG_0 = 0x0048, + HNS3_OPC_DFX_RPU_REG_1 = 0x0049, + HNS3_OPC_DFX_NCSI_REG = 0x004A, + HNS3_OPC_DFX_RTC_REG = 0x004B, + HNS3_OPC_DFX_PPP_REG = 0x004C, + HNS3_OPC_DFX_RCB_REG = 0x004D, + HNS3_OPC_DFX_TQP_REG = 0x004E, + HNS3_OPC_DFX_SSU_REG_2 = 0x004F, HNS3_OPC_QUERY_DEV_SPECS = 0x0050, + HNS3_OPC_SSU_DROP_REG = 0x0065, + /* MAC command */ HNS3_OPC_CONFIG_MAC_MODE = 0x0301, HNS3_OPC_QUERY_LINK_STATUS = 0x0307, HNS3_OPC_CONFIG_MAX_FRM_SIZE = 0x0308, HNS3_OPC_CONFIG_SPEED_DUP = 0x0309, + HNS3_OPC_QUERY_MAC_TNL_INT = 0x0310, + HNS3_OPC_MAC_TNL_INT_EN = 0x0311, + HNS3_OPC_CLEAR_MAC_TNL_INT = 0x0312, HNS3_OPC_CONFIG_FEC_MODE = 0x031A, /* PFC/Pause commands */ @@ -205,7 +225,14 @@ enum hns3_opcode_type { /* Clear hardware state command */ HNS3_OPC_CLEAR_HW_STATE = 0x700B, + /* Firmware stats command */ + HNS3_OPC_FIRMWARE_COMPAT_CFG = 0x701A, + /* Firmware control phy command */ + HNS3_OPC_PHY_PARAM_CFG = 0x7025, + /* SFP command */ + HNS3_OPC_GET_SFP_EEPROM = 0x7100, + HNS3_OPC_GET_SFP_EXIST = 0x7101, HNS3_OPC_SFP_GET_SPEED = 0x7104, /* Interrupts commands */ @@ -290,12 +317,22 @@ enum HNS3_CAPS_BITS { HNS3_CAPS_TQP_TXRX_INDEP_B, HNS3_CAPS_HW_PAD_B, HNS3_CAPS_STASH_B, + HNS3_CAPS_UDP_TUNNEL_CSUM_B, + HNS3_CAPS_RAS_IMP_B, + HNS3_CAPS_FEC_B, + HNS3_CAPS_PAUSE_B, + HNS3_CAPS_RXD_ADV_LAYOUT_B, +}; + +enum HNS3_API_CAP_BITS { + HNS3_API_CAP_FLEX_RSS_TBL_B, }; + #define HNS3_QUERY_CAP_LENGTH 3 struct hns3_query_version_cmd { uint32_t firmware; uint32_t hardware; - uint32_t rsv; + uint32_t api_caps; uint32_t caps[HNS3_QUERY_CAP_LENGTH]; /* capabilities of device */ }; @@ -632,6 +669,48 @@ enum hns3_promisc_type { HNS3_BROADCAST = 3, }; +#define HNS3_LINK_EVENT_REPORT_EN_B 0 +#define HNS3_NCSI_ERROR_REPORT_EN_B 1 +#define HNS3_FIRMWARE_PHY_DRIVER_EN_B 2 +struct hns3_firmware_compat_cmd { + uint32_t compat; + uint8_t rsv[20]; +}; + +/* Bitmap flags in supported, advertising and lp_advertising */ +#define HNS3_PHY_LINK_SPEED_10M_HD_BIT BIT(0) +#define HNS3_PHY_LINK_SPEED_10M_BIT BIT(1) +#define HNS3_PHY_LINK_SPEED_100M_HD_BIT BIT(2) +#define HNS3_PHY_LINK_SPEED_100M_BIT BIT(3) +#define HNS3_PHY_LINK_MODE_AUTONEG_BIT BIT(6) +#define HNS3_PHY_LINK_MODE_PAUSE_BIT BIT(13) +#define HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT BIT(14) + +#define HNS3_PHY_PARAM_CFG_BD_NUM 2 +struct hns3_phy_params_bd0_cmd { + uint32_t speed; +#define HNS3_PHY_DUPLEX_CFG_B 0 + uint8_t duplex; +#define HNS3_PHY_AUTONEG_CFG_B 0 + uint8_t autoneg; + uint8_t eth_tp_mdix; + uint8_t eth_tp_mdix_ctrl; + uint8_t port; + uint8_t transceiver; + uint8_t phy_address; + uint8_t rsv; + uint32_t supported; + uint32_t advertising; + uint32_t lp_advertising; +}; + +struct hns3_phy_params_bd1_cmd { + uint8_t master_slave_cfg; + uint8_t master_slave_state; + uint8_t rsv1[2]; + uint32_t rsv2[5]; +}; + #define HNS3_MAC_TX_EN_B 6 #define HNS3_MAC_RX_EN_B 7 #define HNS3_MAC_PAD_TX_B 11 @@ -697,6 +776,20 @@ struct hns3_config_auto_neg_cmd { #define HNS3_MAC_FEC_BASER 1 #define HNS3_MAC_FEC_RS 2 +#define HNS3_SFP_INFO_BD0_LEN 20UL +#define HNS3_SFP_INFO_BDX_LEN 24UL + +struct hns3_sfp_info_bd0_cmd { + uint16_t offset; + uint16_t read_len; + uint8_t data[HNS3_SFP_INFO_BD0_LEN]; +}; + +struct hns3_sfp_type { + uint8_t type; + uint8_t ext_type; +}; + struct hns3_sfp_speed_cmd { uint32_t sfp_speed; uint8_t query_type; /* 0: sfp speed, 1: active fec */ @@ -775,12 +868,16 @@ enum hns3_int_gl_idx { #define HNS3_TQP_ID_M GENMASK(12, 2) #define HNS3_INT_GL_IDX_S 13 #define HNS3_INT_GL_IDX_M GENMASK(14, 13) +#define HNS3_TQP_INT_ID_L_S 0 +#define HNS3_TQP_INT_ID_L_M GENMASK(7, 0) +#define HNS3_TQP_INT_ID_H_S 8 +#define HNS3_TQP_INT_ID_H_M GENMASK(15, 8) struct hns3_ctrl_vector_chain_cmd { - uint8_t int_vector_id; + uint8_t int_vector_id; /* the low order of the interrupt id */ uint8_t int_cause_num; uint16_t tqp_type_and_id[HNS3_VECTOR_ELEMENTS_PER_CMD]; uint8_t vfid; - uint8_t rsv; + uint8_t int_vector_id_h; /* the high order of the interrupt id */ }; struct hns3_config_max_frm_size_cmd { @@ -836,10 +933,16 @@ struct hns3_reset_tqp_queue_cmd { #define HNS3_CFG_RESET_MAC_B 3 #define HNS3_CFG_RESET_FUNC_B 7 +#define HNS3_CFG_RESET_RCB_B 1 struct hns3_reset_cmd { uint8_t mac_func_reset; uint8_t fun_reset_vfid; - uint8_t rsv[22]; + uint8_t fun_reset_rcb; + uint8_t rsv1; + uint16_t fun_reset_rcb_vqid_start; + uint16_t fun_reset_rcb_vqid_num; + uint8_t fun_reset_rcb_return_status; + uint8_t rsv2[15]; }; #define HNS3_QUERY_DEV_SPECS_BD_NUM 4 @@ -855,6 +958,24 @@ struct hns3_dev_specs_0_cmd { uint32_t max_tm_rate; }; +struct hns3_query_rpu_cmd { + uint32_t tc_queue_num; + uint32_t rsv1[2]; + uint32_t rpu_rx_pkt_drop_cnt; + uint32_t rsv2[2]; +}; + +#define HNS3_OPC_SSU_DROP_REG_NUM 2 + +struct hns3_query_ssu_cmd { + uint8_t rxtx; + uint8_t rsv[3]; + uint32_t full_drop_cnt; + uint32_t part_drop_cnt; + uint32_t oq_drop_cnt; + uint32_t rev1[2]; +}; + #define HNS3_MAX_TQP_NUM_HIP08_PF 64 #define HNS3_DEFAULT_TX_BUF 0x4000 /* 16k bytes */ #define HNS3_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */