X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fhns3%2Fhns3_cmd.h;h=81bc9e9d98c1bd816e320b0228b448def9242c44;hb=daa02b5cddbb8e11b31d41e2bf7bb1ae64dcae2f;hp=ff424a0b65dfc1c0aa03d407566246cb0c7f20c8;hpb=c6332c3cf9f08f5426d53b927a821ea4a28697fb;p=dpdk.git diff --git a/drivers/net/hns3/hns3_cmd.h b/drivers/net/hns3/hns3_cmd.h index ff424a0b65..81bc9e9d98 100644 --- a/drivers/net/hns3/hns3_cmd.h +++ b/drivers/net/hns3/hns3_cmd.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2018-2019 Hisilicon Limited. + * Copyright(c) 2018-2021 HiSilicon Limited. */ #ifndef _HNS3_CMD_H_ @@ -56,13 +56,6 @@ enum hns3_cmd_return_status { HNS3_CMD_ROH_CHECK_FAIL = 12 }; -enum hns3_cmd_status { - HNS3_STATUS_SUCCESS = 0, - HNS3_ERR_CSQ_FULL = -1, - HNS3_ERR_CSQ_TIMEOUT = -2, - HNS3_ERR_CSQ_ERROR = -3, -}; - struct hns3_misc_vector { uint8_t *addr; int vector_irq; @@ -72,7 +65,7 @@ struct hns3_cmq { struct hns3_cmq_ring csq; struct hns3_cmq_ring crq; uint16_t tx_timeout; - enum hns3_cmd_status last_status; + enum hns3_cmd_return_status last_status; }; enum hns3_opcode_type { @@ -95,16 +88,39 @@ enum hns3_opcode_type { HNS3_OPC_QUERY_REG_NUM = 0x0040, HNS3_OPC_QUERY_32_BIT_REG = 0x0041, HNS3_OPC_QUERY_64_BIT_REG = 0x0042, + HNS3_OPC_DFX_BD_NUM = 0x0043, + HNS3_OPC_DFX_BIOS_COMMON_REG = 0x0044, + HNS3_OPC_DFX_SSU_REG_0 = 0x0045, + HNS3_OPC_DFX_SSU_REG_1 = 0x0046, + HNS3_OPC_DFX_IGU_EGU_REG = 0x0047, + HNS3_OPC_DFX_RPU_REG_0 = 0x0048, + HNS3_OPC_DFX_RPU_REG_1 = 0x0049, + HNS3_OPC_DFX_NCSI_REG = 0x004A, + HNS3_OPC_DFX_RTC_REG = 0x004B, + HNS3_OPC_DFX_PPP_REG = 0x004C, + HNS3_OPC_DFX_RCB_REG = 0x004D, + HNS3_OPC_DFX_TQP_REG = 0x004E, + HNS3_OPC_DFX_SSU_REG_2 = 0x004F, HNS3_OPC_QUERY_DEV_SPECS = 0x0050, + HNS3_OPC_SSU_DROP_REG = 0x0065, + /* MAC command */ HNS3_OPC_CONFIG_MAC_MODE = 0x0301, + HNS3_OPC_CONFIG_AN_MODE = 0x0304, HNS3_OPC_QUERY_LINK_STATUS = 0x0307, HNS3_OPC_CONFIG_MAX_FRM_SIZE = 0x0308, HNS3_OPC_CONFIG_SPEED_DUP = 0x0309, + HNS3_OPC_QUERY_MAC_TNL_INT = 0x0310, + HNS3_OPC_MAC_TNL_INT_EN = 0x0311, + HNS3_OPC_CLEAR_MAC_TNL_INT = 0x0312, HNS3_OPC_CONFIG_FEC_MODE = 0x031A, + /* PTP command */ + HNS3_OPC_PTP_INT_EN = 0x0501, + HNS3_OPC_CFG_PTP_MODE = 0x0507, + /* PFC/Pause commands */ HNS3_OPC_CFG_MAC_PAUSE_EN = 0x0701, HNS3_OPC_CFG_PFC_PAUSE_EN = 0x0702, @@ -146,6 +162,9 @@ enum hns3_opcode_type { HNS3_OPC_TM_INTERNAL_CNT = 0x0851, HNS3_OPC_TM_INTERNAL_STS_1 = 0x0852, + HNS3_OPC_TM_PORT_LIMIT_RATE = 0x0870, + HNS3_OPC_TM_TC_LIMIT_RATE = 0x0871, + /* Mailbox cmd */ HNS3_OPC_MBX_VF_TO_PF = 0x2001, @@ -209,11 +228,13 @@ enum hns3_opcode_type { /* Firmware stats command */ HNS3_OPC_FIRMWARE_COMPAT_CFG = 0x701A, + /* Firmware control phy command */ + HNS3_OPC_PHY_PARAM_CFG = 0x7025, /* SFP command */ HNS3_OPC_GET_SFP_EEPROM = 0x7100, HNS3_OPC_GET_SFP_EXIST = 0x7101, - HNS3_OPC_SFP_GET_SPEED = 0x7104, + HNS3_OPC_GET_SFP_INFO = 0x7104, /* Interrupts commands */ HNS3_OPC_ADD_RING_TO_VECTOR = 0x1503, @@ -234,6 +255,8 @@ enum hns3_opcode_type { HNS3_OPC_QUERY_MSIX_INT_STS_BD_NUM = 0x1513, HNS3_OPC_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514, HNS3_OPC_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515, + HNS3_OPC_QUERY_ALL_ERR_BD_NUM = 0x1516, + HNS3_OPC_QUERY_ALL_ERR_INFO = 0x1517, HNS3_OPC_IGU_EGU_TNL_INT_EN = 0x1803, HNS3_OPC_IGU_COMMON_INT_EN = 0x1806, HNS3_OPC_TM_QCN_MEM_INT_CFG = 0x1A14, @@ -286,17 +309,30 @@ struct hns3_rx_priv_buff_cmd { #define HNS3_FW_VERSION_BYTE0_M GENMASK(7, 0) enum HNS3_CAPS_BITS { - HNS3_CAPS_UDP_GSO_B, - HNS3_CAPS_ATR_B, - HNS3_CAPS_FD_QUEUE_REGION_B, + /* + * The following capability index definitions must be the same as those + * of the firmware. + */ + HNS3_CAPS_FD_QUEUE_REGION_B = 2, HNS3_CAPS_PTP_B, - HNS3_CAPS_INT_QL_B, - HNS3_CAPS_SIMPLE_BD_B, - HNS3_CAPS_TX_PUSH_B, - HNS3_CAPS_PHY_IMP_B, + HNS3_CAPS_TX_PUSH_B = 6, + HNS3_CAPS_PHY_IMP_B = 7, HNS3_CAPS_TQP_TXRX_INDEP_B, HNS3_CAPS_HW_PAD_B, HNS3_CAPS_STASH_B, + HNS3_CAPS_UDP_TUNNEL_CSUM_B, + HNS3_CAPS_RAS_IMP_B, + HNS3_CAPS_RXD_ADV_LAYOUT_B = 15, + HNS3_CAPS_TM_B = 17, +}; + +/* Capabilities of VF dependent on the PF */ +enum HNS3VF_CAPS_BITS { + /* + * The following capability index definitions must be the same as those + * in kernel side PF. + */ + HNS3VF_CAPS_VLAN_FLT_MOD_B = 0, }; enum HNS3_API_CAP_BITS { @@ -435,8 +471,6 @@ struct hns3_umv_spc_alc_cmd { #define HNS3_CFG_RD_LEN_BYTES 16 #define HNS3_CFG_RD_LEN_UNIT 4 -#define HNS3_CFG_VMDQ_S 0 -#define HNS3_CFG_VMDQ_M GENMASK(7, 0) #define HNS3_CFG_TC_NUM_S 8 #define HNS3_CFG_TC_NUM_M GENMASK(15, 8) #define HNS3_CFG_TQP_DESC_N_S 16 @@ -646,11 +680,47 @@ enum hns3_promisc_type { #define HNS3_LINK_EVENT_REPORT_EN_B 0 #define HNS3_NCSI_ERROR_REPORT_EN_B 1 +#define HNS3_FIRMWARE_PHY_DRIVER_EN_B 2 struct hns3_firmware_compat_cmd { uint32_t compat; uint8_t rsv[20]; }; +/* Bitmap flags in supported, advertising and lp_advertising */ +#define HNS3_PHY_LINK_SPEED_10M_HD_BIT BIT(0) +#define HNS3_PHY_LINK_SPEED_10M_BIT BIT(1) +#define HNS3_PHY_LINK_SPEED_100M_HD_BIT BIT(2) +#define HNS3_PHY_LINK_SPEED_100M_BIT BIT(3) +#define HNS3_PHY_LINK_SPEED_1000M_BIT BIT(5) +#define HNS3_PHY_LINK_MODE_AUTONEG_BIT BIT(6) +#define HNS3_PHY_LINK_MODE_PAUSE_BIT BIT(13) +#define HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT BIT(14) + +#define HNS3_PHY_PARAM_CFG_BD_NUM 2 +struct hns3_phy_params_bd0_cmd { + uint32_t speed; +#define HNS3_PHY_DUPLEX_CFG_B 0 + uint8_t duplex; +#define HNS3_PHY_AUTONEG_CFG_B 0 + uint8_t autoneg; + uint8_t eth_tp_mdix; + uint8_t eth_tp_mdix_ctrl; + uint8_t port; + uint8_t transceiver; + uint8_t phy_address; + uint8_t rsv; + uint32_t supported; + uint32_t advertising; + uint32_t lp_advertising; +}; + +struct hns3_phy_params_bd1_cmd { + uint8_t master_slave_cfg; + uint8_t master_slave_state; + uint8_t rsv1[2]; + uint32_t rsv2[5]; +}; + #define HNS3_MAC_TX_EN_B 6 #define HNS3_MAC_RX_EN_B 7 #define HNS3_MAC_PAD_TX_B 11 @@ -709,13 +779,6 @@ struct hns3_config_auto_neg_cmd { uint8_t rsv[20]; }; -#define HNS3_MAC_CFG_FEC_AUTO_EN_B 0 -#define HNS3_MAC_CFG_FEC_MODE_S 1 -#define HNS3_MAC_CFG_FEC_MODE_M GENMASK(3, 1) -#define HNS3_MAC_FEC_OFF 0 -#define HNS3_MAC_FEC_BASER 1 -#define HNS3_MAC_FEC_RS 2 - #define HNS3_SFP_INFO_BD0_LEN 20UL #define HNS3_SFP_INFO_BDX_LEN 24UL @@ -730,14 +793,36 @@ struct hns3_sfp_type { uint8_t ext_type; }; -struct hns3_sfp_speed_cmd { - uint32_t sfp_speed; - uint8_t query_type; /* 0: sfp speed, 1: active fec */ - uint8_t active_fec; /* current FEC mode */ - uint16_t rsv1; - uint32_t rsv2[4]; +/* Bitmap flags in supported_speed */ +#define HNS3_FIBER_LINK_SPEED_1G_BIT BIT(0) +#define HNS3_FIBER_LINK_SPEED_10G_BIT BIT(1) +#define HNS3_FIBER_LINK_SPEED_25G_BIT BIT(2) +#define HNS3_FIBER_LINK_SPEED_50G_BIT BIT(3) +#define HNS3_FIBER_LINK_SPEED_100G_BIT BIT(4) +#define HNS3_FIBER_LINK_SPEED_40G_BIT BIT(5) +#define HNS3_FIBER_LINK_SPEED_100M_BIT BIT(6) +#define HNS3_FIBER_LINK_SPEED_10M_BIT BIT(7) +#define HNS3_FIBER_LINK_SPEED_200G_BIT BIT(8) + +struct hns3_sfp_info_cmd { + uint32_t sfp_speed; + uint8_t query_type; /* 0: sfp speed, 1: active */ + uint8_t active_fec; /* current FEC mode */ + uint8_t autoneg; /* current autoneg state */ + /* 0: not support autoneg, 1: support autoneg */ + uint8_t autoneg_ability; + uint32_t supported_speed; /* speed supported by current media */ + uint32_t module_type; + uint8_t rsv1[8]; }; +#define HNS3_MAC_CFG_FEC_AUTO_EN_B 0 +#define HNS3_MAC_CFG_FEC_MODE_S 1 +#define HNS3_MAC_CFG_FEC_MODE_M GENMASK(3, 1) +#define HNS3_MAC_FEC_OFF 0 +#define HNS3_MAC_FEC_BASER 1 +#define HNS3_MAC_FEC_RS 2 + /* Configure FEC mode, opcode:0x031A */ struct hns3_config_fec_cmd { uint8_t fec_mode; @@ -838,7 +923,8 @@ enum hns3_mac_vlan_add_resp_code { HNS3_ADD_MC_OVERFLOW, /* ADD failed for MC overflow */ }; -#define HNS3_MC_MAC_VLAN_ADD_DESC_NUM 3 +#define HNS3_MC_MAC_VLAN_OPS_DESC_NUM 3 +#define HNS3_UC_MAC_VLAN_OPS_DESC_NUM 1 #define HNS3_MAC_VLAN_BIT0_EN_B 0 #define HNS3_MAC_VLAN_BIT1_EN_B 1 @@ -873,10 +959,16 @@ struct hns3_reset_tqp_queue_cmd { #define HNS3_CFG_RESET_MAC_B 3 #define HNS3_CFG_RESET_FUNC_B 7 +#define HNS3_CFG_RESET_RCB_B 1 struct hns3_reset_cmd { uint8_t mac_func_reset; uint8_t fun_reset_vfid; - uint8_t rsv[22]; + uint8_t fun_reset_rcb; + uint8_t rsv1; + uint16_t fun_reset_rcb_vqid_start; + uint16_t fun_reset_rcb_vqid_num; + uint8_t fun_reset_rcb_return_status; + uint8_t rsv2[15]; }; #define HNS3_QUERY_DEV_SPECS_BD_NUM 4 @@ -892,6 +984,50 @@ struct hns3_dev_specs_0_cmd { uint32_t max_tm_rate; }; +struct hns3_query_rpu_cmd { + uint32_t tc_queue_num; + uint32_t rsv1[2]; + uint32_t rpu_rx_pkt_drop_cnt; + uint32_t rsv2[2]; +}; + +#define HNS3_OPC_SSU_DROP_REG_NUM 2 + +struct hns3_query_ssu_cmd { + uint8_t rxtx; + uint8_t rsv[3]; + uint32_t full_drop_cnt; + uint32_t part_drop_cnt; + uint32_t oq_drop_cnt; + uint32_t rev1[2]; +}; + +#define HNS3_PTP_ENABLE_B 0 +#define HNS3_PTP_TX_ENABLE_B 1 +#define HNS3_PTP_RX_ENABLE_B 2 + +#define HNS3_PTP_TYPE_S 0 +#define HNS3_PTP_TYPE_M (0x3 << HNS3_PTP_TYPE_S) + +#define ALL_PTP_V2_TYPE 0xF +#define HNS3_PTP_MESSAGE_TYPE_S 0 +#define HNS3_PTP_MESSAGE_TYPE_M (0xF << HNS3_PTP_MESSAGE_TYPE_S) + +#define PTP_TYPE_L2_V2_TYPE 0 + +struct hns3_ptp_mode_cfg_cmd { + uint8_t enable; + uint8_t ptp_type; + uint8_t v2_message_type_1; + uint8_t v2_message_type_0; + uint8_t rsv[20]; +}; + +struct hns3_ptp_int_cmd { + uint8_t int_en; + uint8_t rsvd[23]; +}; + #define HNS3_MAX_TQP_NUM_HIP08_PF 64 #define HNS3_DEFAULT_TX_BUF 0x4000 /* 16k bytes */ #define HNS3_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */