X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fhns3%2Fhns3_cmd.h;h=da770ac9582e46c4b149d795dc9d04b89488dc32;hb=1256805dd54d;hp=be0ecbe86b2db8fe601c9e0c96e6b3efd178a7b7;hpb=737f30e1c3ab24c46b7a56b59f360517f85f0196;p=dpdk.git

diff --git a/drivers/net/hns3/hns3_cmd.h b/drivers/net/hns3/hns3_cmd.h
index be0ecbe86b..da770ac958 100644
--- a/drivers/net/hns3/hns3_cmd.h
+++ b/drivers/net/hns3/hns3_cmd.h
@@ -79,6 +79,7 @@ enum hns3_opcode_type {
 	HNS3_OPC_GBL_RST_STATUS         = 0x0021,
 	HNS3_OPC_QUERY_FUNC_STATUS      = 0x0022,
 	HNS3_OPC_QUERY_PF_RSRC          = 0x0023,
+	HNS3_OPC_QUERY_VF_RSRC          = 0x0024,
 	HNS3_OPC_GET_CFG_PARAM          = 0x0025,
 	HNS3_OPC_PF_RST_DONE            = 0x0026,
 
@@ -209,6 +210,10 @@ enum hns3_opcode_type {
 	/* SFP command */
 	HNS3_OPC_SFP_GET_SPEED          = 0x7104,
 
+	/* Interrupts commands */
+	HNS3_OPC_ADD_RING_TO_VECTOR	= 0x1503,
+	HNS3_OPC_DEL_RING_TO_VECTOR	= 0x1504,
+
 	/* Error INT commands */
 	HNS3_QUERY_MSIX_INT_STS_BD_NUM          = 0x1513,
 	HNS3_QUERY_CLEAR_ALL_MPF_MSIX_INT       = 0x1514,
@@ -248,6 +253,14 @@ struct hns3_rx_priv_buff_cmd {
 	uint8_t rsv[6];
 };
 
+#define HNS3_FW_VERSION_BYTE3_S		24
+#define HNS3_FW_VERSION_BYTE3_M		GENMASK(31, 24)
+#define HNS3_FW_VERSION_BYTE2_S		16
+#define HNS3_FW_VERSION_BYTE2_M		GENMASK(23, 16)
+#define HNS3_FW_VERSION_BYTE1_S		8
+#define HNS3_FW_VERSION_BYTE1_M		GENMASK(15, 8)
+#define HNS3_FW_VERSION_BYTE0_S		0
+#define HNS3_FW_VERSION_BYTE0_M		GENMASK(7, 0)
 struct hns3_query_version_cmd {
 	uint32_t firmware;
 	uint32_t firmware_rsv[5];
@@ -333,8 +346,9 @@ struct hns3_func_status_cmd {
 	uint8_t rsv[2];
 };
 
-#define HNS3_PF_VEC_NUM_S		0
-#define HNS3_PF_VEC_NUM_M		GENMASK(7, 0)
+#define HNS3_VEC_NUM_S		0
+#define HNS3_VEC_NUM_M		GENMASK(7, 0)
+#define HNS3_MIN_VECTOR_NUM	2 /* one for msi-x, another for IO */
 struct hns3_pf_res_cmd {
 	uint16_t tqp_num;
 	uint16_t buf_size;
@@ -347,6 +361,15 @@ struct hns3_pf_res_cmd {
 	uint32_t rsv[2];
 };
 
+struct hns3_vf_res_cmd {
+	uint16_t tqp_num;
+	uint16_t reserved;
+	uint16_t msixcap_localid_ba_nic;
+	uint16_t msixcap_localid_ba_rocee;
+	uint16_t vf_intr_vector_number;
+	uint16_t rsv[7];
+};
+
 #define HNS3_UMV_SPC_ALC_B	0
 struct hns3_umv_spc_alc_cmd {
 	uint8_t allocate;
@@ -673,6 +696,36 @@ struct hns3_tqp_map_cmd {
 	uint8_t rsv[18];
 };
 
+enum hns3_ring_type {
+	HNS3_RING_TYPE_TX,
+	HNS3_RING_TYPE_RX
+};
+
+enum hns3_int_gl_idx {
+	HNS3_RING_GL_RX,
+	HNS3_RING_GL_TX,
+	HNS3_RING_GL_IMMEDIATE = 3
+};
+
+#define HNS3_RING_GL_IDX_S	0
+#define HNS3_RING_GL_IDX_M	GENMASK(1, 0)
+
+#define HNS3_VECTOR_ELEMENTS_PER_CMD	10
+
+#define HNS3_INT_TYPE_S		0
+#define HNS3_INT_TYPE_M		GENMASK(1, 0)
+#define HNS3_TQP_ID_S		2
+#define HNS3_TQP_ID_M		GENMASK(12, 2)
+#define HNS3_INT_GL_IDX_S	13
+#define HNS3_INT_GL_IDX_M	GENMASK(14, 13)
+struct hns3_ctrl_vector_chain_cmd {
+	uint8_t int_vector_id;
+	uint8_t int_cause_num;
+	uint16_t tqp_type_and_id[HNS3_VECTOR_ELEMENTS_PER_CMD];
+	uint8_t vfid;
+	uint8_t rsv;
+};
+
 struct hns3_config_max_frm_size_cmd {
 	uint16_t max_frm_size;
 	uint8_t min_frm_size;