X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fhns3%2Fhns3_cmd.h;h=e704d0c40b38bc3ec9a40c183c9c7ce7cc253950;hb=fb7ad441d43d4152cb7bde992a1136c20d9166e9;hp=ff424a0b65dfc1c0aa03d407566246cb0c7f20c8;hpb=c6332c3cf9f08f5426d53b927a821ea4a28697fb;p=dpdk.git

diff --git a/drivers/net/hns3/hns3_cmd.h b/drivers/net/hns3/hns3_cmd.h
index ff424a0b65..e704d0c40b 100644
--- a/drivers/net/hns3/hns3_cmd.h
+++ b/drivers/net/hns3/hns3_cmd.h
@@ -95,14 +95,32 @@ enum hns3_opcode_type {
 	HNS3_OPC_QUERY_REG_NUM          = 0x0040,
 	HNS3_OPC_QUERY_32_BIT_REG       = 0x0041,
 	HNS3_OPC_QUERY_64_BIT_REG       = 0x0042,
+	HNS3_OPC_DFX_BD_NUM             = 0x0043,
+	HNS3_OPC_DFX_BIOS_COMMON_REG    = 0x0044,
+	HNS3_OPC_DFX_SSU_REG_0          = 0x0045,
+	HNS3_OPC_DFX_SSU_REG_1          = 0x0046,
+	HNS3_OPC_DFX_IGU_EGU_REG        = 0x0047,
+	HNS3_OPC_DFX_RPU_REG_0          = 0x0048,
+	HNS3_OPC_DFX_RPU_REG_1          = 0x0049,
+	HNS3_OPC_DFX_NCSI_REG           = 0x004A,
+	HNS3_OPC_DFX_RTC_REG            = 0x004B,
+	HNS3_OPC_DFX_PPP_REG            = 0x004C,
+	HNS3_OPC_DFX_RCB_REG            = 0x004D,
+	HNS3_OPC_DFX_TQP_REG            = 0x004E,
+	HNS3_OPC_DFX_SSU_REG_2          = 0x004F,
 
 	HNS3_OPC_QUERY_DEV_SPECS        = 0x0050,
 
+	HNS3_OPC_SSU_DROP_REG           = 0x0065,
+
 	/* MAC command */
 	HNS3_OPC_CONFIG_MAC_MODE        = 0x0301,
 	HNS3_OPC_QUERY_LINK_STATUS      = 0x0307,
 	HNS3_OPC_CONFIG_MAX_FRM_SIZE    = 0x0308,
 	HNS3_OPC_CONFIG_SPEED_DUP       = 0x0309,
+	HNS3_OPC_QUERY_MAC_TNL_INT      = 0x0310,
+	HNS3_OPC_MAC_TNL_INT_EN         = 0x0311,
+	HNS3_OPC_CLEAR_MAC_TNL_INT      = 0x0312,
 	HNS3_OPC_CONFIG_FEC_MODE        = 0x031A,
 
 	/* PFC/Pause commands */
@@ -209,6 +227,8 @@ enum hns3_opcode_type {
 
 	/* Firmware stats command */
 	HNS3_OPC_FIRMWARE_COMPAT_CFG    = 0x701A,
+	/* Firmware control phy command */
+	HNS3_OPC_PHY_PARAM_CFG          = 0x7025,
 
 	/* SFP command */
 	HNS3_OPC_GET_SFP_EEPROM         = 0x7100,
@@ -297,6 +317,11 @@ enum HNS3_CAPS_BITS {
 	HNS3_CAPS_TQP_TXRX_INDEP_B,
 	HNS3_CAPS_HW_PAD_B,
 	HNS3_CAPS_STASH_B,
+	HNS3_CAPS_UDP_TUNNEL_CSUM_B,
+	HNS3_CAPS_RAS_IMP_B,
+	HNS3_CAPS_FEC_B,
+	HNS3_CAPS_PAUSE_B,
+	HNS3_CAPS_RXD_ADV_LAYOUT_B,
 };
 
 enum HNS3_API_CAP_BITS {
@@ -646,11 +671,46 @@ enum hns3_promisc_type {
 
 #define HNS3_LINK_EVENT_REPORT_EN_B	0
 #define HNS3_NCSI_ERROR_REPORT_EN_B	1
+#define HNS3_FIRMWARE_PHY_DRIVER_EN_B	2
 struct hns3_firmware_compat_cmd {
 	uint32_t compat;
 	uint8_t rsv[20];
 };
 
+/* Bitmap flags in supported, advertising and lp_advertising */
+#define HNS3_PHY_LINK_SPEED_10M_HD_BIT		BIT(0)
+#define HNS3_PHY_LINK_SPEED_10M_BIT		BIT(1)
+#define HNS3_PHY_LINK_SPEED_100M_HD_BIT		BIT(2)
+#define HNS3_PHY_LINK_SPEED_100M_BIT		BIT(3)
+#define HNS3_PHY_LINK_MODE_AUTONEG_BIT		BIT(6)
+#define HNS3_PHY_LINK_MODE_PAUSE_BIT		BIT(13)
+#define HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT	BIT(14)
+
+#define HNS3_PHY_PARAM_CFG_BD_NUM	2
+struct hns3_phy_params_bd0_cmd {
+	uint32_t speed;
+#define HNS3_PHY_DUPLEX_CFG_B		0
+	uint8_t duplex;
+#define HNS3_PHY_AUTONEG_CFG_B	0
+	uint8_t autoneg;
+	uint8_t eth_tp_mdix;
+	uint8_t eth_tp_mdix_ctrl;
+	uint8_t port;
+	uint8_t transceiver;
+	uint8_t phy_address;
+	uint8_t rsv;
+	uint32_t supported;
+	uint32_t advertising;
+	uint32_t lp_advertising;
+};
+
+struct hns3_phy_params_bd1_cmd {
+	uint8_t master_slave_cfg;
+	uint8_t master_slave_state;
+	uint8_t rsv1[2];
+	uint32_t rsv2[5];
+};
+
 #define HNS3_MAC_TX_EN_B		6
 #define HNS3_MAC_RX_EN_B		7
 #define HNS3_MAC_PAD_TX_B		11
@@ -892,6 +952,24 @@ struct hns3_dev_specs_0_cmd {
 	uint32_t max_tm_rate;
 };
 
+struct hns3_query_rpu_cmd {
+	uint32_t tc_queue_num;
+	uint32_t rsv1[2];
+	uint32_t rpu_rx_pkt_drop_cnt;
+	uint32_t rsv2[2];
+};
+
+#define HNS3_OPC_SSU_DROP_REG_NUM 2
+
+struct hns3_query_ssu_cmd {
+	uint8_t rxtx;
+	uint8_t rsv[3];
+	uint32_t full_drop_cnt;
+	uint32_t part_drop_cnt;
+	uint32_t oq_drop_cnt;
+	uint32_t rev1[2];
+};
+
 #define HNS3_MAX_TQP_NUM_HIP08_PF	64
 #define HNS3_DEFAULT_TX_BUF		0x4000    /* 16k  bytes */
 #define HNS3_TOTAL_PKT_BUF		0x108000  /* 1.03125M bytes */