X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fhns3%2Fhns3_dcb.h;h=e06ec177c8a23d92e9614a27511abaaa9108b98a;hb=7fbbc981d54fa59fb5f3242d0bf3210e9d23137b;hp=05c97865520e59bad09b24f7b0316c801c386caf;hpb=76d794566d432c50e807c05d227718fb8aaa4e51;p=dpdk.git

diff --git a/drivers/net/hns3/hns3_dcb.h b/drivers/net/hns3/hns3_dcb.h
index 05c9786552..e06ec177c8 100644
--- a/drivers/net/hns3/hns3_dcb.h
+++ b/drivers/net/hns3/hns3_dcb.h
@@ -1,10 +1,14 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2018-2019 Hisilicon Limited.
+ * Copyright(c) 2018-2021 HiSilicon Limited.
  */
 
 #ifndef _HNS3_DCB_H_
 #define _HNS3_DCB_H_
 
+#include <stdint.h>
+
+#include "hns3_cmd.h"
+
 #define HNS3_ETHER_MAX_RATE		100000
 
 /* MAC Pause */
@@ -16,7 +20,7 @@
 
 /* SP or DWRR */
 #define HNS3_DCB_TX_SCHD_DWRR_MSK	BIT(0)
-#define HNS3_DCB_TX_SCHD_SP_MSK		(0xFE)
+#define HNS3_DCB_TX_SCHD_SP_MSK		0xFE
 
 enum hns3_shap_bucket {
 	HNS3_DCB_SHAP_C_BUCKET = 0,
@@ -81,18 +85,46 @@ struct hns3_nq_to_qs_link_cmd {
 #define HNS3_DCB_SHAP_BS_S_MSK  GENMASK(25, 21)
 #define HNS3_DCB_SHAP_BS_S_LSH	21
 
+/*
+ * For more flexible selection of shapping algorithm in different network
+ * engine, the algorithm calculating shapping parameter is moved to firmware to
+ * execute. Bit HNS3_TM_RATE_VLD_B of flag field in hns3_pri_shapping_cmd,
+ * hns3_pg_shapping_cmd or hns3_port_shapping_cmd is set to 1 to require
+ * firmware to recalculate shapping parameters. However, whether the parameters
+ * are recalculated depends on the firmware version. If firmware doesn't support
+ * the calculation of shapping parameters, such as on network engine with
+ * revision id 0x21, the value driver calculated will be used to configure to
+ * hardware. On the contrary, firmware ignores configuration of driver
+ * and recalculates the parameter.
+ */
+#define HNS3_TM_RATE_VLD_B	0
+
 struct hns3_pri_shapping_cmd {
 	uint8_t pri_id;
 	uint8_t rsvd[3];
 	uint32_t pri_shapping_para;
-	uint32_t rsvd1[4];
+	uint8_t flag;
+	uint8_t rsvd1[3];
+	uint32_t pri_rate;  /* Unit Mbps */
+	uint8_t rsvd2[8];
 };
 
 struct hns3_pg_shapping_cmd {
 	uint8_t pg_id;
 	uint8_t rsvd[3];
 	uint32_t pg_shapping_para;
-	uint32_t rsvd1[4];
+	uint8_t flag;
+	uint8_t rsvd1[3];
+	uint32_t pg_rate; /* Unit Mbps */
+	uint8_t rsvd2[8];
+};
+
+struct hns3_port_shapping_cmd {
+	uint32_t port_shapping_para;
+	uint8_t flag;
+	uint8_t rsvd[3];
+	uint32_t port_rate;   /* Unit Mbps */
+	uint8_t rsvd1[12];
 };
 
 #define HNS3_BP_GRP_NUM			32
@@ -115,11 +147,6 @@ struct hns3_pfc_en_cmd {
 	uint8_t rsvd[22];
 };
 
-struct hns3_port_shapping_cmd {
-	uint32_t port_shapping_para;
-	uint32_t rsvd[5];
-};
-
 struct hns3_cfg_pause_param_cmd {
 	uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
 	uint8_t pause_trans_gap;
@@ -180,6 +207,8 @@ int hns3_dcb_pfc_enable(struct rte_eth_dev *dev,
 int hns3_queue_to_tc_mapping(struct hns3_hw *hw, uint16_t nb_rx_q,
 			     uint16_t nb_tx_q);
 
-int hns3_dcb_cfg_update(struct hns3_adapter *hns);
+int hns3_update_queue_map_configure(struct hns3_adapter *hns);
+int hns3_port_shaper_update(struct hns3_hw *hw, uint32_t speed);
+uint8_t hns3_txq_mapped_tc_get(struct hns3_hw *hw, uint16_t txq_no);
 
 #endif /* _HNS3_DCB_H_ */