X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fhns3%2Fhns3_ethdev.c;h=73d504253d2b5a42a3631a5323f18077df83200d;hb=a3d4f4d291d79e2801397055067d903ef5e4d4aa;hp=4797cfb2f2b8278182e56e16415c614ecbc2fe39;hpb=395b5e08ef8de472aedb599d0dfac245d9b1d55f;p=dpdk.git diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 4797cfb2f2..73d504253d 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -56,6 +56,9 @@ #define HNS3_FUN_RST_ING_B 0 #define HNS3_VECTOR0_IMP_RESET_INT_B 1 +#define HNS3_VECTOR0_IMP_CMDQ_ERR_B 4U +#define HNS3_VECTOR0_IMP_RD_POISON_B 5U +#define HNS3_VECTOR0_ALL_MSIX_ERR_B 6U #define HNS3_RESET_WAIT_MS 100 #define HNS3_RESET_WAIT_CNT 200 @@ -97,12 +100,14 @@ hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) struct hns3_hw *hw = &hns->hw; uint32_t vector0_int_stats; uint32_t cmdq_src_val; + uint32_t hw_err_src_reg; uint32_t val; enum hns3_evt_cause ret; /* fetch the events from their corresponding regs */ vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG); + hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG); /* * Assumption: If by any chance reset and mailbox events are reported @@ -145,8 +150,9 @@ hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) } /* check for vector0 msix event source */ - if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) { - val = vector0_int_stats; + if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK || + hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) { + val = vector0_int_stats | hw_err_src_reg; ret = HNS3_VECTOR0_EVENT_ERR; goto out; } @@ -159,9 +165,9 @@ hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) goto out; } - if (clearval && (vector0_int_stats || cmdq_src_val)) - hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x", - vector0_int_stats, cmdq_src_val); + if (clearval && (vector0_int_stats || cmdq_src_val || hw_err_src_reg)) + hns3_warn(hw, "vector0_int_stats:0x%x cmdq_src_val:0x%x hw_err_src_reg:0x%x", + vector0_int_stats, cmdq_src_val, hw_err_src_reg); val = vector0_int_stats; ret = HNS3_VECTOR0_EVENT_OTHER; out: @@ -215,11 +221,14 @@ hns3_interrupt_handler(void *param) /* vector 0 interrupt is shared with reset and mailbox source events. */ if (event_cause == HNS3_VECTOR0_EVENT_ERR) { + hns3_warn(hw, "Received err interrupt"); hns3_handle_msix_error(hns, &hw->reset.request); + hns3_handle_ras_error(hns, &hw->reset.request); hns3_schedule_reset(hns); - } else if (event_cause == HNS3_VECTOR0_EVENT_RST) + } else if (event_cause == HNS3_VECTOR0_EVENT_RST) { + hns3_warn(hw, "Received reset interrupt"); hns3_schedule_reset(hns); - else if (event_cause == HNS3_VECTOR0_EVENT_MBX) + } else if (event_cause == HNS3_VECTOR0_EVENT_MBX) hns3_dev_handle_mbx_msg(hw); else hns3_err(hw, "Received unknown event"); @@ -1401,7 +1410,7 @@ hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); struct hns3_mac_vlan_tbl_entry_cmd req; struct hns3_pf *pf = &hns->pf; - struct hns3_cmd_desc desc; + struct hns3_cmd_desc desc[3]; char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; uint16_t egress_port = 0; uint8_t vf_id; @@ -1435,7 +1444,7 @@ hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) * it if the entry is inexistent. Repeated unicast entry * is not allowed in the mac vlan table. */ - ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false); + ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false); if (ret == -ENOENT) { if (!hns3_is_umv_space_full(hw)) { ret = hns3_add_mac_vlan_tbl(hw, &req, NULL); @@ -2342,6 +2351,12 @@ hns3_dev_configure(struct rte_eth_dev *dev) if (ret) goto cfg_err; + hns->rx_simple_allowed = true; + hns->rx_vec_allowed = true; + hns->tx_simple_allowed = true; + hns->tx_vec_allowed = true; + + hns3_init_rx_ptype_tble(dev); hw->adapter_state = HNS3_NIC_CONFIGURED; return 0; @@ -2463,7 +2478,6 @@ hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) DEV_RX_OFFLOAD_JUMBO_FRAME | DEV_RX_OFFLOAD_RSS_HASH | DEV_RX_OFFLOAD_TCP_LRO); - info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE; info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_TX_OFFLOAD_IPV4_CKSUM | DEV_TX_OFFLOAD_TCP_CKSUM | @@ -2474,7 +2488,7 @@ hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) DEV_TX_OFFLOAD_VXLAN_TNL_TSO | DEV_TX_OFFLOAD_GRE_TNL_TSO | DEV_TX_OFFLOAD_GENEVE_TNL_TSO | - info->tx_queue_offload_capa | + DEV_TX_OFFLOAD_MBUF_FAST_FREE | hns3_txvlan_cap_get(hw)); info->rx_desc_lim = (struct rte_eth_desc_lim) { @@ -2492,12 +2506,18 @@ hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) }; info->default_rxconf = (struct rte_eth_rxconf) { + .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH, /* * If there are no available Rx buffer descriptors, incoming * packets are always dropped by hardware based on hns3 network * engine. */ .rx_drop_en = 1, + .offloads = 0, + }; + info->default_txconf = (struct rte_eth_txconf) { + .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH, + .offloads = 0, }; info->vmdq_queue_num = 0; @@ -3276,7 +3296,7 @@ hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc, + pf->dv_buf_size; shared_buf_tc = tc_num * aligned_mps + aligned_mps; - shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc), + shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc), HNS3_BUF_SIZE_UNIT); rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc); @@ -3306,8 +3326,7 @@ hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc, if (tc_num) hi_thrd = hi_thrd / tc_num; - hi_thrd = max_t(uint32_t, hi_thrd, - HNS3_BUF_MUL_BY * aligned_mps); + hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps); hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT); lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY; } else { @@ -4425,6 +4444,24 @@ hns3_clear_hw(struct hns3_hw *hw) return 0; } +static void +hns3_config_all_msix_error(struct hns3_hw *hw, bool enable) +{ + uint32_t val; + + /* + * The new firmware support report more hardware error types by + * msix mode. These errors are defined as RAS errors in hardware + * and belong to a different type from the MSI-x errors processed + * by the network driver. + * + * Network driver should open the new error report on initialition + */ + val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG); + hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0); + hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val); +} + static int hns3_init_pf(struct rte_eth_dev *eth_dev) { @@ -4467,6 +4504,8 @@ hns3_init_pf(struct rte_eth_dev *eth_dev) goto err_cmd_init; } + hns3_config_all_msix_error(hw, true); + ret = rte_intr_callback_register(&pci_dev->intr_handle, hns3_interrupt_handler, eth_dev); @@ -4550,6 +4589,7 @@ hns3_uninit_pf(struct rte_eth_dev *eth_dev) rte_intr_disable(&pci_dev->intr_handle); hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler, eth_dev); + hns3_config_all_msix_error(hw, false); hns3_cmd_uninit(hw); hns3_cmd_destroy_queue(hw); hw->io_base = NULL; @@ -4715,6 +4755,7 @@ hns3_dev_start(struct rte_eth_dev *dev) hw->adapter_state = HNS3_NIC_STARTED; rte_spinlock_unlock(&hw->lock); + hns3_rx_scattered_calc(dev); hns3_set_rxtx_function(dev); hns3_mp_req_start_rxtx(dev); rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev); @@ -4813,6 +4854,7 @@ hns3_dev_stop(struct rte_eth_dev *dev) hns3_dev_release_mbufs(hns); hw->adapter_state = HNS3_NIC_CONFIGURED; } + hns3_rx_scattered_reset(dev); rte_eal_alarm_cancel(hns3_service_handler, dev); rte_spinlock_unlock(&hw->lock); } @@ -5234,6 +5276,28 @@ hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels) return reset_level; } +static void +hns3_record_imp_error(struct hns3_adapter *hns) +{ + struct hns3_hw *hw = &hns->hw; + uint32_t reg_val; + + reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG); + if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) { + hns3_warn(hw, "Detected IMP RD poison!"); + hns3_error_int_stats_add(hns, "IMP_RD_POISON_INT_STS"); + hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0); + hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val); + } + + if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) { + hns3_warn(hw, "Detected IMP CMDQ error!"); + hns3_error_int_stats_add(hns, "CMDQ_MEM_ECC_INT_STS"); + hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0); + hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val); + } +} + static int hns3_prepare_reset(struct hns3_adapter *hns) { @@ -5257,6 +5321,7 @@ hns3_prepare_reset(struct hns3_adapter *hns) hw->reset.stats.request_cnt++; break; case HNS3_IMP_RESET: + hns3_record_imp_error(hns); reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG); hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val | BIT(HNS3_VECTOR0_IMP_RESET_INT_B)); @@ -5460,6 +5525,7 @@ hns3_reset_service(void *param) } static const struct eth_dev_ops hns3_eth_dev_ops = { + .dev_configure = hns3_dev_configure, .dev_start = hns3_dev_start, .dev_stop = hns3_dev_stop, .dev_close = hns3_dev_close, @@ -5485,7 +5551,8 @@ static const struct eth_dev_ops hns3_eth_dev_ops = { .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable, .rxq_info_get = hns3_rxq_info_get, .txq_info_get = hns3_txq_info_get, - .dev_configure = hns3_dev_configure, + .rx_burst_mode_get = hns3_rx_burst_mode_get, + .tx_burst_mode_get = hns3_tx_burst_mode_get, .flow_ctrl_get = hns3_flow_ctrl_get, .flow_ctrl_set = hns3_flow_ctrl_set, .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set, @@ -5522,6 +5589,8 @@ static int hns3_dev_init(struct rte_eth_dev *eth_dev) { struct hns3_adapter *hns = eth_dev->data->dev_private; + char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; + struct rte_ether_addr *eth_addr; struct hns3_hw *hw = &hns->hw; int ret; @@ -5594,6 +5663,15 @@ hns3_dev_init(struct rte_eth_dev *eth_dev) goto err_rte_zmalloc; } + eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr; + if (!rte_is_valid_assigned_ether_addr(eth_addr)) { + rte_eth_random_addr(hw->mac.mac_addr); + rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, + (struct rte_ether_addr *)hw->mac.mac_addr); + hns3_warn(hw, "default mac_addr from firmware is an invalid " + "unicast address, using random MAC address %s", + mac_str); + } rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr, ð_dev->data->mac_addrs[0]);