X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fhns3%2Fhns3_ethdev.c;h=e51512560e152da5730db88da10f13f84dc68c56;hb=0b3c74b9f7f6a935af257f7be590323694e23873;hp=c554d2adfc4b039752a3c828e3086d3d3120a857;hpb=c70d8e99fbde1830389be95ef2878767787bf2c6;p=dpdk.git diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index c554d2adfc..e51512560e 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -253,8 +253,8 @@ static void hns3_clear_all_event_cause(struct hns3_hw *hw) { uint32_t vector0_int_stats; - vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); + vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) hns3_warn(hw, "Probe during IMP reset interrupt"); @@ -640,7 +640,8 @@ hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable) ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg); if (ret) { - hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret); + hns3_err(hw, "%s strip rx vtag failed, ret = %d.", + enable ? "enable" : "disable", ret); return ret; } @@ -2273,24 +2274,6 @@ hns3_check_mq_mode(struct rte_eth_dev *dev) return 0; } -static int -hns3_check_dcb_cfg(struct rte_eth_dev *dev) -{ - struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); - - if (!hns3_dev_dcb_supported(hw)) { - hns3_err(hw, "this port does not support dcb configurations."); - return -EOPNOTSUPP; - } - - if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) { - hns3_err(hw, "MAC pause enabled, cannot config dcb info."); - return -EOPNOTSUPP; - } - - return 0; -} - static int hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en, enum hns3_ring_type queue_type, uint16_t queue_id) @@ -2426,6 +2409,30 @@ hns3_refresh_mtu(struct rte_eth_dev *dev, struct rte_eth_conf *conf) return 0; } +static int +hns3_setup_dcb(struct rte_eth_dev *dev) +{ + struct hns3_adapter *hns = dev->data->dev_private; + struct hns3_hw *hw = &hns->hw; + int ret; + + if (!hns3_dev_dcb_supported(hw)) { + hns3_err(hw, "this port does not support dcb configurations."); + return -EOPNOTSUPP; + } + + if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) { + hns3_err(hw, "MAC pause enabled, cannot config dcb info."); + return -EOPNOTSUPP; + } + + ret = hns3_dcb_configure(hns); + if (ret) + hns3_err(hw, "failed to config dcb: %d", ret); + + return ret; +} + static int hns3_check_link_speed(struct hns3_hw *hw, uint32_t link_speeds) { @@ -2491,13 +2498,11 @@ hns3_dev_configure(struct rte_eth_dev *dev) * work as usual. But these fake queues are imperceptible, and can not * be used by upper applications. */ - if (!hns3_dev_indep_txrx_supported(hw)) { - ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q); - if (ret) { - hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", - ret); - return ret; - } + ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q); + if (ret) { + hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", ret); + hw->cfg_max_queues = 0; + return ret; } hw->adapter_state = HNS3_NIC_CONFIGURING; @@ -2506,7 +2511,7 @@ hns3_dev_configure(struct rte_eth_dev *dev) goto cfg_err; if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) { - ret = hns3_check_dcb_cfg(dev); + ret = hns3_setup_dcb(dev); if (ret) goto cfg_err; } @@ -2545,6 +2550,7 @@ hns3_dev_configure(struct rte_eth_dev *dev) return 0; cfg_err: + hw->cfg_max_queues = 0; (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0); hw->adapter_state = HNS3_NIC_INITIALIZED; @@ -2791,8 +2797,6 @@ hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) .offloads = 0, }; - info->vmdq_queue_num = 0; - info->reta_size = hw->rss_ind_tbl_size; info->hash_key_size = HNS3_RSS_KEY_SIZE; info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT; @@ -3075,8 +3079,6 @@ hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc) req = (struct hns3_cfg_param_cmd *)desc[0].data; /* get the configuration */ - cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]), - HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S); cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]), HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S); cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]), @@ -3125,7 +3127,6 @@ hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc) ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]), HNS3_CFG_EXT_RSS_SIZE_M, HNS3_CFG_EXT_RSS_SIZE_S); - /* * Field ext_rss_size_max obtained from firmware will be more flexible * for future changes and expansions, which is an exponent of 2, instead @@ -3844,7 +3845,6 @@ hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw, for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) { priv = &buf_alloc->priv_buf[i]; mask = BIT((uint8_t)i); - if (hw->hw_tc_map & mask && !(hw->dcb_info.hw_pfc_map & mask)) { /* Clear the no pfc TC private buffer */ @@ -3930,7 +3930,6 @@ hns3_only_alloc_priv_buff(struct hns3_hw *hw, COMPENSATE_HALF_MPS_NUM * half_mps; min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT); rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT); - if (rx_priv < min_rx_priv) return false; @@ -5175,6 +5174,8 @@ hns3_init_pf(struct rte_eth_dev *eth_dev) goto err_cmd_init; } + hns3_tx_push_init(eth_dev); + /* * To ensure that the hardware environment is clean during * initialization, the driver actively clear the hardware environment @@ -5578,14 +5579,14 @@ hns3_do_start(struct hns3_adapter *hns, bool reset_queue) struct hns3_hw *hw = &hns->hw; int ret; - ret = hns3_dcb_cfg_update(hns); - if (ret) + ret = hns3_update_queue_map_configure(hns); + if (ret) { + hns3_err(hw, "failed to update queue mapping configuration, ret = %d", + ret); return ret; + } - /* - * The hns3_dcb_cfg_update may configure TM module, so - * hns3_tm_conf_update must called later. - */ + /* Note: hns3_tm_conf_update must be called after configuring DCB. */ ret = hns3_tm_conf_update(hw); if (ret) { PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret); @@ -5893,7 +5894,7 @@ hns3_dev_stop(struct rte_eth_dev *dev) /* Disable datapath on secondary process. */ hns3_mp_req_stop_rxtx(dev); /* Prevent crashes when queues are still in use. */ - rte_delay_ms(hw->tqps_num); + rte_delay_ms(hw->cfg_max_queues); rte_spinlock_lock(&hw->lock); if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) { @@ -6063,30 +6064,6 @@ hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) return 0; } -static void -hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode) -{ - switch (mode) { - case RTE_FC_NONE: - hw->requested_fc_mode = HNS3_FC_NONE; - break; - case RTE_FC_RX_PAUSE: - hw->requested_fc_mode = HNS3_FC_RX_PAUSE; - break; - case RTE_FC_TX_PAUSE: - hw->requested_fc_mode = HNS3_FC_TX_PAUSE; - break; - case RTE_FC_FULL: - hw->requested_fc_mode = HNS3_FC_FULL; - break; - default: - hw->requested_fc_mode = HNS3_FC_NONE; - hns3_warn(hw, "fc_mode(%u) exceeds member scope and is " - "configured to RTE_FC_NONE", mode); - break; - } -} - static int hns3_check_fc_autoneg_valid(struct hns3_hw *hw, uint8_t autoneg) { @@ -6160,8 +6137,6 @@ hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) return -EOPNOTSUPP; } - hns3_get_fc_mode(hw, fc_conf->mode); - rte_spinlock_lock(&hw->lock); ret = hns3_fc_enable(dev, fc_conf); rte_spinlock_unlock(&hw->lock); @@ -6208,8 +6183,6 @@ hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev, return -EOPNOTSUPP; } - hns3_get_fc_mode(hw, pfc_conf->fc.mode); - rte_spinlock_lock(&hw->lock); ret = hns3_dcb_pfc_enable(dev, pfc_conf); rte_spinlock_unlock(&hw->lock); @@ -6323,7 +6296,6 @@ hns3_is_reset_pending(struct hns3_adapter *hns) hns3_check_event_cause(hns, NULL); reset = hns3_get_reset_level(hns, &hw->reset.pending); - if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) { hns3_warn(hw, "High level reset %d is pending", reset); @@ -6537,7 +6509,7 @@ hns3_stop_service(struct hns3_adapter *hns) rte_wmb(); /* Disable datapath on secondary process. */ hns3_mp_req_stop_rxtx(eth_dev); - rte_delay_ms(hw->tqps_num); + rte_delay_ms(hw->cfg_max_queues); rte_spinlock_lock(&hw->lock); if (hns->hw.adapter_state == HNS3_NIC_STARTED || @@ -6995,9 +6967,11 @@ hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode) return ret; /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */ - if (!is_fec_mode_one_bit_set(mode)) - hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD," + if (!is_fec_mode_one_bit_set(mode)) { + hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD, " "FEC mode should be only one bit set", mode); + return -EINVAL; + } /* * Check whether the configured mode is within the FEC capability. @@ -7446,8 +7420,8 @@ hns3_dev_init(struct rte_eth_dev *eth_dev) "process, ret = %d", ret); goto err_mp_init_secondary; } - hw->secondary_cnt++; + hns3_tx_push_init(eth_dev); return 0; } @@ -7602,5 +7576,5 @@ RTE_PMD_REGISTER_PARAM_STRING(net_hns3, HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common " HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common " HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> "); -RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE); -RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE); +RTE_LOG_REGISTER_SUFFIX(hns3_logtype_init, init, NOTICE); +RTE_LOG_REGISTER_SUFFIX(hns3_logtype_driver, driver, NOTICE);