X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fhns3%2Fhns3_ethdev.h;h=575bacde090a7d4f6fa16fbb542f87d98ff29536;hb=23e317dd1fbf81bbfb542523e2628e8ed33654d1;hp=6e74ec87523300b7e71f968b842a72c03469f771;hpb=0f10bd6b1fb3d1981e9d4d82bb4473c75e634980;p=dpdk.git diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index 6e74ec8752..575bacde09 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -1,10 +1,11 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2018-2019 Hisilicon Limited. + * Copyright(c) 2018-2021 HiSilicon Limited. */ #ifndef _HNS3_ETHDEV_H_ #define _HNS3_ETHDEV_H_ +#include #include #include #include @@ -41,12 +42,18 @@ #define HNS3_PF_FUNC_ID 0 #define HNS3_1ST_VF_FUNC_ID 1 +#define HNS3_DEFAULT_PORT_CONF_BURST_SIZE 32 +#define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM 1 + #define HNS3_SW_SHIFT_AND_DISCARD_MODE 0 #define HNS3_HW_SHIFT_AND_DISCARD_MODE 1 #define HNS3_UNLIMIT_PROMISC_MODE 0 #define HNS3_LIMIT_PROMISC_MODE 1 +#define HNS3_SPECIAL_PORT_SW_CKSUM_MODE 0 +#define HNS3_SPECIAL_PORT_HW_CKSUM_MODE 1 + #define HNS3_UC_MACADDR_NUM 128 #define HNS3_VF_UC_MACADDR_NUM 48 #define HNS3_MC_MACADDR_NUM 128 @@ -148,7 +155,6 @@ struct hns3_tc_queue_info { }; struct hns3_cfg { - uint8_t vmdq_vport_num; uint8_t tc_num; uint16_t tqp_desc_num; uint16_t rx_buf_len; @@ -162,6 +168,12 @@ struct hns3_cfg { uint16_t umv_space; }; +struct hns3_set_link_speed_cfg { + uint32_t speed; + uint8_t duplex : 1; + uint8_t autoneg : 1; +}; + /* mac media type */ enum hns3_media_type { HNS3_MEDIA_TYPE_UNKNOWN, @@ -171,6 +183,9 @@ enum hns3_media_type { HNS3_MEDIA_TYPE_NONE, }; +#define HNS3_DEFAULT_QUERY 0 +#define HNS3_ACTIVE_QUERY 1 + struct hns3_mac { uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; bool default_addr_setted; /* whether default addr(mac_addr) is set */ @@ -180,10 +195,29 @@ struct hns3_mac { uint8_t link_autoneg : 1; /* ETH_LINK_[AUTONEG/FIXED] */ uint8_t link_status : 1; /* ETH_LINK_[DOWN/UP] */ uint32_t link_speed; /* ETH_SPEED_NUM_ */ - uint32_t supported_capa; /* supported capability for current media */ + /* + * Some firmware versions support only the SFP speed query. In addition + * to the SFP speed query, some firmware supports the query of the speed + * capability, auto-negotiation capability, and FEC mode, which can be + * selected by the 'query_type' filed in the HNS3_OPC_GET_SFP_INFO CMD. + * This field is used to record the SFP information query mode. + * Value range: + * HNS3_DEFAULT_QUERY/HNS3_ACTIVE_QUERY + * + * - HNS3_DEFAULT_QUERY + * Speed obtained is from SFP. When the queried speed changes, the MAC + * speed needs to be reconfigured. + * + * - HNS3_ACTIVE_QUERY + * Speed obtained is from MAC. At this time, it is unnecessary for + * driver to reconfigured the MAC speed. In addition, more information, + * such as, the speed capability, auto-negotiation capability and FEC + * mode, can be obtained by the HNS3_OPC_GET_SFP_INFO CMD. + */ + uint8_t query_type; + uint32_t supported_speed; /* supported speed for current media type */ uint32_t advertising; /* advertised capability in the local part */ - /* advertised capability in the link partner */ - uint32_t lp_advertising; + uint32_t lp_advertising; /* advertised capability in the link partner */ uint8_t support_autoneg; }; @@ -275,8 +309,9 @@ enum hns3_reset_stage { }; enum hns3_reset_level { - HNS3_NONE_RESET, + HNS3_FLR_RESET, /* A VF perform FLR reset */ HNS3_VF_FUNC_RESET, /* A VF function reset */ + /* * All VFs under a PF perform function reset. * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value @@ -284,6 +319,7 @@ enum hns3_reset_level { * same. */ HNS3_VF_PF_FUNC_RESET = 2, + /* * All VFs under a PF perform FLR reset. * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value @@ -297,14 +333,23 @@ enum hns3_reset_level { * In PF FLR, the register state of VF is not reliable, VF's driver * should not access the registers of the VF device. */ - HNS3_VF_FULL_RESET = 3, - HNS3_FLR_RESET, /* A VF perform FLR reset */ + HNS3_VF_FULL_RESET, + /* All VFs under the rootport perform a global or IMP reset */ HNS3_VF_RESET, - HNS3_FUNC_RESET, /* A PF function reset */ + + /* + * The enumeration value of HNS3_FUNC_RESET/HNS3_GLOBAL_RESET/ + * HNS3_IMP_RESET/HNS3_NONE_RESET are also used by firmware, and + * can not be changed. + */ + + HNS3_FUNC_RESET = 5, /* A PF function reset */ + /* All PFs under the rootport perform a global reset */ HNS3_GLOBAL_RESET, HNS3_IMP_RESET, /* All PFs under the rootport perform a IMP reset */ + HNS3_NONE_RESET, HNS3_MAX_RESET }; @@ -435,14 +480,13 @@ struct hns3_hw { uint8_t revision; /* PCI revision, low byte of class word */ struct hns3_cmq cmq; struct hns3_mbx_resp_status mbx_resp; /* mailbox response */ - struct hns3_mbx_arq_ring arq; /* mailbox async rx queue */ - pthread_t irq_thread_id; struct hns3_mac mac; unsigned int secondary_cnt; /* Number of secondary processes init'd. */ struct hns3_tqp_stats tqp_stats; /* Include Mac stats | Rx stats | Tx stats */ struct hns3_mac_stats mac_stats; struct hns3_rx_missed_stats imissed_stats; + uint64_t oerror_stats; uint32_t fw_version; uint16_t num_msi; @@ -467,8 +511,7 @@ struct hns3_hw { uint8_t num_tc; /* Total number of enabled TCs */ uint8_t hw_tc_map; - enum hns3_fc_mode current_mode; - enum hns3_fc_mode requested_mode; + enum hns3_fc_mode requested_fc_mode; /* FC mode requested by user */ struct hns3_dcb_info dcb_info; enum hns3_fc_status current_fc_status; /* current flow control status */ struct hns3_tc_queue_info tc_queue[HNS3_MAX_TC_NUM]; @@ -566,8 +609,27 @@ struct hns3_hw { uint8_t drop_stats_mode; uint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */ + /* + * udp checksum mode. + * value range: + * HNS3_SPECIAL_PORT_HW_CKSUM_MODE/HNS3_SPECIAL_PORT_SW_CKSUM_MODE + * + * - HNS3_SPECIAL_PORT_SW_CKSUM_MODE + * In this mode, HW can not do checksum for special UDP port like + * 4789, 4790, 6081 for non-tunnel UDP packets and UDP tunnel + * packets without the PKT_TX_TUNEL_MASK in the mbuf. So, PMD need + * do the checksum for these packets to avoid a checksum error. + * + * - HNS3_SPECIAL_PORT_HW_CKSUM_MODE + * In this mode, HW does not have the preceding problems and can + * directly calculate the checksum of these UDP packets. + */ + uint8_t udp_cksum_mode; struct hns3_port_base_vlan_config port_base_vlan_cfg; + + pthread_mutex_t flows_lock; /* rte_flow ops lock */ + /* * PMD setup and configuration is not thread safe. Since it is not * performance sensitive, it is better to guarantee thread-safety @@ -663,12 +725,10 @@ struct hns3_ptype_table { * The next fields used to calc packet-type by the * L3_ID/L4_ID/OL3_ID/OL4_ID from the Rx descriptor. */ - uint32_t l2l3table[HNS3_L2TBL_NUM][HNS3_L3TBL_NUM]; + uint32_t l3table[HNS3_L3TBL_NUM]; uint32_t l4table[HNS3_L4TBL_NUM]; - uint32_t inner_l2table[HNS3_L2TBL_NUM]; uint32_t inner_l3table[HNS3_L3TBL_NUM]; uint32_t inner_l4table[HNS3_L4TBL_NUM]; - uint32_t ol2table[HNS3_OL2TBL_NUM]; uint32_t ol3table[HNS3_OL3TBL_NUM]; uint32_t ol4table[HNS3_OL4TBL_NUM]; @@ -677,7 +737,7 @@ struct hns3_ptype_table { * descriptor, it functions only when firmware report the capability of * HNS3_CAPS_RXD_ADV_LAYOUT_B and driver enabled it. */ - uint32_t ptype[HNS3_PTYPE_NUM] __rte_cache_min_aligned; + uint32_t ptype[HNS3_PTYPE_NUM] __rte_cache_aligned; }; #define HNS3_FIXED_MAX_TQP_NUM_MODE 0 @@ -730,6 +790,11 @@ struct hns3_pf { bool support_sfp_query; uint32_t fec_mode; /* current FEC mode for ethdev */ + bool ptp_enable; + + /* Stores timestamp of last received packet on dev */ + uint64_t rx_timestamp; + struct hns3_vtag_cfg vtag_config; LIST_HEAD(vlan_tbl, hns3_user_vlan_table) vlan_list; @@ -739,8 +804,26 @@ struct hns3_pf { struct hns3_tm_conf tm_conf; }; +enum { + HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED, + HNS3_PF_PUSH_LSC_CAP_SUPPORTED, + HNS3_PF_PUSH_LSC_CAP_UNKNOWN +}; + struct hns3_vf { struct hns3_adapter *adapter; + + /* Whether PF support push link status change to VF */ + uint16_t pf_push_lsc_cap; + + /* + * If PF support push link status change, VF still need send request to + * get link status in some cases (such as reset recover stage), so use + * the req_link_info_cnt to control max request count. + */ + uint16_t req_link_info_cnt; + + uint16_t poll_job_started; /* whether poll job is started */ }; struct hns3_adapter { @@ -753,15 +836,12 @@ struct hns3_adapter { struct hns3_vf vf; }; - bool rx_simple_allowed; - bool rx_vec_allowed; - bool tx_simple_allowed; - bool tx_vec_allowed; - uint32_t rx_func_hint; uint32_t tx_func_hint; - struct hns3_ptype_table ptype_tbl __rte_cache_min_aligned; + uint64_t dev_caps_mask; + + struct hns3_ptype_table ptype_tbl __rte_cache_aligned; }; enum { @@ -775,16 +855,20 @@ enum { #define HNS3_DEVARG_RX_FUNC_HINT "rx_func_hint" #define HNS3_DEVARG_TX_FUNC_HINT "tx_func_hint" -#define HNS3_DEV_SUPPORT_DCB_B 0x0 -#define HNS3_DEV_SUPPORT_COPPER_B 0x1 -#define HNS3_DEV_SUPPORT_UDP_GSO_B 0x2 -#define HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B 0x3 -#define HNS3_DEV_SUPPORT_PTP_B 0x4 -#define HNS3_DEV_SUPPORT_TX_PUSH_B 0x5 -#define HNS3_DEV_SUPPORT_INDEP_TXRX_B 0x6 -#define HNS3_DEV_SUPPORT_STASH_B 0x7 -#define HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B 0x9 -#define HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B 0xA +#define HNS3_DEVARG_DEV_CAPS_MASK "dev_caps_mask" + +enum { + HNS3_DEV_SUPPORT_DCB_B, + HNS3_DEV_SUPPORT_COPPER_B, + HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B, + HNS3_DEV_SUPPORT_PTP_B, + HNS3_DEV_SUPPORT_TX_PUSH_B, + HNS3_DEV_SUPPORT_INDEP_TXRX_B, + HNS3_DEV_SUPPORT_STASH_B, + HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, + HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B, + HNS3_DEV_SUPPORT_RAS_IMP_B, +}; #define hns3_dev_dcb_supported(hw) \ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B) @@ -793,10 +877,6 @@ enum { #define hns3_dev_copper_supported(hw) \ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_COPPER_B) -/* Support UDP GSO offload */ -#define hns3_dev_udp_gso_supported(hw) \ - hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_UDP_GSO_B) - /* Support the queue region action rule of flow directory */ #define hns3_dev_fd_queue_region_supported(hw) \ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B) @@ -805,9 +885,6 @@ enum { #define hns3_dev_ptp_supported(hw) \ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_PTP_B) -#define hns3_dev_tx_push_supported(hw) \ - hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_TX_PUSH_B) - /* Support to Independently enable/disable/reset Tx or Rx queues */ #define hns3_dev_indep_txrx_supported(hw) \ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_INDEP_TXRX_B) @@ -821,10 +898,18 @@ enum { #define hns3_dev_outer_udp_cksum_supported(hw) \ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B) +#define hns3_dev_ras_imp_supported(hw) \ + hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_RAS_IMP_B) + +#define hns3_dev_tx_push_supported(hw) \ + hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_TX_PUSH_B) + #define HNS3_DEV_PRIVATE_TO_HW(adapter) \ (&((struct hns3_adapter *)adapter)->hw) #define HNS3_DEV_PRIVATE_TO_PF(adapter) \ (&((struct hns3_adapter *)adapter)->pf) +#define HNS3_DEV_PRIVATE_TO_VF(adapter) \ + (&((struct hns3_adapter *)adapter)->vf) #define HNS3_DEV_HW_TO_ADAPTER(hw) \ container_of(hw, struct hns3_adapter, hw) @@ -834,6 +919,12 @@ static inline struct hns3_pf *HNS3_DEV_HW_TO_PF(struct hns3_hw *hw) return &adapter->pf; } +static inline struct hns3_vf *HNS3_DEV_HW_TO_VF(struct hns3_hw *hw) +{ + struct hns3_adapter *adapter = HNS3_DEV_HW_TO_ADAPTER(hw); + return &adapter->vf; +} + #define hns3_set_field(origin, mask, shift, val) \ do { \ (origin) &= (~(mask)); \ @@ -892,13 +983,13 @@ static inline void hns3_write_reg(void *base, uint32_t reg, uint32_t value) } /* - * The optimized function for writing registers used in the '.rx_pkt_burst' and - * '.tx_pkt_burst' ops implementation function. + * The optimized function for writing registers reduces one address addition + * calculation, it was used in the '.rx_pkt_burst' and '.tx_pkt_burst' ops + * implementation function. */ static inline void hns3_write_reg_opt(volatile void *addr, uint32_t value) { - rte_io_wmb(); - rte_write32_relaxed(rte_cpu_to_le_32(value), addr); + rte_write32(rte_cpu_to_le_32(value), addr); } static inline uint32_t hns3_read_reg(void *base, uint32_t reg) @@ -913,8 +1004,6 @@ static inline uint32_t hns3_read_reg(void *base, uint32_t reg) #define hns3_read_dev(a, reg) \ hns3_read_reg((a)->io_base, (reg)) -#define ARRAY_SIZE(x) RTE_DIM(x) - #define NEXT_ITEM_OF_ACTION(act, actions, index) \ do { \ act = (actions) + (index); \ @@ -927,15 +1016,9 @@ static inline uint32_t hns3_read_reg(void *base, uint32_t reg) #define MSEC_PER_SEC 1000L #define USEC_PER_MSEC 1000L -static inline uint64_t -get_timeofday_ms(void) -{ - struct timeval tv; - - (void)gettimeofday(&tv, NULL); - - return (uint64_t)tv.tv_sec * MSEC_PER_SEC + tv.tv_usec / USEC_PER_MSEC; -} +void hns3_clock_gettime(struct timeval *tv); +uint64_t hns3_clock_calctime_ms(struct timeval *tv); +uint64_t hns3_clock_gettime_ms(void); static inline uint64_t hns3_atomic_test_bit(unsigned int nr, volatile uint64_t *addr) @@ -967,12 +1050,11 @@ hns3_test_and_clear_bit(unsigned int nr, volatile uint64_t *addr) } int hns3_buffer_alloc(struct hns3_hw *hw); -int hns3_dev_filter_ctrl(struct rte_eth_dev *dev, - enum rte_filter_type filter_type, - enum rte_filter_op filter_op, void *arg); +int hns3_dev_flow_ops_get(struct rte_eth_dev *dev, + const struct rte_flow_ops **ops); bool hns3_is_reset_pending(struct hns3_adapter *hns); bool hns3vf_is_reset_pending(struct hns3_adapter *hns); -void hns3_update_link_status_and_event(struct hns3_hw *hw); +void hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query); void hns3_ether_format_addr(char *buf, uint16_t size, const struct rte_ether_addr *ether_addr); int hns3_dev_infos_get(struct rte_eth_dev *eth_dev, @@ -980,6 +1062,22 @@ int hns3_dev_infos_get(struct rte_eth_dev *eth_dev, void hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status, uint32_t link_speed, uint8_t link_duplex); void hns3_parse_devargs(struct rte_eth_dev *dev); +void hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported); +int hns3_restore_ptp(struct hns3_adapter *hns); +int hns3_mbuf_dyn_rx_timestamp_register(struct rte_eth_dev *dev, + struct rte_eth_conf *conf); +int hns3_ptp_init(struct hns3_hw *hw); +int hns3_timesync_enable(struct rte_eth_dev *dev); +int hns3_timesync_disable(struct rte_eth_dev *dev); +int hns3_timesync_read_rx_timestamp(struct rte_eth_dev *dev, + struct timespec *timestamp, + uint32_t flags __rte_unused); +int hns3_timesync_read_tx_timestamp(struct rte_eth_dev *dev, + struct timespec *timestamp); +int hns3_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts); +int hns3_timesync_write_time(struct rte_eth_dev *dev, + const struct timespec *ts); +int hns3_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); static inline bool is_reset_pending(struct hns3_adapter *hns)