X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fhns3%2Fhns3_ethdev.h;h=932600d05b20a8cda2dd89296cc4f19a69beae61;hb=2b6d6d71a0992220043b2f5c3b885c486e7921b7;hp=ef85034fe73813c1a9a10965277bfe03c0b18832;hpb=7ef933908f04983ce6e8d1a930d59263b84d0485;p=dpdk.git diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index ef85034fe7..932600d05b 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -6,13 +6,17 @@ #define _HNS3_ETHDEV_H_ #include -#include +#include +#include +#include +#include #include "hns3_cmd.h" #include "hns3_mbx.h" #include "hns3_rss.h" #include "hns3_fdir.h" #include "hns3_stats.h" +#include "hns3_tm.h" /* Vendor ID */ #define PCI_VENDOR_ID_HUAWEI 0x19e5 @@ -37,6 +41,12 @@ #define HNS3_PF_FUNC_ID 0 #define HNS3_1ST_VF_FUNC_ID 1 +#define HNS3_SW_SHIFT_AND_DISCARD_MODE 0 +#define HNS3_HW_SHIFT_AND_DISCARD_MODE 1 + +#define HNS3_UNLIMIT_PROMISC_MODE 0 +#define HNS3_LIMIT_PROMISC_MODE 1 + #define HNS3_UC_MACADDR_NUM 128 #define HNS3_VF_UC_MACADDR_NUM 48 #define HNS3_MC_MACADDR_NUM 128 @@ -61,6 +71,8 @@ #define HNS3_HIP08_MIN_TX_PKT_LEN 33 #define HNS3_HIP09_MIN_TX_PKT_LEN 9 +#define HNS3_BITS_PER_BYTE 8 + #define HNS3_4_TCS 4 #define HNS3_8_TCS 8 @@ -129,9 +141,9 @@ enum hns3_fc_status { }; struct hns3_tc_queue_info { - uint8_t tqp_offset; /* TQP offset from base TQP */ - uint8_t tqp_count; /* Total TQPs */ - uint8_t tc; /* TC index */ + uint16_t tqp_offset; /* TQP offset from base TQP */ + uint16_t tqp_count; /* Total TQPs */ + uint8_t tc; /* TC index */ bool enable; /* If this TC is enable or not */ }; @@ -161,13 +173,18 @@ enum hns3_media_type { struct hns3_mac { uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; - bool default_addr_setted; /* whether default addr(mac_addr) is setted */ + bool default_addr_setted; /* whether default addr(mac_addr) is set */ uint8_t media_type; uint8_t phy_addr; uint8_t link_duplex : 1; /* ETH_LINK_[HALF/FULL]_DUPLEX */ uint8_t link_autoneg : 1; /* ETH_LINK_[AUTONEG/FIXED] */ uint8_t link_status : 1; /* ETH_LINK_[DOWN/UP] */ uint32_t link_speed; /* ETH_SPEED_NUM_ */ + uint32_t supported_capa; /* supported capability for current media */ + uint32_t advertising; /* advertised capability in the local part */ + /* advertised capability in the link partner */ + uint32_t lp_advertising; + uint8_t support_autoneg; }; struct hns3_fake_queue_data { @@ -272,6 +289,13 @@ enum hns3_reset_level { * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value * of the reset level and the one defined in kernel driver should be * same. + * + * According to the protocol of PCIe, FLR to a PF resets the PF state as + * well as the SR-IOV extended capability including VF Enable which + * means that VFs no longer exist. + * + * In PF FLR, the register state of VF is not reliable, VF's driver + * should not access the registers of the VF device. */ HNS3_VF_FULL_RESET = 3, HNS3_FLR_RESET, /* A VF perform FLR reset */ @@ -333,11 +357,11 @@ enum hns3_schedule { struct hns3_reset_data { enum hns3_reset_stage stage; - rte_atomic16_t schedule; + uint16_t schedule; /* Reset flag, covering the entire reset process */ - rte_atomic16_t resetting; + uint16_t resetting; /* Used to disable sending cmds during reset */ - rte_atomic16_t disable_cmd; + uint16_t disable_cmd; /* The reset level being processed */ enum hns3_reset_level level; /* Reset level set, each bit represents a reset level */ @@ -363,12 +387,11 @@ struct hns3_reset_data { #define HNS3_INTR_MAPPING_VEC_RSV_ONE 0 #define HNS3_INTR_MAPPING_VEC_ALL 1 -#define HNS3_INTR_COALESCE_NON_QL 0 -#define HNS3_INTR_COALESCE_QL 1 - #define HNS3_INTR_COALESCE_GL_UINT_2US 0 #define HNS3_INTR_COALESCE_GL_UINT_1US 1 +#define HNS3_INTR_QL_NONE 0 + struct hns3_queue_intr { /* * interrupt mapping mode. @@ -389,21 +412,6 @@ struct hns3_queue_intr { * Rx interrupt in enabled. */ uint8_t mapping_mode; - /* - * interrupt coalesce mode. - * value range: - * HNS3_INTR_COALESCE_NON_QL/HNS3_INTR_COALESCE_QL - * - * - HNS3_INTR_COALESCE_NON_QL - * For some versions of hardware network engine, hardware doesn't - * support QL(quanity limiter) algorithm for interrupt coalesce - * of queue's interrupt. - * - * - HNS3_INTR_COALESCE_QL - * In this mode, hardware support QL(quanity limiter) algorithm for - * interrupt coalesce of queue's interrupt. - */ - uint8_t coalesce_mode; /* * The unit of GL(gap limiter) configuration for interrupt coalesce of * queue's interrupt. @@ -411,8 +419,13 @@ struct hns3_queue_intr { * HNS3_INTR_COALESCE_GL_UINT_2US/HNS3_INTR_COALESCE_GL_UINT_1US */ uint8_t gl_unit; + /* The max QL(quantity limiter) value */ + uint16_t int_ql_max; }; +#define HNS3_TSO_SW_CAL_PSEUDO_H_CSUM 0 +#define HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 1 + struct hns3_hw { struct rte_eth_dev_data *data; void *io_base; @@ -426,6 +439,7 @@ struct hns3_hw { struct hns3_tqp_stats tqp_stats; /* Include Mac stats | Rx stats | Tx stats */ struct hns3_mac_stats mac_stats; + struct hns3_rx_missed_stats imissed_stats; uint32_t fw_version; uint16_t num_msi; @@ -473,7 +487,63 @@ struct hns3_hw { uint32_t min_tx_pkt_len; struct hns3_queue_intr intr; - + /* + * tso mode. + * value range: + * HNS3_TSO_SW_CAL_PSEUDO_H_CSUM/HNS3_TSO_HW_CAL_PSEUDO_H_CSUM + * + * - HNS3_TSO_SW_CAL_PSEUDO_H_CSUM + * In this mode, because of the hardware constraint, network driver + * software need erase the L4 len value of the TCP pseudo header + * and recalculate the TCP pseudo header checksum of packets that + * need TSO. + * + * - HNS3_TSO_HW_CAL_PSEUDO_H_CSUM + * In this mode, hardware support recalculate the TCP pseudo header + * checksum of packets that need TSO, so network driver software + * not need to recalculate it. + */ + uint8_t tso_mode; + /* + * vlan mode. + * value range: + * HNS3_SW_SHIFT_AND_DISCARD_MODE/HNS3_HW_SHFIT_AND_DISCARD_MODE + * + * - HNS3_SW_SHIFT_AND_DISCARD_MODE + * For some versions of hardware network engine, because of the + * hardware limitation, PMD driver needs to detect the PVID status + * to work with haredware to implement PVID-related functions. + * For example, driver need discard the stripped PVID tag to ensure + * the PVID will not report to mbuf and shift the inserted VLAN tag + * to avoid port based VLAN covering it. + * + * - HNS3_HW_SHIT_AND_DISCARD_MODE + * PMD driver does not need to process PVID-related functions in + * I/O process, Hardware will adjust the sequence between port based + * VLAN tag and BD VLAN tag automatically and VLAN tag stripped by + * PVID will be invisible to driver. And in this mode, hns3 is able + * to send a multi-layer VLAN packets when hw VLAN insert offload + * is enabled. + */ + uint8_t vlan_mode; + /* + * promisc mode. + * value range: + * HNS3_UNLIMIT_PROMISC_MODE/HNS3_LIMIT_PROMISC_MODE + * + * - HNS3_UNLIMIT_PROMISC_MODE + * In this mode, TX unicast promisc will be configured when promisc + * is set, driver can receive all the ingress and outgoing traffic. + * In the words, all the ingress packets, all the packets sent from + * the PF and other VFs on the same physical port. + * + * - HNS3_LIMIT_PROMISC_MODE + * In this mode, TX unicast promisc is shutdown when promisc mode + * is set. So, driver will only receive all the ingress traffic. + * The packets sent from the PF and other VFs on the same physical + * port won't be copied to the function which has set promisc mode. + */ + uint8_t promisc_mode; uint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */ struct hns3_port_base_vlan_config port_base_vlan_cfg; @@ -532,11 +602,21 @@ struct hns3_user_vlan_table { /* Vlan tag configuration for RX direction */ struct hns3_rx_vtag_cfg { - uint8_t rx_vlan_offload_en; /* Whether enable rx vlan offload */ - uint8_t strip_tag1_en; /* Whether strip inner vlan tag */ - uint8_t strip_tag2_en; /* Whether strip outer vlan tag */ - uint8_t vlan1_vlan_prionly; /* Inner VLAN Tag up to descriptor Enable */ - uint8_t vlan2_vlan_prionly; /* Outer VLAN Tag up to descriptor Enable */ + bool rx_vlan_offload_en; /* Whether enable rx vlan offload */ + bool strip_tag1_en; /* Whether strip inner vlan tag */ + bool strip_tag2_en; /* Whether strip outer vlan tag */ + /* + * If strip_tag_en is enabled, this bit decide whether to map the vlan + * tag to descriptor. + */ + bool strip_tag1_discard_en; + bool strip_tag2_discard_en; + /* + * If this bit is enabled, only map inner/outer priority to descriptor + * and the vlan tag is always 0. + */ + bool vlan1_vlan_prionly; + bool vlan2_vlan_prionly; }; /* Vlan tag configuration for TX direction */ @@ -545,10 +625,15 @@ struct hns3_tx_vtag_cfg { bool accept_untag1; /* Whether accept untag1 packet from host */ bool accept_tag2; bool accept_untag2; - bool insert_tag1_en; /* Whether insert inner vlan tag */ - bool insert_tag2_en; /* Whether insert outer vlan tag */ - uint16_t default_tag1; /* The default inner vlan tag to insert */ - uint16_t default_tag2; /* The default outer vlan tag to insert */ + bool insert_tag1_en; /* Whether insert outer vlan tag */ + bool insert_tag2_en; /* Whether insert inner vlan tag */ + /* + * In shift mode, hw will shift the sequence of port based VLAN and + * BD VLAN. + */ + bool tag_shift_mode_en; /* hw shift vlan tag automatically */ + uint16_t default_tag1; /* The default outer vlan tag to insert */ + uint16_t default_tag2; /* The default inner vlan tag to insert */ }; struct hns3_vtag_cfg { @@ -579,25 +664,62 @@ struct hns3_mp_param { #define HNS3_L2TBL_NUM 4 #define HNS3_L3TBL_NUM 16 #define HNS3_L4TBL_NUM 16 +#define HNS3_OL2TBL_NUM 4 #define HNS3_OL3TBL_NUM 16 #define HNS3_OL4TBL_NUM 16 +#define HNS3_PTYPE_NUM 256 struct hns3_ptype_table { - uint32_t l2table[HNS3_L2TBL_NUM]; - uint32_t l3table[HNS3_L3TBL_NUM]; + /* + * The next fields used to calc packet-type by the + * L3_ID/L4_ID/OL3_ID/OL4_ID from the Rx descriptor. + */ + uint32_t l2l3table[HNS3_L2TBL_NUM][HNS3_L3TBL_NUM]; uint32_t l4table[HNS3_L4TBL_NUM]; uint32_t inner_l2table[HNS3_L2TBL_NUM]; uint32_t inner_l3table[HNS3_L3TBL_NUM]; uint32_t inner_l4table[HNS3_L4TBL_NUM]; + uint32_t ol2table[HNS3_OL2TBL_NUM]; uint32_t ol3table[HNS3_OL3TBL_NUM]; uint32_t ol4table[HNS3_OL4TBL_NUM]; + + /* + * The next field used to calc packet-type by the PTYPE from the Rx + * descriptor, it functions only when firmware report the capability of + * HNS3_CAPS_RXD_ADV_LAYOUT_B and driver enabled it. + */ + uint32_t ptype[HNS3_PTYPE_NUM] __rte_cache_min_aligned; }; +#define HNS3_FIXED_MAX_TQP_NUM_MODE 0 +#define HNS3_FLEX_MAX_TQP_NUM_MODE 1 + struct hns3_pf { struct hns3_adapter *adapter; bool is_main_pf; uint16_t func_num; /* num functions of this pf, include pf and vfs */ + /* + * tqp_config mode + * tqp_config_mode value range: + * HNS3_FIXED_MAX_TQP_NUM_MODE, + * HNS3_FLEX_MAX_TQP_NUM_MODE + * + * - HNS3_FIXED_MAX_TQP_NUM_MODE + * There is a limitation on the number of pf interrupts available for + * on some versions of network engines. In this case, the maximum + * queue number of pf can not be greater than the interrupt number, + * such as pf of network engine with revision_id 0x21. So the maximum + * number of queues must be fixed. + * + * - HNS3_FLEX_MAX_TQP_NUM_MODE + * In this mode, the maximum queue number of pf has not any constraint + * and comes from the macro RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF + * in the config file. Users can modify the macro according to their + * own application scenarios, which is more flexible to use. + */ + uint8_t tqp_config_mode; + uint32_t pkt_buf_size; /* Total pf buf size for tx/rx */ uint32_t tx_buf_size; /* Tx buffer size for each TC */ uint32_t dv_buf_size; /* Dv buffer size for each TC */ @@ -620,12 +742,15 @@ struct hns3_pf { struct hns3_err_msix_intr_stats abn_int_stats; bool support_sfp_query; + uint32_t fec_mode; /* current FEC mode for ethdev */ struct hns3_vtag_cfg vtag_config; LIST_HEAD(vlan_tbl, hns3_user_vlan_table) vlan_list; struct hns3_fdir_info fdir; /* flow director info */ LIST_HEAD(counters, hns3_flow_counter) flow_counters; + + struct hns3_tm_conf tm_conf; }; struct hns3_vf { @@ -643,18 +768,22 @@ struct hns3_adapter { }; bool rx_simple_allowed; + bool rx_vec_allowed; bool tx_simple_allowed; + bool tx_vec_allowed; + struct hns3_ptype_table ptype_tbl __rte_cache_min_aligned; }; #define HNS3_DEV_SUPPORT_DCB_B 0x0 #define HNS3_DEV_SUPPORT_COPPER_B 0x1 #define HNS3_DEV_SUPPORT_UDP_GSO_B 0x2 -#define HNS3_DEV_SUPPORT_ADQ_B 0x3 +#define HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B 0x3 #define HNS3_DEV_SUPPORT_PTP_B 0x4 #define HNS3_DEV_SUPPORT_TX_PUSH_B 0x5 #define HNS3_DEV_SUPPORT_INDEP_TXRX_B 0x6 #define HNS3_DEV_SUPPORT_STASH_B 0x7 +#define HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B 0x9 #define hns3_dev_dcb_supported(hw) \ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B) @@ -667,9 +796,9 @@ struct hns3_adapter { #define hns3_dev_udp_gso_supported(hw) \ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_UDP_GSO_B) -/* Support Application Device Queue */ -#define hns3_dev_adq_supported(hw) \ - hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_ADQ_B) +/* Support the queue region action rule of flow directory */ +#define hns3_dev_fd_queue_region_supported(hw) \ + hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B) /* Support PTP timestamp offload */ #define hns3_dev_ptp_supported(hw) \ @@ -685,17 +814,22 @@ struct hns3_adapter { #define hns3_dev_stash_supported(hw) \ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_STASH_B) +#define hns3_dev_rxd_adv_layout_supported(hw) \ + hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B) + #define HNS3_DEV_PRIVATE_TO_HW(adapter) \ (&((struct hns3_adapter *)adapter)->hw) -#define HNS3_DEV_PRIVATE_TO_ADAPTER(adapter) \ - ((struct hns3_adapter *)adapter) #define HNS3_DEV_PRIVATE_TO_PF(adapter) \ (&((struct hns3_adapter *)adapter)->pf) -#define HNS3VF_DEV_PRIVATE_TO_VF(adapter) \ - (&((struct hns3_adapter *)adapter)->vf) #define HNS3_DEV_HW_TO_ADAPTER(hw) \ container_of(hw, struct hns3_adapter, hw) +static inline struct hns3_pf *HNS3_DEV_HW_TO_PF(struct hns3_hw *hw) +{ + struct hns3_adapter *adapter = HNS3_DEV_HW_TO_ADAPTER(hw); + return &adapter->pf; +} + #define hns3_set_field(origin, mask, shift, val) \ do { \ (origin) &= (~(mask)); \ @@ -708,6 +842,8 @@ struct hns3_adapter { #define hns3_get_bit(origin, shift) \ hns3_get_field((origin), (0x1UL << (shift)), (shift)) +#define hns3_gen_field_val(mask, shift, val) (((val) << (shift)) & (mask)) + /* * upper_32_bits - return bits 32-63 of a number * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress @@ -721,6 +857,8 @@ struct hns3_adapter { #define BIT(nr) (1UL << (nr)) +#define BIT_ULL(x) (1ULL << (x)) + #define BITS_PER_LONG (__SIZEOF_LONG__ * 8) #define GENMASK(h, l) \ (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) @@ -771,7 +909,7 @@ static inline uint32_t hns3_read_reg(void *base, uint32_t reg) #define hns3_read_dev(a, reg) \ hns3_read_reg((a)->io_base, (reg)) -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#define ARRAY_SIZE(x) RTE_DIM(x) #define NEXT_ITEM_OF_ACTION(act, actions, index) \ do { \ @@ -830,7 +968,13 @@ int hns3_dev_filter_ctrl(struct rte_eth_dev *dev, enum rte_filter_op filter_op, void *arg); bool hns3_is_reset_pending(struct hns3_adapter *hns); bool hns3vf_is_reset_pending(struct hns3_adapter *hns); -void hns3_update_link_status(struct hns3_hw *hw); +void hns3_update_link_status_and_event(struct hns3_hw *hw); +void hns3_ether_format_addr(char *buf, uint16_t size, + const struct rte_ether_addr *ether_addr); +int hns3_dev_infos_get(struct rte_eth_dev *eth_dev, + struct rte_eth_dev_info *info); +void hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status, + uint32_t link_speed, uint8_t link_duplex); static inline bool is_reset_pending(struct hns3_adapter *hns)