X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fhns3%2Fhns3_ethdev.h;h=a6622a66bfc4f90cb456ba9c23fc805f9ddff116;hb=77d1f6b1afc8a685c5685141e14d866fe2434e99;hp=c7625119a2c71cb5ab117f865169edf17867d391;hpb=6dca716c9e1daa8ea770a4a198bd068e72a2e03c;p=dpdk.git diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index c7625119a2..a6622a66bf 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -1,18 +1,23 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2018-2019 Hisilicon Limited. + * Copyright(c) 2018-2021 HiSilicon Limited. */ #ifndef _HNS3_ETHDEV_H_ #define _HNS3_ETHDEV_H_ +#include #include -#include +#include +#include +#include +#include #include "hns3_cmd.h" #include "hns3_mbx.h" #include "hns3_rss.h" #include "hns3_fdir.h" #include "hns3_stats.h" +#include "hns3_tm.h" /* Vendor ID */ #define PCI_VENDOR_ID_HUAWEI 0x19e5 @@ -23,9 +28,32 @@ #define HNS3_DEV_ID_25GE_RDMA 0xA222 #define HNS3_DEV_ID_50GE_RDMA 0xA224 #define HNS3_DEV_ID_100G_RDMA_MACSEC 0xA226 +#define HNS3_DEV_ID_200G_RDMA 0xA228 #define HNS3_DEV_ID_100G_VF 0xA22E #define HNS3_DEV_ID_100G_RDMA_PFC_VF 0xA22F +/* PCI Config offsets */ +#define HNS3_PCI_REVISION_ID 0x08 +#define HNS3_PCI_REVISION_ID_LEN 1 + +#define PCI_REVISION_ID_HIP08_B 0x21 +#define PCI_REVISION_ID_HIP09_A 0x30 + +#define HNS3_PF_FUNC_ID 0 +#define HNS3_1ST_VF_FUNC_ID 1 + +#define HNS3_DEFAULT_PORT_CONF_BURST_SIZE 32 +#define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM 1 + +#define HNS3_SW_SHIFT_AND_DISCARD_MODE 0 +#define HNS3_HW_SHIFT_AND_DISCARD_MODE 1 + +#define HNS3_UNLIMIT_PROMISC_MODE 0 +#define HNS3_LIMIT_PROMISC_MODE 1 + +#define HNS3_SPECIAL_PORT_SW_CKSUM_MODE 0 +#define HNS3_SPECIAL_PORT_HW_CKSUM_MODE 1 + #define HNS3_UC_MACADDR_NUM 128 #define HNS3_VF_UC_MACADDR_NUM 48 #define HNS3_MC_MACADDR_NUM 128 @@ -39,6 +67,7 @@ #define HNS3_MAX_BD_PAYLEN (1024 * 1024 - 1) #define HNS3_MAX_TSO_HDR_SIZE 512 #define HNS3_MAX_TSO_HDR_BD_NUM 3 +#define HNS3_MAX_LRO_SIZE 64512 #define HNS3_ETH_OVERHEAD \ (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + HNS3_VLAN_TAG_SIZE * 2) @@ -46,7 +75,10 @@ #define HNS3_MAX_MTU (HNS3_MAX_FRAME_LEN - HNS3_ETH_OVERHEAD) #define HNS3_DEFAULT_MTU 1500UL #define HNS3_DEFAULT_FRAME_LEN (HNS3_DEFAULT_MTU + HNS3_ETH_OVERHEAD) -#define HNS3_MIN_PKT_SIZE 60 +#define HNS3_HIP08_MIN_TX_PKT_LEN 33 +#define HNS3_HIP09_MIN_TX_PKT_LEN 9 + +#define HNS3_BITS_PER_BYTE 8 #define HNS3_4_TCS 4 #define HNS3_8_TCS 8 @@ -116,9 +148,9 @@ enum hns3_fc_status { }; struct hns3_tc_queue_info { - uint8_t tqp_offset; /* TQP offset from base TQP */ - uint8_t tqp_count; /* Total TQPs */ - uint8_t tc; /* TC index */ + uint16_t tqp_offset; /* TQP offset from base TQP */ + uint16_t tqp_count; /* Total TQPs */ + uint8_t tc; /* TC index */ bool enable; /* If this TC is enable or not */ }; @@ -137,6 +169,12 @@ struct hns3_cfg { uint16_t umv_space; }; +struct hns3_set_link_speed_cfg { + uint32_t speed; + uint8_t duplex : 1; + uint8_t autoneg : 1; +}; + /* mac media type */ enum hns3_media_type { HNS3_MEDIA_TYPE_UNKNOWN, @@ -146,15 +184,42 @@ enum hns3_media_type { HNS3_MEDIA_TYPE_NONE, }; +#define HNS3_DEFAULT_QUERY 0 +#define HNS3_ACTIVE_QUERY 1 + struct hns3_mac { uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; - bool default_addr_setted; /* whether default addr(mac_addr) is setted */ + bool default_addr_setted; /* whether default addr(mac_addr) is set */ uint8_t media_type; uint8_t phy_addr; uint8_t link_duplex : 1; /* ETH_LINK_[HALF/FULL]_DUPLEX */ uint8_t link_autoneg : 1; /* ETH_LINK_[AUTONEG/FIXED] */ uint8_t link_status : 1; /* ETH_LINK_[DOWN/UP] */ uint32_t link_speed; /* ETH_SPEED_NUM_ */ + /* + * Some firmware versions support only the SFP speed query. In addition + * to the SFP speed query, some firmware supports the query of the speed + * capability, auto-negotiation capability, and FEC mode, which can be + * selected by the 'query_type' filed in the HNS3_OPC_GET_SFP_INFO CMD. + * This field is used to record the SFP information query mode. + * Value range: + * HNS3_DEFAULT_QUERY/HNS3_ACTIVE_QUERY + * + * - HNS3_DEFAULT_QUERY + * Speed obtained is from SFP. When the queried speed changes, the MAC + * speed needs to be reconfigured. + * + * - HNS3_ACTIVE_QUERY + * Speed obtained is from MAC. At this time, it is unnecessary for + * driver to reconfigured the MAC speed. In addition, more information, + * such as, the speed capability, auto-negotiation capability and FEC + * mode, can be obtained by the HNS3_OPC_GET_SFP_INFO CMD. + */ + uint8_t query_type; + uint32_t supported_speed; /* supported speed for current media type */ + uint32_t advertising; /* advertised capability in the local part */ + uint32_t lp_advertising; /* advertised capability in the link partner */ + uint8_t support_autoneg; }; struct hns3_fake_queue_data { @@ -164,6 +229,13 @@ struct hns3_fake_queue_data { uint16_t nb_fake_tx_queues; /* Number of fake TX queues. */ }; +#define HNS3_PORT_BASE_VLAN_DISABLE 0 +#define HNS3_PORT_BASE_VLAN_ENABLE 1 +struct hns3_port_base_vlan_config { + uint16_t state; + uint16_t pvid; +}; + /* Primary process maintains driver state in main thread. * * +---------------+ @@ -238,8 +310,9 @@ enum hns3_reset_stage { }; enum hns3_reset_level { - HNS3_NONE_RESET, + HNS3_FLR_RESET, /* A VF perform FLR reset */ HNS3_VF_FUNC_RESET, /* A VF function reset */ + /* * All VFs under a PF perform function reset. * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value @@ -247,20 +320,37 @@ enum hns3_reset_level { * same. */ HNS3_VF_PF_FUNC_RESET = 2, + /* * All VFs under a PF perform FLR reset. * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value * of the reset level and the one defined in kernel driver should be * same. + * + * According to the protocol of PCIe, FLR to a PF resets the PF state as + * well as the SR-IOV extended capability including VF Enable which + * means that VFs no longer exist. + * + * In PF FLR, the register state of VF is not reliable, VF's driver + * should not access the registers of the VF device. */ - HNS3_VF_FULL_RESET = 3, - HNS3_FLR_RESET, /* A VF perform FLR reset */ + HNS3_VF_FULL_RESET, + /* All VFs under the rootport perform a global or IMP reset */ HNS3_VF_RESET, - HNS3_FUNC_RESET, /* A PF function reset */ + + /* + * The enumeration value of HNS3_FUNC_RESET/HNS3_GLOBAL_RESET/ + * HNS3_IMP_RESET/HNS3_NONE_RESET are also used by firmware, and + * can not be changed. + */ + + HNS3_FUNC_RESET = 5, /* A PF function reset */ + /* All PFs under the rootport perform a global reset */ HNS3_GLOBAL_RESET, HNS3_IMP_RESET, /* All PFs under the rootport perform a IMP reset */ + HNS3_NONE_RESET, HNS3_MAX_RESET }; @@ -313,11 +403,11 @@ enum hns3_schedule { struct hns3_reset_data { enum hns3_reset_stage stage; - rte_atomic16_t schedule; + uint16_t schedule; /* Reset flag, covering the entire reset process */ - rte_atomic16_t resetting; + uint16_t resetting; /* Used to disable sending cmds during reset */ - rte_atomic16_t disable_cmd; + uint16_t disable_cmd; /* The reset level being processed */ enum hns3_reset_level level; /* Reset level set, each bit represents a reset level */ @@ -340,38 +430,89 @@ struct hns3_reset_data { struct hns3_wait_data *wait_data; }; +#define HNS3_INTR_MAPPING_VEC_RSV_ONE 0 +#define HNS3_INTR_MAPPING_VEC_ALL 1 + +#define HNS3_INTR_COALESCE_GL_UINT_2US 0 +#define HNS3_INTR_COALESCE_GL_UINT_1US 1 + +#define HNS3_INTR_QL_NONE 0 + +struct hns3_queue_intr { + /* + * interrupt mapping mode. + * value range: + * HNS3_INTR_MAPPING_VEC_RSV_ONE/HNS3_INTR_MAPPING_VEC_ALL + * + * - HNS3_INTR_MAPPING_VEC_RSV_ONE + * For some versions of hardware network engine, because of the + * hardware constraint, we need implement clearing the mapping + * relationship configurations by binding all queues to the last + * interrupt vector and reserving the last interrupt vector. This + * method results in a decrease of the maximum queues when upper + * applications call the rte_eth_dev_configure API function to + * enable Rx interrupt. + * + * - HNS3_INTR_MAPPING_VEC_ALL + * PMD driver can map/unmmap all interrupt vectors with queues When + * Rx interrupt in enabled. + */ + uint8_t mapping_mode; + /* + * The unit of GL(gap limiter) configuration for interrupt coalesce of + * queue's interrupt. + * value range: + * HNS3_INTR_COALESCE_GL_UINT_2US/HNS3_INTR_COALESCE_GL_UINT_1US + */ + uint8_t gl_unit; + /* The max QL(quantity limiter) value */ + uint16_t int_ql_max; +}; + +#define HNS3_TSO_SW_CAL_PSEUDO_H_CSUM 0 +#define HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 1 + +#define HNS3_PKTS_DROP_STATS_MODE1 0 +#define HNS3_PKTS_DROP_STATS_MODE2 1 + struct hns3_hw { struct rte_eth_dev_data *data; void *io_base; + uint8_t revision; /* PCI revision, low byte of class word */ struct hns3_cmq cmq; struct hns3_mbx_resp_status mbx_resp; /* mailbox response */ - struct hns3_mbx_arq_ring arq; /* mailbox async rx queue */ - pthread_t irq_thread_id; struct hns3_mac mac; unsigned int secondary_cnt; /* Number of secondary processes init'd. */ struct hns3_tqp_stats tqp_stats; /* Include Mac stats | Rx stats | Tx stats */ struct hns3_mac_stats mac_stats; + struct hns3_rx_missed_stats imissed_stats; + uint64_t oerror_stats; uint32_t fw_version; uint16_t num_msi; uint16_t total_tqps_num; /* total task queue pairs of this PF */ uint16_t tqps_num; /* num task queue pairs of this function */ + uint16_t intr_tqps_num; /* num queue pairs mapping interrupt */ uint16_t rss_size_max; /* HW defined max RSS task queue */ - uint16_t rx_buf_len; + uint16_t rx_buf_len; /* hold min hardware rx buf len */ uint16_t num_tx_desc; /* desc num of per tx queue */ uint16_t num_rx_desc; /* desc num of per rx queue */ + uint32_t mng_entry_num; /* number of manager table entry */ + uint32_t mac_entry_num; /* number of mac-vlan table entry */ struct rte_ether_addr mc_addrs[HNS3_MC_MACADDR_NUM]; int mc_addrs_num; /* Multicast mac addresses number */ /* The configuration info of RSS */ struct hns3_rss_conf rss_info; + bool rss_dis_flag; /* disable rss flag. true: disable, false: enable */ + uint16_t rss_ind_tbl_size; + uint16_t rss_key_size; uint8_t num_tc; /* Total number of enabled TCs */ uint8_t hw_tc_map; - enum hns3_fc_mode current_mode; - enum hns3_fc_mode requested_mode; + enum hns3_fc_mode requested_fc_mode; /* FC mode requested by user */ struct hns3_dcb_info dcb_info; enum hns3_fc_status current_fc_status; /* current flow control status */ struct hns3_tc_queue_info tc_queue[HNS3_MAX_TC_NUM]; @@ -384,7 +525,112 @@ struct hns3_hw { uint16_t alloc_rss_size; /* RX queue number per TC */ uint16_t tx_qnum_per_tc; /* TX queue number per TC */ - uint32_t flag; + uint32_t capability; + uint32_t max_tm_rate; + /* + * The minimum length of the packet supported by hardware in the Tx + * direction. + */ + uint32_t min_tx_pkt_len; + + struct hns3_queue_intr intr; + /* + * tso mode. + * value range: + * HNS3_TSO_SW_CAL_PSEUDO_H_CSUM/HNS3_TSO_HW_CAL_PSEUDO_H_CSUM + * + * - HNS3_TSO_SW_CAL_PSEUDO_H_CSUM + * In this mode, because of the hardware constraint, network driver + * software need erase the L4 len value of the TCP pseudo header + * and recalculate the TCP pseudo header checksum of packets that + * need TSO. + * + * - HNS3_TSO_HW_CAL_PSEUDO_H_CSUM + * In this mode, hardware support recalculate the TCP pseudo header + * checksum of packets that need TSO, so network driver software + * not need to recalculate it. + */ + uint8_t tso_mode; + /* + * vlan mode. + * value range: + * HNS3_SW_SHIFT_AND_DISCARD_MODE/HNS3_HW_SHFIT_AND_DISCARD_MODE + * + * - HNS3_SW_SHIFT_AND_DISCARD_MODE + * For some versions of hardware network engine, because of the + * hardware limitation, PMD driver needs to detect the PVID status + * to work with haredware to implement PVID-related functions. + * For example, driver need discard the stripped PVID tag to ensure + * the PVID will not report to mbuf and shift the inserted VLAN tag + * to avoid port based VLAN covering it. + * + * - HNS3_HW_SHIT_AND_DISCARD_MODE + * PMD driver does not need to process PVID-related functions in + * I/O process, Hardware will adjust the sequence between port based + * VLAN tag and BD VLAN tag automatically and VLAN tag stripped by + * PVID will be invisible to driver. And in this mode, hns3 is able + * to send a multi-layer VLAN packets when hw VLAN insert offload + * is enabled. + */ + uint8_t vlan_mode; + /* + * promisc mode. + * value range: + * HNS3_UNLIMIT_PROMISC_MODE/HNS3_LIMIT_PROMISC_MODE + * + * - HNS3_UNLIMIT_PROMISC_MODE + * In this mode, TX unicast promisc will be configured when promisc + * is set, driver can receive all the ingress and outgoing traffic. + * In the words, all the ingress packets, all the packets sent from + * the PF and other VFs on the same physical port. + * + * - HNS3_LIMIT_PROMISC_MODE + * In this mode, TX unicast promisc is shutdown when promisc mode + * is set. So, driver will only receive all the ingress traffic. + * The packets sent from the PF and other VFs on the same physical + * port won't be copied to the function which has set promisc mode. + */ + uint8_t promisc_mode; + + /* + * drop_stats_mode mode. + * value range: + * HNS3_PKTS_DROP_STATS_MODE1/HNS3_PKTS_DROP_STATS_MODE2 + * + * - HNS3_PKTS_DROP_STATS_MODE1 + * This mode for kunpeng920. In this mode, port level imissed stats + * is supported. It only includes RPU drop stats. + * + * - HNS3_PKTS_DROP_STATS_MODE2 + * This mode for kunpeng930. In this mode, imissed stats and oerrors + * stats is supported. Function level imissed stats is supported. It + * includes RPU drop stats in VF, and includes both RPU drop stats + * and SSU drop stats in PF. Oerror stats is also supported in PF. + */ + uint8_t drop_stats_mode; + + uint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */ + /* + * udp checksum mode. + * value range: + * HNS3_SPECIAL_PORT_HW_CKSUM_MODE/HNS3_SPECIAL_PORT_SW_CKSUM_MODE + * + * - HNS3_SPECIAL_PORT_SW_CKSUM_MODE + * In this mode, HW can not do checksum for special UDP port like + * 4789, 4790, 6081 for non-tunnel UDP packets and UDP tunnel + * packets without the PKT_TX_TUNEL_MASK in the mbuf. So, PMD need + * do the checksum for these packets to avoid a checksum error. + * + * - HNS3_SPECIAL_PORT_HW_CKSUM_MODE + * In this mode, HW does not have the preceding problems and can + * directly calculate the checksum of these UDP packets. + */ + uint8_t udp_cksum_mode; + + struct hns3_port_base_vlan_config port_base_vlan_cfg; + + pthread_mutex_t flows_lock; /* rte_flow ops lock */ + /* * PMD setup and configuration is not thread safe. Since it is not * performance sensitive, it is better to guarantee thread-safety @@ -399,14 +645,6 @@ struct hns3_hw { #define HNS3_FLAG_TC_BASE_SCH_MODE 1 #define HNS3_FLAG_VNET_BASE_SCH_MODE 2 -struct hns3_err_msix_intr_stats { - uint64_t mac_afifo_tnl_intr_cnt; - uint64_t ppu_mpf_abnormal_intr_st2_cnt; - uint64_t ssu_port_based_pf_intr_cnt; - uint64_t ppp_pf_abnormal_intr_cnt; - uint64_t ppu_pf_abnormal_intr_cnt; -}; - /* vlan entry information. */ struct hns3_user_vlan_table { LIST_ENTRY(hns3_user_vlan_table) next; @@ -414,18 +652,23 @@ struct hns3_user_vlan_table { uint16_t vlan_id; }; -struct hns3_port_base_vlan_config { - uint16_t state; - uint16_t pvid; -}; - /* Vlan tag configuration for RX direction */ struct hns3_rx_vtag_cfg { - uint8_t rx_vlan_offload_en; /* Whether enable rx vlan offload */ - uint8_t strip_tag1_en; /* Whether strip inner vlan tag */ - uint8_t strip_tag2_en; /* Whether strip outer vlan tag */ - uint8_t vlan1_vlan_prionly; /* Inner VLAN Tag up to descriptor Enable */ - uint8_t vlan2_vlan_prionly; /* Outer VLAN Tag up to descriptor Enable */ + bool rx_vlan_offload_en; /* Whether enable rx vlan offload */ + bool strip_tag1_en; /* Whether strip inner vlan tag */ + bool strip_tag2_en; /* Whether strip outer vlan tag */ + /* + * If strip_tag_en is enabled, this bit decide whether to map the vlan + * tag to descriptor. + */ + bool strip_tag1_discard_en; + bool strip_tag2_discard_en; + /* + * If this bit is enabled, only map inner/outer priority to descriptor + * and the vlan tag is always 0. + */ + bool vlan1_vlan_prionly; + bool vlan2_vlan_prionly; }; /* Vlan tag configuration for TX direction */ @@ -434,10 +677,15 @@ struct hns3_tx_vtag_cfg { bool accept_untag1; /* Whether accept untag1 packet from host */ bool accept_tag2; bool accept_untag2; - bool insert_tag1_en; /* Whether insert inner vlan tag */ - bool insert_tag2_en; /* Whether insert outer vlan tag */ - uint16_t default_tag1; /* The default inner vlan tag to insert */ - uint16_t default_tag2; /* The default outer vlan tag to insert */ + bool insert_tag1_en; /* Whether insert outer vlan tag */ + bool insert_tag2_en; /* Whether insert inner vlan tag */ + /* + * In shift mode, hw will shift the sequence of port based VLAN and + * BD VLAN. + */ + bool tag_shift_mode_en; /* hw shift vlan tag automatically */ + uint16_t default_tag1; /* The default outer vlan tag to insert */ + uint16_t default_tag2; /* The default inner vlan tag to insert */ }; struct hns3_vtag_cfg { @@ -465,11 +713,63 @@ struct hns3_mp_param { /* Key string for IPC. */ #define HNS3_MP_NAME "net_hns3_mp" +#define HNS3_L2TBL_NUM 4 +#define HNS3_L3TBL_NUM 16 +#define HNS3_L4TBL_NUM 16 +#define HNS3_OL2TBL_NUM 4 +#define HNS3_OL3TBL_NUM 16 +#define HNS3_OL4TBL_NUM 16 +#define HNS3_PTYPE_NUM 256 + +struct hns3_ptype_table { + /* + * The next fields used to calc packet-type by the + * L3_ID/L4_ID/OL3_ID/OL4_ID from the Rx descriptor. + */ + uint32_t l3table[HNS3_L3TBL_NUM]; + uint32_t l4table[HNS3_L4TBL_NUM]; + uint32_t inner_l3table[HNS3_L3TBL_NUM]; + uint32_t inner_l4table[HNS3_L4TBL_NUM]; + uint32_t ol3table[HNS3_OL3TBL_NUM]; + uint32_t ol4table[HNS3_OL4TBL_NUM]; + + /* + * The next field used to calc packet-type by the PTYPE from the Rx + * descriptor, it functions only when firmware report the capability of + * HNS3_CAPS_RXD_ADV_LAYOUT_B and driver enabled it. + */ + uint32_t ptype[HNS3_PTYPE_NUM] __rte_cache_min_aligned; +}; + +#define HNS3_FIXED_MAX_TQP_NUM_MODE 0 +#define HNS3_FLEX_MAX_TQP_NUM_MODE 1 + struct hns3_pf { struct hns3_adapter *adapter; bool is_main_pf; uint16_t func_num; /* num functions of this pf, include pf and vfs */ + /* + * tqp_config mode + * tqp_config_mode value range: + * HNS3_FIXED_MAX_TQP_NUM_MODE, + * HNS3_FLEX_MAX_TQP_NUM_MODE + * + * - HNS3_FIXED_MAX_TQP_NUM_MODE + * There is a limitation on the number of pf interrupts available for + * on some versions of network engines. In this case, the maximum + * queue number of pf can not be greater than the interrupt number, + * such as pf of network engine with revision_id 0x21. So the maximum + * number of queues must be fixed. + * + * - HNS3_FLEX_MAX_TQP_NUM_MODE + * In this mode, the maximum queue number of pf has not any constraint + * and comes from the macro RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF + * in the config file. Users can modify the macro according to their + * own application scenarios, which is more flexible to use. + */ + uint8_t tqp_config_mode; + uint32_t pkt_buf_size; /* Total pf buf size for tx/rx */ uint32_t tx_buf_size; /* Tx buffer size for each TC */ uint32_t dv_buf_size; /* Dv buffer size for each TC */ @@ -488,21 +788,43 @@ struct hns3_pf { uint16_t max_umv_size; uint16_t used_umv_size; - /* Statistics information for abnormal interrupt */ - struct hns3_err_msix_intr_stats abn_int_stats; - bool support_sfp_query; + uint32_t fec_mode; /* current FEC mode for ethdev */ + + bool ptp_enable; + + /* Stores timestamp of last received packet on dev */ + uint64_t rx_timestamp; struct hns3_vtag_cfg vtag_config; - struct hns3_port_base_vlan_config port_base_vlan_cfg; LIST_HEAD(vlan_tbl, hns3_user_vlan_table) vlan_list; struct hns3_fdir_info fdir; /* flow director info */ LIST_HEAD(counters, hns3_flow_counter) flow_counters; + + struct hns3_tm_conf tm_conf; +}; + +enum { + HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED, + HNS3_PF_PUSH_LSC_CAP_SUPPORTED, + HNS3_PF_PUSH_LSC_CAP_UNKNOWN }; struct hns3_vf { struct hns3_adapter *adapter; + + /* Whether PF support push link status change to VF */ + uint16_t pf_push_lsc_cap; + + /* + * If PF support push link status change, VF still need send request to + * get link status in some cases (such as reset recover stage), so use + * the req_link_info_cnt to control max request count. + */ + uint16_t req_link_info_cnt; + + uint16_t poll_job_started; /* whether poll job is started */ }; struct hns3_adapter { @@ -514,24 +836,92 @@ struct hns3_adapter { struct hns3_pf pf; struct hns3_vf vf; }; + + uint32_t rx_func_hint; + uint32_t tx_func_hint; + + uint64_t dev_caps_mask; + + struct hns3_ptype_table ptype_tbl __rte_cache_min_aligned; }; -#define HNS3_DEV_SUPPORT_DCB_B 0x0 +enum { + HNS3_IO_FUNC_HINT_NONE = 0, + HNS3_IO_FUNC_HINT_VEC, + HNS3_IO_FUNC_HINT_SVE, + HNS3_IO_FUNC_HINT_SIMPLE, + HNS3_IO_FUNC_HINT_COMMON +}; + +#define HNS3_DEVARG_RX_FUNC_HINT "rx_func_hint" +#define HNS3_DEVARG_TX_FUNC_HINT "tx_func_hint" + +#define HNS3_DEVARG_DEV_CAPS_MASK "dev_caps_mask" + +enum { + HNS3_DEV_SUPPORT_DCB_B, + HNS3_DEV_SUPPORT_COPPER_B, + HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B, + HNS3_DEV_SUPPORT_PTP_B, + HNS3_DEV_SUPPORT_INDEP_TXRX_B, + HNS3_DEV_SUPPORT_STASH_B, + HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, + HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B, + HNS3_DEV_SUPPORT_RAS_IMP_B, +}; #define hns3_dev_dcb_supported(hw) \ - hns3_get_bit((hw)->flag, HNS3_DEV_SUPPORT_DCB_B) + hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B) + +/* Support copper media type */ +#define hns3_dev_copper_supported(hw) \ + hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_COPPER_B) + +/* Support the queue region action rule of flow directory */ +#define hns3_dev_fd_queue_region_supported(hw) \ + hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B) + +/* Support PTP timestamp offload */ +#define hns3_dev_ptp_supported(hw) \ + hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_PTP_B) + +/* Support to Independently enable/disable/reset Tx or Rx queues */ +#define hns3_dev_indep_txrx_supported(hw) \ + hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_INDEP_TXRX_B) + +#define hns3_dev_stash_supported(hw) \ + hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_STASH_B) + +#define hns3_dev_rxd_adv_layout_supported(hw) \ + hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B) + +#define hns3_dev_outer_udp_cksum_supported(hw) \ + hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B) + +#define hns3_dev_ras_imp_supported(hw) \ + hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_RAS_IMP_B) #define HNS3_DEV_PRIVATE_TO_HW(adapter) \ (&((struct hns3_adapter *)adapter)->hw) -#define HNS3_DEV_PRIVATE_TO_ADAPTER(adapter) \ - ((struct hns3_adapter *)adapter) #define HNS3_DEV_PRIVATE_TO_PF(adapter) \ (&((struct hns3_adapter *)adapter)->pf) -#define HNS3VF_DEV_PRIVATE_TO_VF(adapter) \ +#define HNS3_DEV_PRIVATE_TO_VF(adapter) \ (&((struct hns3_adapter *)adapter)->vf) #define HNS3_DEV_HW_TO_ADAPTER(hw) \ container_of(hw, struct hns3_adapter, hw) +static inline struct hns3_pf *HNS3_DEV_HW_TO_PF(struct hns3_hw *hw) +{ + struct hns3_adapter *adapter = HNS3_DEV_HW_TO_ADAPTER(hw); + return &adapter->pf; +} + +static inline struct hns3_vf *HNS3_DEV_HW_TO_VF(struct hns3_hw *hw) +{ + struct hns3_adapter *adapter = HNS3_DEV_HW_TO_ADAPTER(hw); + return &adapter->vf; +} + #define hns3_set_field(origin, mask, shift, val) \ do { \ (origin) &= (~(mask)); \ @@ -544,6 +934,8 @@ struct hns3_adapter { #define hns3_get_bit(origin, shift) \ hns3_get_field((origin), (0x1UL << (shift)), (shift)) +#define hns3_gen_field_val(mask, shift, val) (((val) << (shift)) & (mask)) + /* * upper_32_bits - return bits 32-63 of a number * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress @@ -557,6 +949,8 @@ struct hns3_adapter { #define BIT(nr) (1UL << (nr)) +#define BIT_ULL(x) (1ULL << (x)) + #define BITS_PER_LONG (__SIZEOF_LONG__ * 8) #define GENMASK(h, l) \ (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) @@ -566,19 +960,39 @@ struct hns3_adapter { #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) -#define max_t(type, x, y) ({ \ - type __max1 = (x); \ - type __max2 = (y); \ - __max1 > __max2 ? __max1 : __max2; }) - +/* + * Because hardware always access register in little-endian mode based on hns3 + * network engine, so driver should also call rte_cpu_to_le_32 to convert data + * in little-endian mode before writing register and call rte_le_to_cpu_32 to + * convert data after reading from register. + * + * Here the driver encapsulates the data conversion operation in the register + * read/write operation function as below: + * hns3_write_reg + * hns3_write_reg_opt + * hns3_read_reg + * Therefore, when calling these functions, conversion is not required again. + */ static inline void hns3_write_reg(void *base, uint32_t reg, uint32_t value) { - rte_write32(value, (volatile void *)((char *)base + reg)); + rte_write32(rte_cpu_to_le_32(value), + (volatile void *)((char *)base + reg)); +} + +/* + * The optimized function for writing registers reduces one address addition + * calculation, it was used in the '.rx_pkt_burst' and '.tx_pkt_burst' ops + * implementation function. + */ +static inline void hns3_write_reg_opt(volatile void *addr, uint32_t value) +{ + rte_write32(rte_cpu_to_le_32(value), addr); } static inline uint32_t hns3_read_reg(void *base, uint32_t reg) { - return rte_read32((volatile void *)((char *)base + reg)); + uint32_t read_val = rte_read32((volatile void *)((char *)base + reg)); + return rte_le_to_cpu_32(read_val); } #define hns3_write_dev(a, reg, value) \ @@ -587,8 +1001,6 @@ static inline uint32_t hns3_read_reg(void *base, uint32_t reg) #define hns3_read_dev(a, reg) \ hns3_read_reg((a)->io_base, (reg)) -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) - #define NEXT_ITEM_OF_ACTION(act, actions, index) \ do { \ act = (actions) + (index); \ @@ -601,15 +1013,9 @@ static inline uint32_t hns3_read_reg(void *base, uint32_t reg) #define MSEC_PER_SEC 1000L #define USEC_PER_MSEC 1000L -static inline uint64_t -get_timeofday_ms(void) -{ - struct timeval tv; - - (void)gettimeofday(&tv, NULL); - - return (uint64_t)tv.tv_sec * MSEC_PER_SEC + tv.tv_usec / USEC_PER_MSEC; -} +void hns3_clock_gettime(struct timeval *tv); +uint64_t hns3_clock_calctime_ms(struct timeval *tv); +uint64_t hns3_clock_gettime_ms(void); static inline uint64_t hns3_atomic_test_bit(unsigned int nr, volatile uint64_t *addr) @@ -641,13 +1047,34 @@ hns3_test_and_clear_bit(unsigned int nr, volatile uint64_t *addr) } int hns3_buffer_alloc(struct hns3_hw *hw); -int hns3_config_gro(struct hns3_hw *hw, bool en); -int hns3_dev_filter_ctrl(struct rte_eth_dev *dev, - enum rte_filter_type filter_type, - enum rte_filter_op filter_op, void *arg); +int hns3_dev_flow_ops_get(struct rte_eth_dev *dev, + const struct rte_flow_ops **ops); bool hns3_is_reset_pending(struct hns3_adapter *hns); bool hns3vf_is_reset_pending(struct hns3_adapter *hns); -void hns3_update_link_status(struct hns3_hw *hw); +void hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query); +void hns3_ether_format_addr(char *buf, uint16_t size, + const struct rte_ether_addr *ether_addr); +int hns3_dev_infos_get(struct rte_eth_dev *eth_dev, + struct rte_eth_dev_info *info); +void hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status, + uint32_t link_speed, uint8_t link_duplex); +void hns3_parse_devargs(struct rte_eth_dev *dev); +void hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported); +int hns3_restore_ptp(struct hns3_adapter *hns); +int hns3_mbuf_dyn_rx_timestamp_register(struct rte_eth_dev *dev, + struct rte_eth_conf *conf); +int hns3_ptp_init(struct hns3_hw *hw); +int hns3_timesync_enable(struct rte_eth_dev *dev); +int hns3_timesync_disable(struct rte_eth_dev *dev); +int hns3_timesync_read_rx_timestamp(struct rte_eth_dev *dev, + struct timespec *timestamp, + uint32_t flags __rte_unused); +int hns3_timesync_read_tx_timestamp(struct rte_eth_dev *dev, + struct timespec *timestamp); +int hns3_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts); +int hns3_timesync_write_time(struct rte_eth_dev *dev, + const struct timespec *ts); +int hns3_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); static inline bool is_reset_pending(struct hns3_adapter *hns) @@ -660,4 +1087,13 @@ is_reset_pending(struct hns3_adapter *hns) return ret; } +static inline uint64_t +hns3_txvlan_cap_get(struct hns3_hw *hw) +{ + if (hw->port_base_vlan_cfg.state) + return DEV_TX_OFFLOAD_VLAN_INSERT; + else + return DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT; +} + #endif /* _HNS3_ETHDEV_H_ */