X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fhns3%2Fhns3_ethdev.h;h=d27c725175d9b714722a64dda1830d6d672abbb9;hb=a2bc5d7bcc11438404027c119e889f6cd4c2bdfa;hp=39afae7b8010fed7721225bde0da4f5c260cf466;hpb=d4fdb71a0e7beb95b6e2c6ffe13fb159904317bf;p=dpdk.git

diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h
index 39afae7b80..d27c725175 100644
--- a/drivers/net/hns3/hns3_ethdev.h
+++ b/drivers/net/hns3/hns3_ethdev.h
@@ -5,6 +5,7 @@
 #ifndef _HNS3_ETHDEV_H_
 #define _HNS3_ETHDEV_H_
 
+#include <pthread.h>
 #include <sys/time.h>
 #include <ethdev_driver.h>
 #include <rte_byteorder.h>
@@ -165,6 +166,12 @@ struct hns3_cfg {
 	uint16_t umv_space;
 };
 
+struct hns3_set_link_speed_cfg {
+	uint32_t speed;
+	uint8_t duplex  : 1;
+	uint8_t autoneg : 1;
+};
+
 /* mac media type */
 enum hns3_media_type {
 	HNS3_MEDIA_TYPE_UNKNOWN,
@@ -174,6 +181,9 @@ enum hns3_media_type {
 	HNS3_MEDIA_TYPE_NONE,
 };
 
+#define HNS3_DEFAULT_QUERY		0
+#define HNS3_ACTIVE_QUERY		1
+
 struct hns3_mac {
 	uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
 	bool default_addr_setted; /* whether default addr(mac_addr) is set */
@@ -183,10 +193,29 @@ struct hns3_mac {
 	uint8_t link_autoneg : 1; /* ETH_LINK_[AUTONEG/FIXED] */
 	uint8_t link_status  : 1; /* ETH_LINK_[DOWN/UP] */
 	uint32_t link_speed;      /* ETH_SPEED_NUM_ */
+	/*
+	 * Some firmware versions support only the SFP speed query. In addition
+	 * to the SFP speed query, some firmware supports the query of the speed
+	 * capability, auto-negotiation capability, and FEC mode, which can be
+	 * selected by the 'query_type' filed in the HNS3_OPC_GET_SFP_INFO CMD.
+	 * This field is used to record the SFP information query mode.
+	 * Value range:
+	 *       HNS3_DEFAULT_QUERY/HNS3_ACTIVE_QUERY
+	 *
+	 * - HNS3_DEFAULT_QUERY
+	 * Speed obtained is from SFP. When the queried speed changes, the MAC
+	 * speed needs to be reconfigured.
+	 *
+	 * - HNS3_ACTIVE_QUERY
+	 * Speed obtained is from MAC. At this time, it is unnecessary for
+	 * driver to reconfigured the MAC speed. In addition, more information,
+	 * such as, the speed capability, auto-negotiation capability and FEC
+	 * mode, can be obtained by the HNS3_OPC_GET_SFP_INFO CMD.
+	 */
+	uint8_t query_type;
 	uint32_t supported_speed;  /* supported speed for current media type */
 	uint32_t advertising;     /* advertised capability in the local part */
-	/* advertised capability in the link partner */
-	uint32_t lp_advertising;
+	uint32_t lp_advertising; /* advertised capability in the link partner */
 	uint8_t support_autoneg;
 };
 
@@ -278,8 +307,9 @@ enum hns3_reset_stage {
 };
 
 enum hns3_reset_level {
-	HNS3_NONE_RESET,
+	HNS3_FLR_RESET,     /* A VF perform FLR reset */
 	HNS3_VF_FUNC_RESET, /* A VF function reset */
+
 	/*
 	 * All VFs under a PF perform function reset.
 	 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
@@ -287,6 +317,7 @@ enum hns3_reset_level {
 	 * same.
 	 */
 	HNS3_VF_PF_FUNC_RESET = 2,
+
 	/*
 	 * All VFs under a PF perform FLR reset.
 	 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
@@ -300,14 +331,23 @@ enum hns3_reset_level {
 	 * In PF FLR, the register state of VF is not reliable, VF's driver
 	 * should not access the registers of the VF device.
 	 */
-	HNS3_VF_FULL_RESET = 3,
-	HNS3_FLR_RESET,     /* A VF perform FLR reset */
+	HNS3_VF_FULL_RESET,
+
 	/* All VFs under the rootport perform a global or IMP reset */
 	HNS3_VF_RESET,
-	HNS3_FUNC_RESET,    /* A PF function reset */
+
+	/*
+	 * The enumeration value of HNS3_FUNC_RESET/HNS3_GLOBAL_RESET/
+	 * HNS3_IMP_RESET/HNS3_NONE_RESET are also used by firmware, and
+	 * can not be changed.
+	 */
+
+	HNS3_FUNC_RESET = 5,    /* A PF function reset */
+
 	/* All PFs under the rootport perform a global reset */
 	HNS3_GLOBAL_RESET,
 	HNS3_IMP_RESET,     /* All PFs under the rootport perform a IMP reset */
+	HNS3_NONE_RESET,
 	HNS3_MAX_RESET
 };
 
@@ -585,6 +625,9 @@ struct hns3_hw {
 	uint8_t udp_cksum_mode;
 
 	struct hns3_port_base_vlan_config port_base_vlan_cfg;
+
+	pthread_mutex_t flows_lock; /* rte_flow ops lock */
+
 	/*
 	 * PMD setup and configuration is not thread safe. Since it is not
 	 * performance sensitive, it is better to guarantee thread-safety
@@ -794,6 +837,8 @@ struct hns3_adapter {
 	uint32_t rx_func_hint;
 	uint32_t tx_func_hint;
 
+	uint64_t dev_caps_mask;
+
 	struct hns3_ptype_table ptype_tbl __rte_cache_min_aligned;
 };
 
@@ -808,6 +853,8 @@ enum {
 #define HNS3_DEVARG_RX_FUNC_HINT	"rx_func_hint"
 #define HNS3_DEVARG_TX_FUNC_HINT	"tx_func_hint"
 
+#define HNS3_DEVARG_DEV_CAPS_MASK	"dev_caps_mask"
+
 #define HNS3_DEV_SUPPORT_DCB_B			0x0
 #define HNS3_DEV_SUPPORT_COPPER_B		0x1
 #define HNS3_DEV_SUPPORT_UDP_GSO_B		0x2
@@ -818,6 +865,7 @@ enum {
 #define HNS3_DEV_SUPPORT_STASH_B		0x7
 #define HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B	0x9
 #define HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B	0xA
+#define HNS3_DEV_SUPPORT_RAS_IMP_B		0xB
 
 #define hns3_dev_dcb_supported(hw) \
 	hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B)
@@ -854,6 +902,9 @@ enum {
 #define hns3_dev_outer_udp_cksum_supported(hw) \
 	hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B)
 
+#define hns3_dev_ras_imp_supported(hw) \
+	hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_RAS_IMP_B)
+
 #define HNS3_DEV_PRIVATE_TO_HW(adapter) \
 	(&((struct hns3_adapter *)adapter)->hw)
 #define HNS3_DEV_PRIVATE_TO_PF(adapter) \