X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fhns3%2Fhns3_ethdev.h;h=dcae15482edbff8c5acfb394d76934828a29702b;hb=821496d2144c0014d62477721f74fb15dc819f7f;hp=7422706a8ad1294d0a021c8914b1f3f3926891cd;hpb=89c04d81175aaf6b0277f1f1d2345d6daf97df43;p=dpdk.git diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index 7422706a8a..dcae15482e 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -7,6 +7,7 @@ #include #include +#include #include "hns3_cmd.h" #include "hns3_mbx.h" @@ -23,18 +24,37 @@ #define HNS3_DEV_ID_25GE_RDMA 0xA222 #define HNS3_DEV_ID_50GE_RDMA 0xA224 #define HNS3_DEV_ID_100G_RDMA_MACSEC 0xA226 +#define HNS3_DEV_ID_200G_RDMA 0xA228 #define HNS3_DEV_ID_100G_VF 0xA22E #define HNS3_DEV_ID_100G_RDMA_PFC_VF 0xA22F +/* PCI Config offsets */ +#define HNS3_PCI_REVISION_ID 0x08 +#define HNS3_PCI_REVISION_ID_LEN 1 + +#define PCI_REVISION_ID_HIP08_B 0x21 +#define PCI_REVISION_ID_HIP09_A 0x30 + +#define HNS3_PF_FUNC_ID 0 +#define HNS3_1ST_VF_FUNC_ID 1 + +#define HNS3_SW_SHIFT_AND_DISCARD_MODE 0 +#define HNS3_HW_SHIFT_AND_DISCARD_MODE 1 + #define HNS3_UC_MACADDR_NUM 128 #define HNS3_VF_UC_MACADDR_NUM 48 #define HNS3_MC_MACADDR_NUM 128 #define HNS3_MAX_BD_SIZE 65535 -#define HNS3_MAX_TX_BD_PER_PKT 8 +#define HNS3_MAX_NON_TSO_BD_PER_PKT 8 +#define HNS3_MAX_TSO_BD_PER_PKT 63 #define HNS3_MAX_FRAME_LEN 9728 #define HNS3_VLAN_TAG_SIZE 4 #define HNS3_DEFAULT_RX_BUF_LEN 2048 +#define HNS3_MAX_BD_PAYLEN (1024 * 1024 - 1) +#define HNS3_MAX_TSO_HDR_SIZE 512 +#define HNS3_MAX_TSO_HDR_BD_NUM 3 +#define HNS3_MAX_LRO_SIZE 64512 #define HNS3_ETH_OVERHEAD \ (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + HNS3_VLAN_TAG_SIZE * 2) @@ -42,7 +62,10 @@ #define HNS3_MAX_MTU (HNS3_MAX_FRAME_LEN - HNS3_ETH_OVERHEAD) #define HNS3_DEFAULT_MTU 1500UL #define HNS3_DEFAULT_FRAME_LEN (HNS3_DEFAULT_MTU + HNS3_ETH_OVERHEAD) -#define HNS3_MIN_PKT_SIZE 60 +#define HNS3_HIP08_MIN_TX_PKT_LEN 33 +#define HNS3_HIP09_MIN_TX_PKT_LEN 9 + +#define HNS3_BITS_PER_BYTE 8 #define HNS3_4_TCS 4 #define HNS3_8_TCS 8 @@ -112,9 +135,9 @@ enum hns3_fc_status { }; struct hns3_tc_queue_info { - uint8_t tqp_offset; /* TQP offset from base TQP */ - uint8_t tqp_count; /* Total TQPs */ - uint8_t tc; /* TC index */ + uint16_t tqp_offset; /* TQP offset from base TQP */ + uint16_t tqp_count; /* Total TQPs */ + uint8_t tc; /* TC index */ bool enable; /* If this TC is enable or not */ }; @@ -153,6 +176,19 @@ struct hns3_mac { uint32_t link_speed; /* ETH_SPEED_NUM_ */ }; +struct hns3_fake_queue_data { + void **rx_queues; /* Array of pointers to fake RX queues. */ + void **tx_queues; /* Array of pointers to fake TX queues. */ + uint16_t nb_fake_rx_queues; /* Number of fake RX queues. */ + uint16_t nb_fake_tx_queues; /* Number of fake TX queues. */ +}; + +#define HNS3_PORT_BASE_VLAN_DISABLE 0 +#define HNS3_PORT_BASE_VLAN_ENABLE 1 +struct hns3_port_base_vlan_config { + uint16_t state; + uint16_t pvid; +}; /* Primary process maintains driver state in main thread. * @@ -242,6 +278,13 @@ enum hns3_reset_level { * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value * of the reset level and the one defined in kernel driver should be * same. + * + * According to the protocol of PCIe, FLR to a PF resets the PF state as + * well as the SR-IOV extended capability including VF Enable which + * means that VFs no longer exist. + * + * In PF FLR, the register state of VF is not reliable, VF's driver + * should not access the registers of the VF device. */ HNS3_VF_FULL_RESET = 3, HNS3_FLR_RESET, /* A VF perform FLR reset */ @@ -330,9 +373,66 @@ struct hns3_reset_data { struct hns3_wait_data *wait_data; }; +#define HNS3_INTR_MAPPING_VEC_RSV_ONE 0 +#define HNS3_INTR_MAPPING_VEC_ALL 1 + +#define HNS3_INTR_COALESCE_NON_QL 0 +#define HNS3_INTR_COALESCE_QL 1 + +#define HNS3_INTR_COALESCE_GL_UINT_2US 0 +#define HNS3_INTR_COALESCE_GL_UINT_1US 1 + +struct hns3_queue_intr { + /* + * interrupt mapping mode. + * value range: + * HNS3_INTR_MAPPING_VEC_RSV_ONE/HNS3_INTR_MAPPING_VEC_ALL + * + * - HNS3_INTR_MAPPING_VEC_RSV_ONE + * For some versions of hardware network engine, because of the + * hardware constraint, we need implement clearing the mapping + * relationship configurations by binding all queues to the last + * interrupt vector and reserving the last interrupt vector. This + * method results in a decrease of the maximum queues when upper + * applications call the rte_eth_dev_configure API function to + * enable Rx interrupt. + * + * - HNS3_INTR_MAPPING_VEC_ALL + * PMD driver can map/unmmap all interrupt vectors with queues When + * Rx interrupt in enabled. + */ + uint8_t mapping_mode; + /* + * interrupt coalesce mode. + * value range: + * HNS3_INTR_COALESCE_NON_QL/HNS3_INTR_COALESCE_QL + * + * - HNS3_INTR_COALESCE_NON_QL + * For some versions of hardware network engine, hardware doesn't + * support QL(quanity limiter) algorithm for interrupt coalesce + * of queue's interrupt. + * + * - HNS3_INTR_COALESCE_QL + * In this mode, hardware support QL(quanity limiter) algorithm for + * interrupt coalesce of queue's interrupt. + */ + uint8_t coalesce_mode; + /* + * The unit of GL(gap limiter) configuration for interrupt coalesce of + * queue's interrupt. + * value range: + * HNS3_INTR_COALESCE_GL_UINT_2US/HNS3_INTR_COALESCE_GL_UINT_1US + */ + uint8_t gl_unit; +}; + +#define HNS3_TSO_SW_CAL_PSEUDO_H_CSUM 0 +#define HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 1 + struct hns3_hw { struct rte_eth_dev_data *data; void *io_base; + uint8_t revision; /* PCI revision, low byte of class word */ struct hns3_cmq cmq; struct hns3_mbx_resp_status mbx_resp; /* mailbox response */ struct hns3_mbx_arq_ring arq; /* mailbox async rx queue */ @@ -347,16 +447,22 @@ struct hns3_hw { uint16_t num_msi; uint16_t total_tqps_num; /* total task queue pairs of this PF */ uint16_t tqps_num; /* num task queue pairs of this function */ + uint16_t intr_tqps_num; /* num queue pairs mapping interrupt */ uint16_t rss_size_max; /* HW defined max RSS task queue */ - uint16_t rx_buf_len; + uint16_t rx_buf_len; /* hold min hardware rx buf len */ uint16_t num_tx_desc; /* desc num of per tx queue */ uint16_t num_rx_desc; /* desc num of per rx queue */ + uint32_t mng_entry_num; /* number of manager table entry */ + uint32_t mac_entry_num; /* number of mac-vlan table entry */ struct rte_ether_addr mc_addrs[HNS3_MC_MACADDR_NUM]; int mc_addrs_num; /* Multicast mac addresses number */ /* The configuration info of RSS */ struct hns3_rss_conf rss_info; + bool rss_dis_flag; /* disable rss flag. true: disable, false: enable */ + uint16_t rss_ind_tbl_size; + uint16_t rss_key_size; uint8_t num_tc; /* Total number of enabled TCs */ uint8_t hw_tc_map; @@ -365,10 +471,66 @@ struct hns3_hw { struct hns3_dcb_info dcb_info; enum hns3_fc_status current_fc_status; /* current flow control status */ struct hns3_tc_queue_info tc_queue[HNS3_MAX_TC_NUM]; - uint16_t alloc_tqps; - uint16_t alloc_rss_size; /* Queue number per TC */ + uint16_t used_rx_queues; + uint16_t used_tx_queues; - uint32_t flag; + /* Config max queue numbers between rx and tx queues from user */ + uint16_t cfg_max_queues; + struct hns3_fake_queue_data fkq_data; /* fake queue data */ + uint16_t alloc_rss_size; /* RX queue number per TC */ + uint16_t tx_qnum_per_tc; /* TX queue number per TC */ + + uint32_t capability; + uint32_t max_tm_rate; + /* + * The minimum length of the packet supported by hardware in the Tx + * direction. + */ + uint32_t min_tx_pkt_len; + + struct hns3_queue_intr intr; + /* + * tso mode. + * value range: + * HNS3_TSO_SW_CAL_PSEUDO_H_CSUM/HNS3_TSO_HW_CAL_PSEUDO_H_CSUM + * + * - HNS3_TSO_SW_CAL_PSEUDO_H_CSUM + * In this mode, because of the hardware constraint, network driver + * software need erase the L4 len value of the TCP pseudo header + * and recalculate the TCP pseudo header checksum of packets that + * need TSO. + * + * - HNS3_TSO_HW_CAL_PSEUDO_H_CSUM + * In this mode, hardware support recalculate the TCP pseudo header + * checksum of packets that need TSO, so network driver software + * not need to recalculate it. + */ + uint8_t tso_mode; + /* + * vlan mode. + * value range: + * HNS3_SW_SHIFT_AND_DISCARD_MODE/HNS3_HW_SHFIT_AND_DISCARD_MODE + * + * - HNS3_SW_SHIFT_AND_DISCARD_MODE + * For some versions of hardware network engine, because of the + * hardware limitation, PMD driver needs to detect the PVID status + * to work with haredware to implement PVID-related functions. + * For example, driver need discard the stripped PVID tag to ensure + * the PVID will not report to mbuf and shift the inserted VLAN tag + * to avoid port based VLAN covering it. + * + * - HNS3_HW_SHIT_AND_DISCARD_MODE + * PMD driver does not need to process PVID-related functions in + * I/O process, Hardware will adjust the sequence between port based + * VLAN tag and BD VLAN tag automatically and VLAN tag stripped by + * PVID will be invisible to driver. And in this mode, hns3 is able + * to send a multi-layer VLAN packets when hw VLAN insert offload + * is enabled. + */ + uint8_t vlan_mode; + uint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */ + + struct hns3_port_base_vlan_config port_base_vlan_cfg; /* * PMD setup and configuration is not thread safe. Since it is not * performance sensitive, it is better to guarantee thread-safety @@ -384,11 +546,35 @@ struct hns3_hw { #define HNS3_FLAG_VNET_BASE_SCH_MODE 2 struct hns3_err_msix_intr_stats { - uint64_t mac_afifo_tnl_intr_cnt; - uint64_t ppu_mpf_abnormal_intr_st2_cnt; - uint64_t ssu_port_based_pf_intr_cnt; - uint64_t ppp_pf_abnormal_intr_cnt; - uint64_t ppu_pf_abnormal_intr_cnt; + uint64_t mac_afifo_tnl_int_cnt; + uint64_t ppu_mpf_abn_int_st2_msix_cnt; + uint64_t ssu_port_based_pf_int_cnt; + uint64_t ppp_pf_abnormal_int_cnt; + uint64_t ppu_pf_abnormal_int_msix_cnt; + + uint64_t imp_tcm_ecc_int_cnt; + uint64_t cmdq_mem_ecc_int_cnt; + uint64_t imp_rd_poison_int_cnt; + uint64_t tqp_int_ecc_int_cnt; + uint64_t msix_ecc_int_cnt; + uint64_t ssu_ecc_multi_bit_int_0_cnt; + uint64_t ssu_ecc_multi_bit_int_1_cnt; + uint64_t ssu_common_ecc_int_cnt; + uint64_t igu_int_cnt; + uint64_t ppp_mpf_abnormal_int_st1_cnt; + uint64_t ppp_mpf_abnormal_int_st3_cnt; + uint64_t ppu_mpf_abnormal_int_st1_cnt; + uint64_t ppu_mpf_abn_int_st2_ras_cnt; + uint64_t ppu_mpf_abnormal_int_st3_cnt; + uint64_t tm_sch_int_cnt; + uint64_t qcn_fifo_int_cnt; + uint64_t qcn_ecc_int_cnt; + uint64_t ncsi_ecc_int_cnt; + uint64_t ssu_port_based_err_int_cnt; + uint64_t ssu_fifo_overflow_int_cnt; + uint64_t ssu_ets_tcg_int_cnt; + uint64_t igu_egu_tnl_int_cnt; + uint64_t ppu_pf_abnormal_int_ras_cnt; }; /* vlan entry information. */ @@ -398,18 +584,23 @@ struct hns3_user_vlan_table { uint16_t vlan_id; }; -struct hns3_port_base_vlan_config { - uint16_t state; - uint16_t pvid; -}; - /* Vlan tag configuration for RX direction */ struct hns3_rx_vtag_cfg { - uint8_t rx_vlan_offload_en; /* Whether enable rx vlan offload */ - uint8_t strip_tag1_en; /* Whether strip inner vlan tag */ - uint8_t strip_tag2_en; /* Whether strip outer vlan tag */ - uint8_t vlan1_vlan_prionly; /* Inner VLAN Tag up to descriptor Enable */ - uint8_t vlan2_vlan_prionly; /* Outer VLAN Tag up to descriptor Enable */ + bool rx_vlan_offload_en; /* Whether enable rx vlan offload */ + bool strip_tag1_en; /* Whether strip inner vlan tag */ + bool strip_tag2_en; /* Whether strip outer vlan tag */ + /* + * If strip_tag_en is enabled, this bit decide whether to map the vlan + * tag to descriptor. + */ + bool strip_tag1_discard_en; + bool strip_tag2_discard_en; + /* + * If this bit is enabled, only map inner/outer priority to descriptor + * and the vlan tag is always 0. + */ + bool vlan1_vlan_prionly; + bool vlan2_vlan_prionly; }; /* Vlan tag configuration for TX direction */ @@ -418,10 +609,15 @@ struct hns3_tx_vtag_cfg { bool accept_untag1; /* Whether accept untag1 packet from host */ bool accept_tag2; bool accept_untag2; - bool insert_tag1_en; /* Whether insert inner vlan tag */ - bool insert_tag2_en; /* Whether insert outer vlan tag */ - uint16_t default_tag1; /* The default inner vlan tag to insert */ - uint16_t default_tag2; /* The default outer vlan tag to insert */ + bool insert_tag1_en; /* Whether insert outer vlan tag */ + bool insert_tag2_en; /* Whether insert inner vlan tag */ + /* + * In shift mode, hw will shift the sequence of port based VLAN and + * BD VLAN. + */ + bool tag_shift_mode_en; /* hw shift vlan tag automatically */ + uint16_t default_tag1; /* The default outer vlan tag to insert */ + uint16_t default_tag2; /* The default inner vlan tag to insert */ }; struct hns3_vtag_cfg { @@ -449,9 +645,52 @@ struct hns3_mp_param { /* Key string for IPC. */ #define HNS3_MP_NAME "net_hns3_mp" +#define HNS3_L2TBL_NUM 4 +#define HNS3_L3TBL_NUM 16 +#define HNS3_L4TBL_NUM 16 +#define HNS3_OL2TBL_NUM 4 +#define HNS3_OL3TBL_NUM 16 +#define HNS3_OL4TBL_NUM 16 + +struct hns3_ptype_table { + uint32_t l2l3table[HNS3_L2TBL_NUM][HNS3_L3TBL_NUM]; + uint32_t l4table[HNS3_L4TBL_NUM]; + uint32_t inner_l2table[HNS3_L2TBL_NUM]; + uint32_t inner_l3table[HNS3_L3TBL_NUM]; + uint32_t inner_l4table[HNS3_L4TBL_NUM]; + uint32_t ol2table[HNS3_OL2TBL_NUM]; + uint32_t ol3table[HNS3_OL3TBL_NUM]; + uint32_t ol4table[HNS3_OL4TBL_NUM]; +}; + +#define HNS3_FIXED_MAX_TQP_NUM_MODE 0 +#define HNS3_FLEX_MAX_TQP_NUM_MODE 1 + struct hns3_pf { struct hns3_adapter *adapter; bool is_main_pf; + uint16_t func_num; /* num functions of this pf, include pf and vfs */ + + /* + * tqp_config mode + * tqp_config_mode value range: + * HNS3_FIXED_MAX_TQP_NUM_MODE, + * HNS3_FLEX_MAX_TQP_NUM_MODE + * + * - HNS3_FIXED_MAX_TQP_NUM_MODE + * There is a limitation on the number of pf interrupts available for + * on some versions of network engines. In this case, the maximum + * queue number of pf can not be greater than the interrupt number, + * such as pf of network engine with revision_id 0x21. So the maximum + * number of queues must be fixed. + * + * - HNS3_FLEX_MAX_TQP_NUM_MODE + * In this mode, the maximum queue number of pf has not any constraint + * and comes from the macro RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF + * in the config file. Users can modify the macro according to their + * own application scenarios, which is more flexible to use. + */ + uint8_t tqp_config_mode; uint32_t pkt_buf_size; /* Total pf buf size for tx/rx */ uint32_t tx_buf_size; /* Tx buffer size for each TC */ @@ -475,9 +714,9 @@ struct hns3_pf { struct hns3_err_msix_intr_stats abn_int_stats; bool support_sfp_query; + uint32_t fec_mode; /* current FEC mode for ethdev */ struct hns3_vtag_cfg vtag_config; - struct hns3_port_base_vlan_config port_base_vlan_cfg; LIST_HEAD(vlan_tbl, hns3_user_vlan_table) vlan_list; struct hns3_fdir_info fdir; /* flow director info */ @@ -497,12 +736,52 @@ struct hns3_adapter { struct hns3_pf pf; struct hns3_vf vf; }; + + bool rx_simple_allowed; + bool rx_vec_allowed; + bool tx_simple_allowed; + bool tx_vec_allowed; + + struct hns3_ptype_table ptype_tbl __rte_cache_min_aligned; }; #define HNS3_DEV_SUPPORT_DCB_B 0x0 +#define HNS3_DEV_SUPPORT_COPPER_B 0x1 +#define HNS3_DEV_SUPPORT_UDP_GSO_B 0x2 +#define HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B 0x3 +#define HNS3_DEV_SUPPORT_PTP_B 0x4 +#define HNS3_DEV_SUPPORT_TX_PUSH_B 0x5 +#define HNS3_DEV_SUPPORT_INDEP_TXRX_B 0x6 +#define HNS3_DEV_SUPPORT_STASH_B 0x7 #define hns3_dev_dcb_supported(hw) \ - hns3_get_bit((hw)->flag, HNS3_DEV_SUPPORT_DCB_B) + hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B) + +/* Support copper media type */ +#define hns3_dev_copper_supported(hw) \ + hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_COPPER_B) + +/* Support UDP GSO offload */ +#define hns3_dev_udp_gso_supported(hw) \ + hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_UDP_GSO_B) + +/* Support the queue region action rule of flow directory */ +#define hns3_dev_fd_queue_region_supported(hw) \ + hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B) + +/* Support PTP timestamp offload */ +#define hns3_dev_ptp_supported(hw) \ + hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_PTP_B) + +#define hns3_dev_tx_push_supported(hw) \ + hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_TX_PUSH_B) + +/* Support to Independently enable/disable/reset Tx or Rx queues */ +#define hns3_dev_indep_txrx_supported(hw) \ + hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_INDEP_TXRX_B) + +#define hns3_dev_stash_supported(hw) \ + hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_STASH_B) #define HNS3_DEV_PRIVATE_TO_HW(adapter) \ (&((struct hns3_adapter *)adapter)->hw) @@ -540,6 +819,8 @@ struct hns3_adapter { #define BIT(nr) (1UL << (nr)) +#define BIT_ULL(x) (1ULL << (x)) + #define BITS_PER_LONG (__SIZEOF_LONG__ * 8) #define GENMASK(h, l) \ (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) @@ -549,19 +830,39 @@ struct hns3_adapter { #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) -#define max_t(type, x, y) ({ \ - type __max1 = (x); \ - type __max2 = (y); \ - __max1 > __max2 ? __max1 : __max2; }) - +/* + * Because hardware always access register in little-endian mode based on hns3 + * network engine, so driver should also call rte_cpu_to_le_32 to convert data + * in little-endian mode before writing register and call rte_le_to_cpu_32 to + * convert data after reading from register. + * + * Here the driver encapsulates the data conversion operation in the register + * read/write operation function as below: + * hns3_write_reg + * hns3_write_reg_opt + * hns3_read_reg + * Therefore, when calling these functions, conversion is not required again. + */ static inline void hns3_write_reg(void *base, uint32_t reg, uint32_t value) { - rte_write32(value, (volatile void *)((char *)base + reg)); + rte_write32(rte_cpu_to_le_32(value), + (volatile void *)((char *)base + reg)); +} + +/* + * The optimized function for writing registers used in the '.rx_pkt_burst' and + * '.tx_pkt_burst' ops implementation function. + */ +static inline void hns3_write_reg_opt(volatile void *addr, uint32_t value) +{ + rte_io_wmb(); + rte_write32_relaxed(rte_cpu_to_le_32(value), addr); } static inline uint32_t hns3_read_reg(void *base, uint32_t reg) { - return rte_read32((volatile void *)((char *)base + reg)); + uint32_t read_val = rte_read32((volatile void *)((char *)base + reg)); + return rte_le_to_cpu_32(read_val); } #define hns3_write_dev(a, reg, value) \ @@ -624,7 +925,6 @@ hns3_test_and_clear_bit(unsigned int nr, volatile uint64_t *addr) } int hns3_buffer_alloc(struct hns3_hw *hw); -int hns3_config_gro(struct hns3_hw *hw, bool en); int hns3_dev_filter_ctrl(struct rte_eth_dev *dev, enum rte_filter_type filter_type, enum rte_filter_op filter_op, void *arg); @@ -643,4 +943,13 @@ is_reset_pending(struct hns3_adapter *hns) return ret; } +static inline uint64_t +hns3_txvlan_cap_get(struct hns3_hw *hw) +{ + if (hw->port_base_vlan_cfg.state) + return DEV_TX_OFFLOAD_VLAN_INSERT; + else + return DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT; +} + #endif /* _HNS3_ETHDEV_H_ */