X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fhns3%2Fhns3_ethdev.h;h=e1ed4d6086c047ec715c94d8b2fa588e7040e19b;hb=f8e7fcbfd0b8d883343d11a5e621350362ad77ac;hp=b8eb7ddc15d5c83c91e3cecd7d1e90a4b2cf1498;hpb=27911a6e62e53bb4c9e7a05e735801eb4c69b6fc;p=dpdk.git diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index b8eb7ddc15..e1ed4d6086 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -37,6 +37,9 @@ #define HNS3_PF_FUNC_ID 0 #define HNS3_1ST_VF_FUNC_ID 1 +#define HNS3_SW_SHIFT_AND_DISCARD_MODE 0 +#define HNS3_HW_SHIFT_AND_DISCARD_MODE 1 + #define HNS3_UC_MACADDR_NUM 128 #define HNS3_VF_UC_MACADDR_NUM 48 #define HNS3_MC_MACADDR_NUM 128 @@ -58,7 +61,8 @@ #define HNS3_MAX_MTU (HNS3_MAX_FRAME_LEN - HNS3_ETH_OVERHEAD) #define HNS3_DEFAULT_MTU 1500UL #define HNS3_DEFAULT_FRAME_LEN (HNS3_DEFAULT_MTU + HNS3_ETH_OVERHEAD) -#define HNS3_MIN_PKT_SIZE 60 +#define HNS3_HIP08_MIN_TX_PKT_LEN 33 +#define HNS3_HIP09_MIN_TX_PKT_LEN 9 #define HNS3_4_TCS 4 #define HNS3_8_TCS 8 @@ -271,6 +275,13 @@ enum hns3_reset_level { * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value * of the reset level and the one defined in kernel driver should be * same. + * + * According to the protocol of PCIe, FLR to a PF resets the PF state as + * well as the SR-IOV extended capability including VF Enable which + * means that VFs no longer exist. + * + * In PF FLR, the register state of VF is not reliable, VF's driver + * should not access the registers of the VF device. */ HNS3_VF_FULL_RESET = 3, HNS3_FLR_RESET, /* A VF perform FLR reset */ @@ -412,6 +423,9 @@ struct hns3_queue_intr { uint8_t gl_unit; }; +#define HNS3_TSO_SW_CAL_PSEUDO_H_CSUM 0 +#define HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 1 + struct hns3_hw { struct rte_eth_dev_data *data; void *io_base; @@ -432,6 +446,7 @@ struct hns3_hw { uint16_t tqps_num; /* num task queue pairs of this function */ uint16_t intr_tqps_num; /* num queue pairs mapping interrupt */ uint16_t rss_size_max; /* HW defined max RSS task queue */ + uint16_t rx_buf_len; /* hold min hardware rx buf len */ uint16_t num_tx_desc; /* desc num of per tx queue */ uint16_t num_rx_desc; /* desc num of per rx queue */ uint32_t mng_entry_num; /* number of manager table entry */ @@ -464,9 +479,52 @@ struct hns3_hw { uint32_t capability; uint32_t max_tm_rate; + /* + * The minimum length of the packet supported by hardware in the Tx + * direction. + */ + uint32_t min_tx_pkt_len; struct hns3_queue_intr intr; - + /* + * tso mode. + * value range: + * HNS3_TSO_SW_CAL_PSEUDO_H_CSUM/HNS3_TSO_HW_CAL_PSEUDO_H_CSUM + * + * - HNS3_TSO_SW_CAL_PSEUDO_H_CSUM + * In this mode, because of the hardware constraint, network driver + * software need erase the L4 len value of the TCP pseudo header + * and recalculate the TCP pseudo header checksum of packets that + * need TSO. + * + * - HNS3_TSO_HW_CAL_PSEUDO_H_CSUM + * In this mode, hardware support recalculate the TCP pseudo header + * checksum of packets that need TSO, so network driver software + * not need to recalculate it. + */ + uint8_t tso_mode; + /* + * vlan mode. + * value range: + * HNS3_SW_SHIFT_AND_DISCARD_MODE/HNS3_HW_SHFIT_AND_DISCARD_MODE + * + * - HNS3_SW_SHIFT_AND_DISCARD_MODE + * For some versions of hardware network engine, because of the + * hardware limitation, PMD driver needs to detect the PVID status + * to work with haredware to implement PVID-related functions. + * For example, driver need discard the stripped PVID tag to ensure + * the PVID will not report to mbuf and shift the inserted VLAN tag + * to avoid port based VLAN covering it. + * + * - HNS3_HW_SHIT_AND_DISCARD_MODE + * PMD driver does not need to process PVID-related functions in + * I/O process, Hardware will adjust the sequence between port based + * VLAN tag and BD VLAN tag automatically and VLAN tag stripped by + * PVID will be invisible to driver. And in this mode, hns3 is able + * to send a multi-layer VLAN packets when hw VLAN insert offload + * is enabled. + */ + uint8_t vlan_mode; uint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */ struct hns3_port_base_vlan_config port_base_vlan_cfg; @@ -485,11 +543,35 @@ struct hns3_hw { #define HNS3_FLAG_VNET_BASE_SCH_MODE 2 struct hns3_err_msix_intr_stats { - uint64_t mac_afifo_tnl_intr_cnt; - uint64_t ppu_mpf_abnormal_intr_st2_cnt; - uint64_t ssu_port_based_pf_intr_cnt; - uint64_t ppp_pf_abnormal_intr_cnt; - uint64_t ppu_pf_abnormal_intr_cnt; + uint64_t mac_afifo_tnl_int_cnt; + uint64_t ppu_mpf_abn_int_st2_msix_cnt; + uint64_t ssu_port_based_pf_int_cnt; + uint64_t ppp_pf_abnormal_int_cnt; + uint64_t ppu_pf_abnormal_int_msix_cnt; + + uint64_t imp_tcm_ecc_int_cnt; + uint64_t cmdq_mem_ecc_int_cnt; + uint64_t imp_rd_poison_int_cnt; + uint64_t tqp_int_ecc_int_cnt; + uint64_t msix_ecc_int_cnt; + uint64_t ssu_ecc_multi_bit_int_0_cnt; + uint64_t ssu_ecc_multi_bit_int_1_cnt; + uint64_t ssu_common_ecc_int_cnt; + uint64_t igu_int_cnt; + uint64_t ppp_mpf_abnormal_int_st1_cnt; + uint64_t ppp_mpf_abnormal_int_st3_cnt; + uint64_t ppu_mpf_abnormal_int_st1_cnt; + uint64_t ppu_mpf_abn_int_st2_ras_cnt; + uint64_t ppu_mpf_abnormal_int_st3_cnt; + uint64_t tm_sch_int_cnt; + uint64_t qcn_fifo_int_cnt; + uint64_t qcn_ecc_int_cnt; + uint64_t ncsi_ecc_int_cnt; + uint64_t ssu_port_based_err_int_cnt; + uint64_t ssu_fifo_overflow_int_cnt; + uint64_t ssu_ets_tcg_int_cnt; + uint64_t igu_egu_tnl_int_cnt; + uint64_t ppu_pf_abnormal_int_ras_cnt; }; /* vlan entry information. */ @@ -501,11 +583,21 @@ struct hns3_user_vlan_table { /* Vlan tag configuration for RX direction */ struct hns3_rx_vtag_cfg { - uint8_t rx_vlan_offload_en; /* Whether enable rx vlan offload */ - uint8_t strip_tag1_en; /* Whether strip inner vlan tag */ - uint8_t strip_tag2_en; /* Whether strip outer vlan tag */ - uint8_t vlan1_vlan_prionly; /* Inner VLAN Tag up to descriptor Enable */ - uint8_t vlan2_vlan_prionly; /* Outer VLAN Tag up to descriptor Enable */ + bool rx_vlan_offload_en; /* Whether enable rx vlan offload */ + bool strip_tag1_en; /* Whether strip inner vlan tag */ + bool strip_tag2_en; /* Whether strip outer vlan tag */ + /* + * If strip_tag_en is enabled, this bit decide whether to map the vlan + * tag to descriptor. + */ + bool strip_tag1_discard_en; + bool strip_tag2_discard_en; + /* + * If this bit is enabled, only map inner/outer priority to descriptor + * and the vlan tag is always 0. + */ + bool vlan1_vlan_prionly; + bool vlan2_vlan_prionly; }; /* Vlan tag configuration for TX direction */ @@ -514,10 +606,15 @@ struct hns3_tx_vtag_cfg { bool accept_untag1; /* Whether accept untag1 packet from host */ bool accept_tag2; bool accept_untag2; - bool insert_tag1_en; /* Whether insert inner vlan tag */ - bool insert_tag2_en; /* Whether insert outer vlan tag */ - uint16_t default_tag1; /* The default inner vlan tag to insert */ - uint16_t default_tag2; /* The default outer vlan tag to insert */ + bool insert_tag1_en; /* Whether insert outer vlan tag */ + bool insert_tag2_en; /* Whether insert inner vlan tag */ + /* + * In shift mode, hw will shift the sequence of port based VLAN and + * BD VLAN. + */ + bool tag_shift_mode_en; /* hw shift vlan tag automatically */ + uint16_t default_tag1; /* The default outer vlan tag to insert */ + uint16_t default_tag2; /* The default inner vlan tag to insert */ }; struct hns3_vtag_cfg { @@ -545,6 +642,23 @@ struct hns3_mp_param { /* Key string for IPC. */ #define HNS3_MP_NAME "net_hns3_mp" +#define HNS3_L2TBL_NUM 4 +#define HNS3_L3TBL_NUM 16 +#define HNS3_L4TBL_NUM 16 +#define HNS3_OL3TBL_NUM 16 +#define HNS3_OL4TBL_NUM 16 + +struct hns3_ptype_table { + uint32_t l2table[HNS3_L2TBL_NUM]; + uint32_t l3table[HNS3_L3TBL_NUM]; + uint32_t l4table[HNS3_L4TBL_NUM]; + uint32_t inner_l2table[HNS3_L2TBL_NUM]; + uint32_t inner_l3table[HNS3_L3TBL_NUM]; + uint32_t inner_l4table[HNS3_L4TBL_NUM]; + uint32_t ol3table[HNS3_OL3TBL_NUM]; + uint32_t ol4table[HNS3_OL4TBL_NUM]; +}; + struct hns3_pf { struct hns3_adapter *adapter; bool is_main_pf; @@ -593,12 +707,19 @@ struct hns3_adapter { struct hns3_pf pf; struct hns3_vf vf; }; + + bool rx_simple_allowed; + bool rx_vec_allowed; + bool tx_simple_allowed; + bool tx_vec_allowed; + + struct hns3_ptype_table ptype_tbl __rte_cache_min_aligned; }; #define HNS3_DEV_SUPPORT_DCB_B 0x0 #define HNS3_DEV_SUPPORT_COPPER_B 0x1 #define HNS3_DEV_SUPPORT_UDP_GSO_B 0x2 -#define HNS3_DEV_SUPPORT_ADQ_B 0x3 +#define HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B 0x3 #define HNS3_DEV_SUPPORT_PTP_B 0x4 #define HNS3_DEV_SUPPORT_TX_PUSH_B 0x5 #define HNS3_DEV_SUPPORT_INDEP_TXRX_B 0x6 @@ -615,9 +736,9 @@ struct hns3_adapter { #define hns3_dev_udp_gso_supported(hw) \ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_UDP_GSO_B) -/* Support Application Device Queue */ -#define hns3_dev_adq_supported(hw) \ - hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_ADQ_B) +/* Support the queue region action rule of flow directory */ +#define hns3_dev_fd_queue_region_supported(hw) \ + hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B) /* Support PTP timestamp offload */ #define hns3_dev_ptp_supported(hw) \ @@ -678,19 +799,39 @@ struct hns3_adapter { #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) -#define max_t(type, x, y) ({ \ - type __max1 = (x); \ - type __max2 = (y); \ - __max1 > __max2 ? __max1 : __max2; }) - +/* + * Because hardware always access register in little-endian mode based on hns3 + * network engine, so driver should also call rte_cpu_to_le_32 to convert data + * in little-endian mode before writing register and call rte_le_to_cpu_32 to + * convert data after reading from register. + * + * Here the driver encapsulates the data conversion operation in the register + * read/write operation function as below: + * hns3_write_reg + * hns3_write_reg_opt + * hns3_read_reg + * Therefore, when calling these functions, conversion is not required again. + */ static inline void hns3_write_reg(void *base, uint32_t reg, uint32_t value) { - rte_write32(value, (volatile void *)((char *)base + reg)); + rte_write32(rte_cpu_to_le_32(value), + (volatile void *)((char *)base + reg)); +} + +/* + * The optimized function for writing registers used in the '.rx_pkt_burst' and + * '.tx_pkt_burst' ops implementation function. + */ +static inline void hns3_write_reg_opt(volatile void *addr, uint32_t value) +{ + rte_io_wmb(); + rte_write32_relaxed(rte_cpu_to_le_32(value), addr); } static inline uint32_t hns3_read_reg(void *base, uint32_t reg) { - return rte_read32((volatile void *)((char *)base + reg)); + uint32_t read_val = rte_read32((volatile void *)((char *)base + reg)); + return rte_le_to_cpu_32(read_val); } #define hns3_write_dev(a, reg, value) \