X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fi40e%2Fbase%2Fi40e_adminq_cmd.h;h=b459be9212a20eb2f6c2d9af14b6fdb356f78b29;hb=092b38341859c1640871b864817d5e2e4c845edb;hp=cf6ef63e391837ec94f3c4333b5f4908171cfb56;hpb=1a0833efde700134532aa8e2e8a069da7b9fe78b;p=dpdk.git

diff --git a/drivers/net/i40e/base/i40e_adminq_cmd.h b/drivers/net/i40e/base/i40e_adminq_cmd.h
index cf6ef63e39..b459be9212 100644
--- a/drivers/net/i40e/base/i40e_adminq_cmd.h
+++ b/drivers/net/i40e/base/i40e_adminq_cmd.h
@@ -1935,17 +1935,14 @@ enum i40e_aq_phy_type {
 	I40E_PHY_TYPE_25GBASE_LR		= 0x22,
 	I40E_PHY_TYPE_25GBASE_AOC		= 0x23,
 	I40E_PHY_TYPE_25GBASE_ACC		= 0x24,
-#ifdef CARLSVILLE_HW
 	I40E_PHY_TYPE_2_5GBASE_T		= 0x30,
 	I40E_PHY_TYPE_5GBASE_T			= 0x31,
-#endif
 	I40E_PHY_TYPE_MAX,
 	I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP	= 0xFD,
 	I40E_PHY_TYPE_EMPTY			= 0xFE,
 	I40E_PHY_TYPE_DEFAULT			= 0xFF,
 };
 
-#ifdef CARLSVILLE_HW
 #define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \
 				BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \
 				BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) | \
@@ -1984,66 +1981,22 @@ enum i40e_aq_phy_type {
 				BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC) | \
 				BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T) | \
 				BIT_ULL(I40E_PHY_TYPE_5GBASE_T))
-#else
-#define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \
-				BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \
-				BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) | \
-				BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) | \
-				BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) | \
-				BIT_ULL(I40E_PHY_TYPE_XAUI) | \
-				BIT_ULL(I40E_PHY_TYPE_XFI) | \
-				BIT_ULL(I40E_PHY_TYPE_SFI) | \
-				BIT_ULL(I40E_PHY_TYPE_XLAUI) | \
-				BIT_ULL(I40E_PHY_TYPE_XLPPI) | \
-				BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) | \
-				BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) | \
-				BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) | \
-				BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) | \
-				BIT_ULL(I40E_PHY_TYPE_UNRECOGNIZED) | \
-				BIT_ULL(I40E_PHY_TYPE_UNSUPPORTED) | \
-				BIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \
-				BIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \
-				BIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \
-				BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) | \
-				BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) | \
-				BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) | \
-				BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) | \
-				BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) | \
-				BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) | \
-				BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) | \
-				BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) | \
-				BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) | \
-				BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) | \
-				BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) | \
-				BIT_ULL(I40E_PHY_TYPE_25GBASE_KR) | \
-				BIT_ULL(I40E_PHY_TYPE_25GBASE_CR) | \
-				BIT_ULL(I40E_PHY_TYPE_25GBASE_SR) | \
-				BIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \
-				BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \
-				BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC))
-#endif
 
-#ifdef CARLSVILLE_HW
 #define I40E_LINK_SPEED_2_5GB_SHIFT	0x0
-#endif
 #define I40E_LINK_SPEED_100MB_SHIFT	0x1
 #define I40E_LINK_SPEED_1000MB_SHIFT	0x2
 #define I40E_LINK_SPEED_10GB_SHIFT	0x3
 #define I40E_LINK_SPEED_40GB_SHIFT	0x4
 #define I40E_LINK_SPEED_20GB_SHIFT	0x5
 #define I40E_LINK_SPEED_25GB_SHIFT	0x6
-#ifdef CARLSVILLE_HW
 #define I40E_LINK_SPEED_5GB_SHIFT	0x7
-#endif
 
 enum i40e_aq_link_speed {
 	I40E_LINK_SPEED_UNKNOWN	= 0,
 	I40E_LINK_SPEED_100MB	= (1 << I40E_LINK_SPEED_100MB_SHIFT),
 	I40E_LINK_SPEED_1GB	= (1 << I40E_LINK_SPEED_1000MB_SHIFT),
-#ifdef CARLSVILLE_HW
 	I40E_LINK_SPEED_2_5GB	= (1 << I40E_LINK_SPEED_2_5GB_SHIFT),
 	I40E_LINK_SPEED_5GB	= (1 << I40E_LINK_SPEED_5GB_SHIFT),
-#endif
 	I40E_LINK_SPEED_10GB	= (1 << I40E_LINK_SPEED_10GB_SHIFT),
 	I40E_LINK_SPEED_40GB	= (1 << I40E_LINK_SPEED_40GB_SHIFT),
 	I40E_LINK_SPEED_20GB	= (1 << I40E_LINK_SPEED_20GB_SHIFT),
@@ -2089,10 +2042,8 @@ struct i40e_aq_get_phy_abilities_resp {
 #define I40E_AQ_PHY_TYPE_EXT_25G_LR	0x08
 #define I40E_AQ_PHY_TYPE_EXT_25G_AOC	0x10
 #define I40E_AQ_PHY_TYPE_EXT_25G_ACC	0x20
-#ifdef CARLSVILLE_HW
 #define I40E_AQ_PHY_TYPE_EXT_2_5GBASE_T	0x40
 #define I40E_AQ_PHY_TYPE_EXT_5GBASE_T	0x80
-#endif
 	u8	fec_cfg_curr_mod_ext_info;
 #define I40E_AQ_ENABLE_FEC_KR		0x01
 #define I40E_AQ_ENABLE_FEC_RS		0x02