X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fi40e%2Fbase%2Fi40e_adminq_cmd.h;h=d2615705a9c1b6448213c7b4d6ebf841a1f5d2ff;hb=3ff83255288b2eb55eeec205cbc20714d5e6293f;hp=65831ea7abd0de380888975ad4e78ada965d4bd2;hpb=73cd23dd87e9a870421f260fa61a8fe2741a50ba;p=dpdk.git

diff --git a/drivers/net/i40e/base/i40e_adminq_cmd.h b/drivers/net/i40e/base/i40e_adminq_cmd.h
index 65831ea7ab..d2615705a9 100644
--- a/drivers/net/i40e/base/i40e_adminq_cmd.h
+++ b/drivers/net/i40e/base/i40e_adminq_cmd.h
@@ -12,7 +12,7 @@
  */
 
 #define I40E_FW_API_VERSION_MAJOR	0x0001
-#define I40E_FW_API_VERSION_MINOR_X722	0x000B
+#define I40E_FW_API_VERSION_MINOR_X722	0x000C
 #define I40E_FW_API_VERSION_MINOR_X710	0x000C
 
 #define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \
@@ -768,6 +768,7 @@ struct i40e_aqc_set_switch_config {
 #define I40E_AQ_SET_SWITCH_CFG_PROMISC		0x0001
 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER	0x0002
 #define I40E_AQ_SET_SWITCH_CFG_HW_ATR_EVICT	0x0004
+#define I40E_AQ_SET_SWITCH_CFG_OUTER_VLAN	0x0008
 	__le16	valid_flags;
 	/* The ethertype in switch_tag is dropped on ingress and used
 	 * internally by the switch. Set this to zero for the default
@@ -904,7 +905,7 @@ struct i40e_aqc_vsi_properties_data {
 	u8	sec_reserved;
 	/* VLAN section */
 	__le16	pvid; /* VLANS include priority bits */
-	__le16	fcoe_pvid;
+	__le16	outer_vlan;
 	u8	port_vlan_flags;
 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT	0x00
 #define I40E_AQ_VSI_PVLAN_MODE_MASK	(0x03 << \
@@ -920,7 +921,24 @@ struct i40e_aqc_vsi_properties_data {
 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP	0x08
 #define I40E_AQ_VSI_PVLAN_EMOD_STR	0x10
 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING	0x18
-	u8	pvlan_reserved[3];
+	u8	outer_vlan_flags;
+#define I40E_AQ_VSI_OVLAN_MODE_SHIFT	0x00
+#define I40E_AQ_VSI_OVLAN_MODE_MASK	(0x03 << \
+					 I40E_AQ_VSI_OVLAN_MODE_SHIFT)
+#define I40E_AQ_VSI_OVLAN_MODE_UNTAGGED	0x01
+#define I40E_AQ_VSI_OVLAN_MODE_TAGGED	0x02
+#define I40E_AQ_VSI_OVLAN_MODE_ALL	0x03
+#define I40E_AQ_VSI_OVLAN_INSERT_PVID	0x04
+#define I40E_AQ_VSI_OVLAN_EMOD_SHIFT	0x03
+#define I40E_AQ_VSI_OVLAN_EMOD_MASK	(0x03 <<\
+					 I40E_AQ_VSI_OVLAN_EMOD_SHIFT)
+#define I40E_AQ_VSI_OVLAN_EMOD_SHOW_ALL	0x00
+#define I40E_AQ_VSI_OVLAN_EMOD_SHOW_UP	0x01
+#define I40E_AQ_VSI_OVLAN_EMOD_HIDE_ALL	0x02
+#define I40E_AQ_VSI_OVLAN_EMOD_NOTHING	0x03
+#define I40E_AQ_VSI_OVLAN_CTRL_ENA	0x04
+
+	u8	pvlan_reserved[2];
 	/* ingress egress up sections */
 	__le32	ingress_table; /* bitmap, 3 bits per up */
 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT	0
@@ -1222,7 +1240,7 @@ struct i40e_aqc_set_vsi_promiscuous_modes {
 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST	0x04
 #define I40E_AQC_SET_VSI_DEFAULT		0x08
 #define I40E_AQC_SET_VSI_PROMISC_VLAN		0x10
-#define I40E_AQC_SET_VSI_PROMISC_TX		0x8000
+#define I40E_AQC_SET_VSI_PROMISC_RX_ONLY	0x8000
 	__le16	seid;
 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK		0x3FF
 	__le16	vlan_tag;
@@ -1947,8 +1965,10 @@ enum i40e_aq_phy_type {
 	I40E_PHY_TYPE_25GBASE_LR		= 0x22,
 	I40E_PHY_TYPE_25GBASE_AOC		= 0x23,
 	I40E_PHY_TYPE_25GBASE_ACC		= 0x24,
-	I40E_PHY_TYPE_2_5GBASE_T		= 0x30,
-	I40E_PHY_TYPE_5GBASE_T			= 0x31,
+	I40E_PHY_TYPE_2_5GBASE_T		= 0x26,
+	I40E_PHY_TYPE_5GBASE_T			= 0x27,
+	I40E_PHY_TYPE_2_5GBASE_T_LINK_STATUS	= 0x30,
+	I40E_PHY_TYPE_5GBASE_T_LINK_STATUS	= 0x31,
 	I40E_PHY_TYPE_MAX,
 	I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP	= 0xFD,
 	I40E_PHY_TYPE_EMPTY			= 0xFE,
@@ -2015,6 +2035,15 @@ enum i40e_aq_link_speed {
 	I40E_LINK_SPEED_25GB	= (1 << I40E_LINK_SPEED_25GB_SHIFT),
 };
 
+enum i40e_prt_mac_pcs_link_speed {
+	I40E_PRT_MAC_PCS_LINK_SPEED_UNKNOWN = 0,
+	I40E_PRT_MAC_PCS_LINK_SPEED_100MB,
+	I40E_PRT_MAC_PCS_LINK_SPEED_1GB,
+	I40E_PRT_MAC_PCS_LINK_SPEED_10GB,
+	I40E_PRT_MAC_PCS_LINK_SPEED_40GB,
+	I40E_PRT_MAC_PCS_LINK_SPEED_20GB
+};
+
 struct i40e_aqc_module_desc {
 	u8 oui[3];
 	u8 reserved1;
@@ -2425,11 +2454,15 @@ struct i40e_aqc_rollback_revision_update {
 	u8	optin_mode; /* bool */
 #define I40E_AQ_RREV_OPTION_MODE			0x01
 	u8	module_selected;
-#define I40E_AQ_RREV_MODULE_PCIE_ANALOG		0
-#define I40E_AQ_RREV_MODULE_PHY_ANALOG		1
-#define I40E_AQ_RREV_MODULE_OPTION_ROM		2
-#define I40E_AQ_RREV_MODULE_EMP_IMAGE		3
-#define I40E_AQ_RREV_MODULE_PE_IMAGE		4
+#define I40E_AQ_RREV_MODULE_PCIE_ANALOG			0
+#define I40E_AQ_RREV_MODULE_PHY_ANALOG			1
+#define I40E_AQ_RREV_MODULE_OPTION_ROM			2
+#define I40E_AQ_RREV_MODULE_EMP_IMAGE			3
+#define I40E_AQ_RREV_MODULE_PE_IMAGE			4
+#define I40E_AQ_RREV_MODULE_PHY_PLL_O_CONFIGURATION	5
+#define I40E_AQ_RREV_MODULE_PHY_0_CONFIGURATION		6
+#define I40E_AQ_RREV_MODULE_PHY_PLL_1_CONFIGURATION	7
+#define I40E_AQ_RREV_MODULE_PHY_1_CONFIGURATION		8
 	u8	reserved1[2];
 	u32	min_rrev;
 	u8	reserved2[8];