X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fi40e%2Fbase%2Fi40e_osdep.h;h=8a2d82a8d0cace1b6bc16582c88edd75db1f2844;hb=ca9ae7209173b67bcb260f6007ab7a72e4457c4c;hp=71077f0b892610406ac5ff2f5017905882c3d9cb;hpb=3f50f072ff064ead4d7678005df6ebc6bd2b1275;p=dpdk.git diff --git a/drivers/net/i40e/base/i40e_osdep.h b/drivers/net/i40e/base/i40e_osdep.h index 71077f0b89..8a2d82a8d0 100644 --- a/drivers/net/i40e/base/i40e_osdep.h +++ b/drivers/net/i40e/base/i40e_osdep.h @@ -1,40 +1,13 @@ -/****************************************************************************** - - Copyright (c) 2001-2015, Intel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - 3. Neither the name of the Intel Corporation nor the names of its - contributors may be used to endorse or promote products derived from - this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. -******************************************************************************/ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2001-2018 + */ #ifndef _I40E_OSDEP_H_ #define _I40E_OSDEP_H_ #include #include +#include #include #include @@ -44,6 +17,7 @@ #include #include #include +#include #include "../i40e_logs.h" @@ -56,7 +30,6 @@ typedef uint16_t u16; typedef uint32_t u32; typedef int32_t s32; typedef uint64_t u64; -typedef int bool; typedef enum i40e_status_code i40e_status; #define __iomem @@ -98,7 +71,6 @@ typedef enum i40e_status_code i40e_status; #define max(a,b) RTE_MAX(a,b) #define FIELD_SIZEOF(t, f) (sizeof(((t*)0)->f)) -#define ASSERT(x) if(!(x)) rte_panic("IXGBE: x") #define DEBUGOUT(S) PMD_DRV_LOG_RAW(DEBUG, S) #define DEBUGOUT1(S, A...) PMD_DRV_LOG_RAW(DEBUG, S, ##A) @@ -117,15 +89,54 @@ do { \ ##__VA_ARGS__); \ } while (0) -#define I40E_PCI_REG(reg) (*((volatile uint32_t *)(reg))) +/* AQ commands based interfaces of i40e_read_rx_ctl() and i40e_write_rx_ctl() + * are required for reading/writing below registers, as reading/writing it + * directly may not function correctly if the device is under heavy small + * packet traffic. Note that those interfaces are available from FVL5 and not + * suitable before the AdminQ is ready during initialization. + * + * I40E_PFQF_CTL_0 + * I40E_PFQF_HENA + * I40E_PFQF_FDALLOC + * I40E_PFQF_HREGION + * I40E_PFLAN_QALLOC + * I40E_VPQF_CTL + * I40E_VFQF_HENA + * I40E_VFQF_HREGION + * I40E_VSIQF_CTL + * I40E_VSILAN_QBASE + * I40E_VSILAN_QTABLE + * I40E_VSIQF_TCREGION + * I40E_PFQF_HKEY + * I40E_VFQF_HKEY + * I40E_PRTQF_CTL_0 + * I40E_GLFCOE_RCTL + * I40E_GLFCOE_RSOF + * I40E_GLQF_CTL + * I40E_GLQF_SWAP + * I40E_GLQF_HASH_MSK + * I40E_GLQF_HASH_INSET + * I40E_GLQF_HSYM + * I40E_GLQF_FC_MSK + * I40E_GLQF_FC_INSET + * I40E_GLQF_FD_MSK + * I40E_PRTQF_FD_INSET + * I40E_PRTQF_FD_FLXINSET + * I40E_PRTQF_FD_MSK + */ + +#define I40E_PCI_REG(reg) rte_read32(reg) #define I40E_PCI_REG_ADDR(a, reg) \ ((volatile uint32_t *)((char *)(a)->hw_addr + (reg))) static inline uint32_t i40e_read_addr(volatile void *addr) { return rte_le_to_cpu_32(I40E_PCI_REG(addr)); } -#define I40E_PCI_REG_WRITE(reg, value) \ - do { I40E_PCI_REG((reg)) = rte_cpu_to_le_32(value); } while (0) + +#define I40E_PCI_REG_WRITE(reg, value) \ + rte_write32((rte_cpu_to_le_32(value)), reg) +#define I40E_PCI_REG_WRITE_RELAXED(reg, value) \ + rte_write32_relaxed((rte_cpu_to_le_32(value)), reg) #define I40E_WRITE_FLUSH(a) I40E_READ_REG(a, I40E_GLGEN_STAT) #define I40EVF_WRITE_FLUSH(a) I40E_READ_REG(a, I40E_VFGEN_RSTAT) @@ -168,6 +179,13 @@ struct i40e_virt_mem { #define LE32_TO_CPU(c) rte_le_to_cpu_32(c) #define LE64_TO_CPU(k) rte_le_to_cpu_64(k) +#define cpu_to_le16(o) rte_cpu_to_le_16(o) +#define cpu_to_le32(s) rte_cpu_to_le_32(s) +#define cpu_to_le64(h) rte_cpu_to_le_64(h) +#define le16_to_cpu(a) rte_le_to_cpu_16(a) +#define le32_to_cpu(c) rte_le_to_cpu_32(c) +#define le64_to_cpu(k) rte_le_to_cpu_64(k) + /* SW spinlock */ struct i40e_spinlock { rte_spinlock_t spinlock; @@ -187,9 +205,9 @@ struct i40e_spinlock { #define i40e_memcpy(a, b, c, d) rte_memcpy((a), (b), (c)) #define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) -#define DELAY(x) rte_delay_us(x) -#define i40e_usec_delay(x) rte_delay_us(x) -#define i40e_msec_delay(x) rte_delay_us(1000*(x)) +#define DELAY(x) rte_delay_us_sleep(x) +#define i40e_usec_delay(x) DELAY(x) +#define i40e_msec_delay(x) DELAY(1000 * (x)) #define udelay(x) DELAY(x) #define msleep(x) DELAY(1000*(x)) #define usleep_range(min, max) msleep(DIV_ROUND_UP(min, 1000))