X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fi40e%2Fbase%2Fi40e_osdep.h;h=8c84ed824fcfad2c4dfc88cfb262d63c90a11e56;hb=23fb3b460fdccf232c74a6115171e035d1f56435;hp=3ce80578db556c38f6553b8ce5437e90f41caba8;hpb=5c9222058df7cc10fa98c13d097f85a7fa0341a3;p=dpdk.git

diff --git a/drivers/net/i40e/base/i40e_osdep.h b/drivers/net/i40e/base/i40e_osdep.h
index 3ce80578db..8c84ed824f 100644
--- a/drivers/net/i40e/base/i40e_osdep.h
+++ b/drivers/net/i40e/base/i40e_osdep.h
@@ -117,15 +117,51 @@ do {                                                            \
 					##__VA_ARGS__);         \
 } while (0)
 
+/* AQ commands based interfaces of i40e_read_rx_ctl() and i40e_write_rx_ctl()
+ * are required for reading/writing below registers, as reading/writing it
+ * directly may not function correctly if the device is under heavy small
+ * packet traffic. Note that those interfaces are available from FVL5 and not
+ * suitable before the AdminQ is ready during initialization.
+ *
+ * I40E_PFQF_CTL_0
+ * I40E_PFQF_HENA
+ * I40E_PFQF_FDALLOC
+ * I40E_PFQF_HREGION
+ * I40E_PFLAN_QALLOC
+ * I40E_VPQF_CTL
+ * I40E_VFQF_HENA
+ * I40E_VFQF_HREGION
+ * I40E_VSIQF_CTL
+ * I40E_VSILAN_QBASE
+ * I40E_VSILAN_QTABLE
+ * I40E_VSIQF_TCREGION
+ * I40E_PFQF_HKEY
+ * I40E_VFQF_HKEY
+ * I40E_PRTQF_CTL_0
+ * I40E_GLFCOE_RCTL
+ * I40E_GLFCOE_RSOF
+ * I40E_GLQF_CTL
+ * I40E_GLQF_SWAP
+ * I40E_GLQF_HASH_MSK
+ * I40E_GLQF_HASH_INSET
+ * I40E_GLQF_HSYM
+ * I40E_GLQF_FC_MSK
+ * I40E_GLQF_FC_INSET
+ * I40E_GLQF_FD_MSK
+ * I40E_PRTQF_FD_INSET
+ * I40E_PRTQF_FD_FLXINSET
+ * I40E_PRTQF_FD_MSK
+ */
+
 #define I40E_PCI_REG(reg)         (*((volatile uint32_t *)(reg)))
 #define I40E_PCI_REG_ADDR(a, reg) \
 	((volatile uint32_t *)((char *)(a)->hw_addr + (reg)))
 static inline uint32_t i40e_read_addr(volatile void *addr)
 {
-	return I40E_PCI_REG(addr);
+	return rte_le_to_cpu_32(I40E_PCI_REG(addr));
 }
 #define I40E_PCI_REG_WRITE(reg, value) \
-	do {I40E_PCI_REG((reg)) = (value);} while(0)
+	do { I40E_PCI_REG((reg)) = rte_cpu_to_le_32(value); } while (0)
 
 #define I40E_WRITE_FLUSH(a) I40E_READ_REG(a, I40E_GLGEN_STAT)
 #define I40EVF_WRITE_FLUSH(a) I40E_READ_REG(a, I40E_VFGEN_RSTAT)
@@ -146,7 +182,7 @@ struct i40e_dma_mem {
 	void *va;
 	u64 pa;
 	u32 size;
-	u64 id;
+	const void *zone;
 } __attribute__((packed));
 
 #define i40e_allocate_dma_mem(h, m, unused, s, a) \