X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fi40e%2Fbase%2Fi40e_type.h;h=112866bbf22810f88c31a684059f3ac0189a2480;hb=c345c7d1acf43b4d30e1ecdd5a8cd3402234a6aa;hp=77562f24e75327da150b84dba1b18ab1abb9e9b8;hpb=a3aed72d40d055a53c4b9722885a9a4c8b922a1f;p=dpdk.git

diff --git a/drivers/net/i40e/base/i40e_type.h b/drivers/net/i40e/base/i40e_type.h
index 77562f24e7..112866bbf2 100644
--- a/drivers/net/i40e/base/i40e_type.h
+++ b/drivers/net/i40e/base/i40e_type.h
@@ -329,14 +329,12 @@ struct i40e_phy_info {
 					     I40E_PHY_TYPE_OFFSET)
 #define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \
 					     I40E_PHY_TYPE_OFFSET)
-#ifdef CARLSVILLE_HW
 /* Offset for 2.5G/5G PHY Types value to bit number conversion */
 #define I40E_PHY_TYPE_OFFSET2 (-10)
 #define I40E_CAP_PHY_TYPE_2_5GBASE_T BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T + \
 					     I40E_PHY_TYPE_OFFSET2)
 #define I40E_CAP_PHY_TYPE_5GBASE_T BIT_ULL(I40E_PHY_TYPE_5GBASE_T + \
 					     I40E_PHY_TYPE_OFFSET2)
-#endif
 #define I40E_HW_CAP_MAX_GPIO			30
 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO		0
 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C		1
@@ -670,6 +668,7 @@ struct i40e_hw {
 	u8 revision_id;
 	u8 port;
 	bool adapter_stopped;
+	bool adapter_closed;
 
 	/* capabilities for entire device and PCI func */
 	struct i40e_hw_capabilities dev_caps;