X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fi40e%2Fi40e_ethdev.c;h=3e79fc9cb58e4f3388b489248485f1cdd8927bf6;hb=413c157dde72f579129800134a1807a919811d50;hp=284e9cb641b7035b22a9ed427b124d8a28e7723d;hpb=8c56e4089b1eb422154610ec3f084d7416518c4c;p=dpdk.git diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index 284e9cb641..3e79fc9cb5 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -42,6 +42,9 @@ #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb" #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list" +#define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver" +#define ETH_I40E_QUEUE_NUM_PER_VF_ARG "queue-num-per-vf" +#define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec" #define I40E_CLEAR_PXE_WAIT_MS 200 @@ -290,6 +293,7 @@ static void i40e_stat_update_48(struct i40e_hw *hw, uint64_t *stat); static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue); static void i40e_dev_interrupt_handler(void *param); +static void i40e_dev_alarm_handler(void *param); static int i40e_res_pool_init(struct i40e_res_pool_info *pool, uint32_t base, uint32_t num); static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool); @@ -401,6 +405,14 @@ static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev); int i40e_logtype_init; int i40e_logtype_driver; +static const char *const valid_keys[] = { + ETH_I40E_FLOATING_VEB_ARG, + ETH_I40E_FLOATING_VEB_LIST_ARG, + ETH_I40E_SUPPORT_MULTI_DRIVER, + ETH_I40E_QUEUE_NUM_PER_VF_ARG, + ETH_I40E_USE_LATEST_VEC, + NULL}; + static const struct rte_pci_id pci_id_i40e_map[] = { { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) }, { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) }, @@ -694,12 +706,20 @@ static struct rte_pci_driver rte_i40e_pmd = { }; static inline void -i40e_write_global_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) +i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr, + uint32_t reg_val) { + uint32_t ori_reg_val; + struct rte_eth_dev *dev; + + ori_reg_val = i40e_read_rx_ctl(hw, reg_addr); + dev = ((struct i40e_adapter *)hw->back)->eth_dev; i40e_write_rx_ctl(hw, reg_addr, reg_val); - PMD_DRV_LOG(DEBUG, "Global register 0x%08x is modified " - "with value 0x%08x", - reg_addr, reg_val); + if (ori_reg_val != reg_val) + PMD_DRV_LOG(WARNING, + "i40e device %s changed global register [0x%08x]." + " original: 0x%08x, new: 0x%08x", + dev->device->name, reg_addr, ori_reg_val, reg_val); } RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd); @@ -726,7 +746,6 @@ static inline void i40e_GLQF_reg_init(struct i40e_hw *hw) */ I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029); I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420); - i40e_global_cfg_warning(I40E_WARNING_QINQ_PARSER); } static inline void i40e_config_automask(struct i40e_pf *pf) @@ -845,7 +864,7 @@ config_vf_floating_veb(struct rte_devargs *devargs, if (devargs == NULL) return; - kvlist = rte_kvargs_parse(devargs->args, NULL); + kvlist = rte_kvargs_parse(devargs->args, valid_keys); if (kvlist == NULL) return; @@ -886,7 +905,7 @@ is_floating_veb_supported(struct rte_devargs *devargs) if (devargs == NULL) return 0; - kvlist = rte_kvargs_parse(devargs->args, NULL); + kvlist = rte_kvargs_parse(devargs->args, valid_keys); if (kvlist == NULL) return 0; @@ -1093,8 +1112,6 @@ i40e_init_queue_region_conf(struct rte_eth_dev *dev) memset(info, 0, sizeof(struct i40e_queue_regions)); } -#define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver" - static int i40e_parse_multi_drv_handler(__rte_unused const char *key, const char *value, @@ -1126,9 +1143,8 @@ static int i40e_support_multi_driver(struct rte_eth_dev *dev) { struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); - static const char *const valid_keys[] = { - ETH_I40E_SUPPORT_MULTI_DRIVER, NULL}; struct rte_kvargs *kvlist; + int kvargs_count; /* Enable global configuration by default */ pf->support_multi_driver = false; @@ -1140,7 +1156,13 @@ i40e_support_multi_driver(struct rte_eth_dev *dev) if (!kvlist) return -EINVAL; - if (rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER) > 1) + kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER); + if (!kvargs_count) { + rte_kvargs_free(kvlist); + return 0; + } + + if (kvargs_count > 1) PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only " "the first invalid or last valid one is used !", ETH_I40E_SUPPORT_MULTI_DRIVER); @@ -1155,6 +1177,93 @@ i40e_support_multi_driver(struct rte_eth_dev *dev) return 0; } +static int +i40e_aq_debug_write_global_register(struct i40e_hw *hw, + uint32_t reg_addr, uint64_t reg_val, + struct i40e_asq_cmd_details *cmd_details) +{ + uint64_t ori_reg_val; + struct rte_eth_dev *dev; + int ret; + + ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL); + if (ret != I40E_SUCCESS) { + PMD_DRV_LOG(ERR, + "Fail to debug read from 0x%08x", + reg_addr); + return -EIO; + } + dev = ((struct i40e_adapter *)hw->back)->eth_dev; + + if (ori_reg_val != reg_val) + PMD_DRV_LOG(WARNING, + "i40e device %s changed global register [0x%08x]." + " original: 0x%"PRIx64", after: 0x%"PRIx64, + dev->device->name, reg_addr, ori_reg_val, reg_val); + + return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details); +} + +static int +i40e_parse_latest_vec_handler(__rte_unused const char *key, + const char *value, + void *opaque) +{ + struct i40e_adapter *ad; + int use_latest_vec; + + ad = (struct i40e_adapter *)opaque; + + use_latest_vec = atoi(value); + + if (use_latest_vec != 0 && use_latest_vec != 1) + PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!"); + + ad->use_latest_vec = (uint8_t)use_latest_vec; + + return 0; +} + +static int +i40e_use_latest_vec(struct rte_eth_dev *dev) +{ + struct i40e_adapter *ad = + I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); + struct rte_kvargs *kvlist; + int kvargs_count; + + ad->use_latest_vec = false; + + if (!dev->device->devargs) + return 0; + + kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys); + if (!kvlist) + return -EINVAL; + + kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC); + if (!kvargs_count) { + rte_kvargs_free(kvlist); + return 0; + } + + if (kvargs_count > 1) + PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only " + "the first invalid or last valid one is used !", + ETH_I40E_USE_LATEST_VEC); + + if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC, + i40e_parse_latest_vec_handler, ad) < 0) { + rte_kvargs_free(kvlist); + return -EINVAL; + } + + rte_kvargs_free(kvlist); + return 0; +} + +#define I40E_ALARM_INTERVAL 50000 /* us */ + static int eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused) { @@ -1208,15 +1317,21 @@ eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused) hw->bus.func = pci_dev->addr.function; hw->adapter_stopped = 0; + /* + * Switch Tag value should not be identical to either the First Tag + * or Second Tag values. So set something other than common Ethertype + * for internal switching. + */ + hw->switch_tag = 0xffff; + /* Check if need to support multi-driver */ i40e_support_multi_driver(dev); + /* Check if users want the latest supported vec path */ + i40e_use_latest_vec(dev); /* Make sure all is clean before doing PF reset */ i40e_clear_hw(hw); - /* Initialize the hardware */ - i40e_hw_init(dev); - /* Reset here to make sure all is clean for each PF */ ret = i40e_pf_reset(hw); if (ret) { @@ -1231,6 +1346,23 @@ eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused) return ret; } + /* Initialize the parameters for adminq */ + i40e_init_adminq_parameter(hw); + ret = i40e_init_adminq(hw); + if (ret != I40E_SUCCESS) { + PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret); + return -EIO; + } + PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x", + hw->aq.fw_maj_ver, hw->aq.fw_min_ver, + hw->aq.api_maj_ver, hw->aq.api_min_ver, + ((hw->nvm.version >> 12) & 0xf), + ((hw->nvm.version >> 4) & 0xff), + (hw->nvm.version & 0xf), hw->nvm.eetrack); + + /* Initialize the hardware */ + i40e_hw_init(dev); + i40e_config_automask(pf); i40e_set_default_pctype_table(dev); @@ -1246,23 +1378,10 @@ eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused) /* Initialize the input set for filters (hash and fd) to default value */ i40e_filter_input_set_init(pf); - /* Initialize the parameters for adminq */ - i40e_init_adminq_parameter(hw); - ret = i40e_init_adminq(hw); - if (ret != I40E_SUCCESS) { - PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret); - return -EIO; - } - PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x", - hw->aq.fw_maj_ver, hw->aq.fw_min_ver, - hw->aq.api_maj_ver, hw->aq.api_min_ver, - ((hw->nvm.version >> 12) & 0xf), - ((hw->nvm.version >> 4) & 0xff), - (hw->nvm.version & 0xf), hw->nvm.eetrack); - /* initialise the L3_MAP register */ if (!pf->support_multi_driver) { - ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40), + ret = i40e_aq_debug_write_global_register(hw, + I40E_GLQF_L3_MAP(40), 0x00000028, NULL); if (ret) PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", @@ -1270,7 +1389,6 @@ eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused) PMD_INIT_LOG(DEBUG, "Global register 0x%08x is changed with 0x28", I40E_GLQF_L3_MAP(40)); - i40e_global_cfg_warning(I40E_WARNING_QINQ_CLOUD_FILTER); } /* Need the special FW version to support floating VEB */ @@ -1557,7 +1675,6 @@ void i40e_flex_payload_reg_set_default(struct i40e_hw *hw) I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000); I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000); I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000); - i40e_global_cfg_warning(I40E_WARNING_DIS_FLX_PLD); } static int @@ -1800,8 +1917,7 @@ __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect, /* Write first RX queue to Link list register as the head element */ if (vsi->type != I40E_VSI_SRIOV) { uint16_t interval = - i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1, - pf->support_multi_driver); + i40e_calc_itr_interval(1, pf->support_multi_driver); if (msix_vect == I40E_MISC_VEC_ID) { I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0, @@ -1997,27 +2113,40 @@ i40e_phy_conf_link(struct i40e_hw *hw, struct i40e_aq_get_phy_abilities_resp phy_ab; struct i40e_aq_set_phy_config phy_conf; enum i40e_aq_phy_type cnt; + uint8_t avail_speed; uint32_t phy_type_mask = 0; const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX | I40E_AQ_PHY_FLAG_PAUSE_RX | I40E_AQ_PHY_FLAG_PAUSE_RX | I40E_AQ_PHY_FLAG_LOW_POWER; - const uint8_t advt = I40E_LINK_SPEED_40GB | - I40E_LINK_SPEED_25GB | - I40E_LINK_SPEED_10GB | - I40E_LINK_SPEED_1GB | - I40E_LINK_SPEED_100MB; int ret = -ENOTSUP; + /* To get phy capabilities of available speeds. */ + status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab, + NULL); + if (status) { + PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n", + status); + return ret; + } + avail_speed = phy_ab.link_speed; + /* To get the current phy config. */ status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab, NULL); - if (status) + if (status) { + PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n", + status); return ret; + } - /* If link already up, no need to set up again */ - if (is_up && phy_ab.phy_type != 0) + /* If link needs to go up and it is in autoneg mode the speed is OK, + * no need to set up again. + */ + if (is_up && phy_ab.phy_type != 0 && + abilities & I40E_AQ_PHY_AN_ENABLED && + phy_ab.link_speed != 0) return I40E_SUCCESS; memset(&phy_conf, 0, sizeof(phy_conf)); @@ -2026,18 +2155,20 @@ i40e_phy_conf_link(struct i40e_hw *hw, abilities &= ~mask; abilities |= phy_ab.abilities & mask; - /* update ablities and speed */ - if (abilities & I40E_AQ_PHY_AN_ENABLED) - phy_conf.link_speed = advt; - else - phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed; - phy_conf.abilities = abilities; + /* If link needs to go up, but the force speed is not supported, + * Warn users and config the default available speeds. + */ + if (is_up && !(force_speed & avail_speed)) { + PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n"); + phy_conf.link_speed = avail_speed; + } else { + phy_conf.link_speed = is_up ? force_speed : avail_speed; + } - - /* To enable link, phy_type mask needs to include each type */ - for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++) + /* PHY type mask needs to include each type except PHY type extension */ + for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++) phy_type_mask |= 1 << cnt; /* use get_phy_abilities_resp value for the rest */ @@ -2070,11 +2201,18 @@ i40e_apply_link_speed(struct rte_eth_dev *dev) struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); struct rte_eth_conf *conf = &dev->data->dev_conf; + if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) { + conf->link_speeds = ETH_LINK_SPEED_40G | + ETH_LINK_SPEED_25G | + ETH_LINK_SPEED_20G | + ETH_LINK_SPEED_10G | + ETH_LINK_SPEED_1G | + ETH_LINK_SPEED_100M; + } speed = i40e_parse_link_speeds(conf->link_speeds); - abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; - if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED)) - abilities |= I40E_AQ_PHY_AN_ENABLED; - abilities |= I40E_AQ_PHY_LINK_ENABLED; + abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK | + I40E_AQ_PHY_AN_ENABLED | + I40E_AQ_PHY_LINK_ENABLED; return i40e_phy_conf_link(hw, abilities, speed, true); } @@ -2191,13 +2329,6 @@ i40e_dev_start(struct rte_eth_dev *dev) } /* Apply link configure */ - if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M | - ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G | - ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | - ETH_LINK_SPEED_40G)) { - PMD_DRV_LOG(ERR, "Invalid link setting"); - goto err_up; - } ret = i40e_apply_link_speed(dev); if (I40E_SUCCESS != ret) { PMD_DRV_LOG(ERR, "Fail to apply link setting"); @@ -2227,8 +2358,13 @@ i40e_dev_start(struct rte_eth_dev *dev) i40e_dev_link_update(dev, 0); } - /* enable uio intr after callback register */ - rte_intr_enable(intr_handle); + if (dev->data->dev_conf.intr_conf.rxq == 0) { + rte_eal_alarm_set(I40E_ALARM_INTERVAL, + i40e_dev_alarm_handler, dev); + } else { + /* enable uio intr after callback register */ + rte_intr_enable(intr_handle); + } i40e_filter_restore(pf); @@ -2258,6 +2394,12 @@ i40e_dev_stop(struct rte_eth_dev *dev) if (hw->adapter_stopped == 1) return; + + if (dev->data->dev_conf.intr_conf.rxq == 0) { + rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev); + rte_intr_enable(intr_handle); + } + /* Disable all queues */ i40e_dev_switch_queues(pf, FALSE); @@ -2340,6 +2482,8 @@ i40e_dev_close(struct rte_eth_dev *dev) i40e_pf_disable_irq0(hw); rte_intr_disable(intr_handle); + i40e_fdir_teardown(pf); + /* shutdown and destroy the HMC */ i40e_shutdown_lan_hmc(hw); @@ -2351,7 +2495,6 @@ i40e_dev_close(struct rte_eth_dev *dev) pf->vmdq = NULL; /* release all the existing VSIs and VEBs */ - i40e_fdir_teardown(pf); i40e_vsi_release(pf->main_vsi); /* shutdown the adminq */ @@ -2492,7 +2635,7 @@ i40e_dev_set_link_down(struct rte_eth_dev *dev) } static __rte_always_inline void -update_link_no_wait(struct i40e_hw *hw, struct rte_eth_link *link) +update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link) { /* Link status registers and values*/ #define I40E_PRTMAC_LINKSTA 0x001E2420 @@ -2513,7 +2656,7 @@ update_link_no_wait(struct i40e_hw *hw, struct rte_eth_link *link) reg_val &= I40E_REG_LINK_UP; link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0; - if (unlikely(link->link_status != 0)) + if (unlikely(link->link_status == 0)) return; /* Parse the link status */ @@ -2546,8 +2689,8 @@ update_link_no_wait(struct i40e_hw *hw, struct rte_eth_link *link) } static __rte_always_inline void -update_link_wait(struct i40e_hw *hw, struct rte_eth_link *link, - bool enable_lse) +update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link, + bool enable_lse, int wait_to_complete) { #define CHECK_INTERVAL 100 /* 100ms */ #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */ @@ -2571,8 +2714,8 @@ update_link_wait(struct i40e_hw *hw, struct rte_eth_link *link, } link->link_status = link_status.link_info & I40E_AQ_LINK_UP; - if (unlikely(link->link_status != 0)) - return; + if (!wait_to_complete || link->link_status) + break; rte_delay_ms(CHECK_INTERVAL); } while (--rep_cnt); @@ -2619,10 +2762,10 @@ i40e_dev_link_update(struct rte_eth_dev *dev, link.link_autoneg = !(dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED); - if (!wait_to_complete) - update_link_no_wait(hw, &link); + if (!wait_to_complete && !enable_lse) + update_link_reg(hw, &link); else - update_link_wait(hw, &link, enable_lse); + update_link_aq(hw, &link, enable_lse, wait_to_complete); ret = rte_eth_linkstatus_set(dev, &link); i40e_notify_all_vfs_link_status(dev); @@ -3296,12 +3439,13 @@ i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) DEV_RX_OFFLOAD_UDP_CKSUM | DEV_RX_OFFLOAD_TCP_CKSUM | DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | - DEV_RX_OFFLOAD_CRC_STRIP | + DEV_RX_OFFLOAD_KEEP_CRC | + DEV_RX_OFFLOAD_SCATTER | DEV_RX_OFFLOAD_VLAN_EXTEND | DEV_RX_OFFLOAD_VLAN_FILTER | DEV_RX_OFFLOAD_JUMBO_FRAME; - dev_info->tx_queue_offload_capa = 0; + dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE; dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT | @@ -3314,7 +3458,9 @@ i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) DEV_TX_OFFLOAD_VXLAN_TNL_TSO | DEV_TX_OFFLOAD_GRE_TNL_TSO | DEV_TX_OFFLOAD_IPIP_TNL_TSO | - DEV_TX_OFFLOAD_GENEVE_TNL_TSO; + DEV_TX_OFFLOAD_GENEVE_TNL_TSO | + DEV_TX_OFFLOAD_MULTI_SEGS | + dev_info->tx_queue_offload_capa; dev_info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; @@ -3343,8 +3489,7 @@ i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) }, .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH, .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH, - .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS | - ETH_TXQ_FLAGS_NOOFFLOADS, + .offloads = 0, }; dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { @@ -3457,7 +3602,8 @@ i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev, return 0; } - ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id), + ret = i40e_aq_debug_write_global_register(hw, + I40E_GL_SWT_L2TAGCTRL(reg_id), reg_w, NULL); if (ret != I40E_SUCCESS) { PMD_DRV_LOG(ERR, @@ -3507,7 +3653,7 @@ i40e_vlan_tpid_set(struct rte_eth_dev *dev, if (vlan_type == ETH_VLAN_TYPE_OUTER) hw->second_tag = rte_cpu_to_le_16(tpid); } - ret = i40e_aq_set_switch_config(hw, 0, 0, NULL); + ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL); if (ret != I40E_SUCCESS) { PMD_DRV_LOG(ERR, "Set switch config failed aq_err: %d", @@ -3518,7 +3664,6 @@ i40e_vlan_tpid_set(struct rte_eth_dev *dev, /* If NVM API < 1.7, keep the register setting */ ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type, tpid, qinq); - i40e_global_cfg_warning(I40E_WARNING_TPID); return ret; } @@ -3764,7 +3909,6 @@ i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW, pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] << I40E_KILOSHIFT); - i40e_global_cfg_warning(I40E_WARNING_FLOW_CTL); } else { PMD_DRV_LOG(ERR, "Water marker configuration is not supported."); @@ -4301,7 +4445,6 @@ i40e_get_cap(struct i40e_hw *hw) } #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4 -#define QUEUE_NUM_PER_VF_ARG "queue-num-per-vf" static int i40e_pf_parse_vf_queue_number_handler(const char *key, const char *value, @@ -4335,9 +4478,9 @@ static int i40e_pf_parse_vf_queue_number_handler(const char *key, static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev) { - static const char * const valid_keys[] = {QUEUE_NUM_PER_VF_ARG, NULL}; struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); struct rte_kvargs *kvlist; + int kvargs_count; /* set default queue number per VF as 4 */ pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF; @@ -4349,12 +4492,18 @@ static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev) if (kvlist == NULL) return -(EINVAL); - if (rte_kvargs_count(kvlist, QUEUE_NUM_PER_VF_ARG) > 1) + kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG); + if (!kvargs_count) { + rte_kvargs_free(kvlist); + return 0; + } + + if (kvargs_count > 1) PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only " "the first invalid or last valid one is used !", - QUEUE_NUM_PER_VF_ARG); + ETH_I40E_QUEUE_NUM_PER_VF_ARG); - rte_kvargs_process(kvlist, QUEUE_NUM_PER_VF_ARG, + rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG, i40e_pf_parse_vf_queue_number_handler, pf); rte_kvargs_free(kvlist); @@ -6479,6 +6628,53 @@ done: rte_intr_enable(dev->intr_handle); } +static void +i40e_dev_alarm_handler(void *param) +{ + struct rte_eth_dev *dev = (struct rte_eth_dev *)param; + struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); + uint32_t icr0; + + /* Disable interrupt */ + i40e_pf_disable_irq0(hw); + + /* read out interrupt causes */ + icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0); + + /* No interrupt event indicated */ + if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) + goto done; + if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK) + PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error"); + if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) + PMD_DRV_LOG(ERR, "ICR0: malicious programming detected"); + if (icr0 & I40E_PFINT_ICR0_GRST_MASK) + PMD_DRV_LOG(INFO, "ICR0: global reset requested"); + if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) + PMD_DRV_LOG(INFO, "ICR0: PCI exception activated"); + if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK) + PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state"); + if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) + PMD_DRV_LOG(ERR, "ICR0: HMC error"); + if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK) + PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error"); + + if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) { + PMD_DRV_LOG(INFO, "ICR0: VF reset detected"); + i40e_dev_handle_vfr_event(dev); + } + if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) { + PMD_DRV_LOG(INFO, "ICR0: adminq event"); + i40e_dev_handle_aq_msg(dev); + } + +done: + /* Enable interrupt */ + i40e_pf_enable_irq0(hw); + rte_eal_alarm_set(I40E_ALARM_INTERVAL, + i40e_dev_alarm_handler, dev); +} + int i40e_add_macvlan_filters(struct i40e_vsi *vsi, struct i40e_macvlan_filter *filter, @@ -7532,6 +7728,7 @@ i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf) struct i40e_aqc_replace_cloud_filters_cmd filter_replace; struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf; struct i40e_hw *hw = I40E_PF_TO_HW(pf); + struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev; enum i40e_status_code status = I40E_SUCCESS; if (pf->support_multi_driver) { @@ -7575,13 +7772,14 @@ i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf) status = i40e_aq_replace_cloud_filters(hw, &filter_replace, &filter_replace_buf); - if (!status) { - i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER); - PMD_DRV_LOG(DEBUG, "Global configuration modification: " - "cloud l1 type is changed from 0x%x to 0x%x", + if (!status && (filter_replace.old_filter_type != + filter_replace.new_filter_type)) + PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type." + " original: 0x%x, new: 0x%x", + dev->device->name, filter_replace.old_filter_type, filter_replace.new_filter_type); - } + return status; } @@ -7591,6 +7789,7 @@ i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf) struct i40e_aqc_replace_cloud_filters_cmd filter_replace; struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf; struct i40e_hw *hw = I40E_PF_TO_HW(pf); + struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev; enum i40e_status_code status = I40E_SUCCESS; if (pf->support_multi_driver) { @@ -7619,10 +7818,13 @@ i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf) &filter_replace_buf); if (status < 0) return status; - PMD_DRV_LOG(DEBUG, "Global configuration modification: " - "cloud filter type is changed from 0x%x to 0x%x", - filter_replace.old_filter_type, - filter_replace.new_filter_type); + if (filter_replace.old_filter_type != + filter_replace.new_filter_type) + PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type." + " original: 0x%x, new: 0x%x", + dev->device->name, + filter_replace.old_filter_type, + filter_replace.new_filter_type); /* For MPLSoGRE */ memset(&filter_replace, 0, @@ -7645,13 +7847,14 @@ i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf) status = i40e_aq_replace_cloud_filters(hw, &filter_replace, &filter_replace_buf); - if (!status) { - i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER); - PMD_DRV_LOG(DEBUG, "Global configuration modification: " - "cloud filter type is changed from 0x%x to 0x%x", + if (!status && (filter_replace.old_filter_type != + filter_replace.new_filter_type)) + PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type." + " original: 0x%x, new: 0x%x", + dev->device->name, filter_replace.old_filter_type, filter_replace.new_filter_type); - } + return status; } @@ -7661,6 +7864,7 @@ i40e_replace_gtp_l1_filter(struct i40e_pf *pf) struct i40e_aqc_replace_cloud_filters_cmd filter_replace; struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf; struct i40e_hw *hw = I40E_PF_TO_HW(pf); + struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev; enum i40e_status_code status = I40E_SUCCESS; if (pf->support_multi_driver) { @@ -7696,10 +7900,13 @@ i40e_replace_gtp_l1_filter(struct i40e_pf *pf) &filter_replace_buf); if (status < 0) return status; - PMD_DRV_LOG(DEBUG, "Global configuration modification: " - "cloud l1 type is changed from 0x%x to 0x%x", - filter_replace.old_filter_type, - filter_replace.new_filter_type); + if (filter_replace.old_filter_type != + filter_replace.new_filter_type) + PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type." + " original: 0x%x, new: 0x%x", + dev->device->name, + filter_replace.old_filter_type, + filter_replace.new_filter_type); /* for GTP-U */ memset(&filter_replace, 0, @@ -7728,13 +7935,14 @@ i40e_replace_gtp_l1_filter(struct i40e_pf *pf) status = i40e_aq_replace_cloud_filters(hw, &filter_replace, &filter_replace_buf); - if (!status) { - i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER); - PMD_DRV_LOG(DEBUG, "Global configuration modification: " - "cloud l1 type is changed from 0x%x to 0x%x", + if (!status && (filter_replace.old_filter_type != + filter_replace.new_filter_type)) + PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type." + " original: 0x%x, new: 0x%x", + dev->device->name, filter_replace.old_filter_type, filter_replace.new_filter_type); - } + return status; } @@ -7744,6 +7952,7 @@ i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf) struct i40e_aqc_replace_cloud_filters_cmd filter_replace; struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf; struct i40e_hw *hw = I40E_PF_TO_HW(pf); + struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev; enum i40e_status_code status = I40E_SUCCESS; if (pf->support_multi_driver) { @@ -7771,10 +7980,13 @@ i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf) &filter_replace_buf); if (status < 0) return status; - PMD_DRV_LOG(DEBUG, "Global configuration modification: " - "cloud filter type is changed from 0x%x to 0x%x", - filter_replace.old_filter_type, - filter_replace.new_filter_type); + if (filter_replace.old_filter_type != + filter_replace.new_filter_type) + PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type." + " original: 0x%x, new: 0x%x", + dev->device->name, + filter_replace.old_filter_type, + filter_replace.new_filter_type); /* for GTP-U */ memset(&filter_replace, 0, @@ -7796,13 +8008,14 @@ i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf) status = i40e_aq_replace_cloud_filters(hw, &filter_replace, &filter_replace_buf); - if (!status) { - i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER); - PMD_DRV_LOG(DEBUG, "Global configuration modification: " - "cloud filter type is changed from 0x%x to 0x%x", + if (!status && (filter_replace.old_filter_type != + filter_replace.new_filter_type)) + PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type." + " original: 0x%x, new: 0x%x", + dev->device->name, filter_replace.old_filter_type, filter_replace.new_filter_type); - } + return status; } @@ -8354,14 +8567,14 @@ i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len) } if (reg != val) { - ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2), + ret = i40e_aq_debug_write_global_register(hw, + I40E_GL_PRS_FVBM(2), reg, NULL); if (ret != 0) return ret; PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed " "with value 0x%08x", I40E_GL_PRS_FVBM(2), reg); - i40e_global_cfg_warning(I40E_WARNING_GRE_KEY_LEN); } else { ret = 0; } @@ -8627,7 +8840,6 @@ i40e_set_hash_filter_global_config(struct i40e_hw *hw, I40E_GLQF_HSYM(j), reg); } - i40e_global_cfg_warning(I40E_WARNING_HSYM); } } @@ -8653,7 +8865,6 @@ i40e_set_hash_filter_global_config(struct i40e_hw *hw, goto out; i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg); - i40e_global_cfg_warning(I40E_WARNING_QF_CTL); out: I40E_WRITE_FLUSH(hw); @@ -9246,12 +9457,17 @@ void i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val) { uint32_t reg = i40e_read_rx_ctl(hw, addr); + struct rte_eth_dev *dev; - PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg); - if (reg != val) - i40e_write_global_rx_ctl(hw, addr, val); - PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr, - (uint32_t)i40e_read_rx_ctl(hw, addr)); + dev = ((struct i40e_adapter *)hw->back)->eth_dev; + if (reg != val) { + i40e_write_rx_ctl(hw, addr, val); + PMD_DRV_LOG(WARNING, + "i40e device %s changed global register [0x%08x]." + " original: 0x%08x, new: 0x%08x", + dev->device->name, addr, reg, + (uint32_t)i40e_read_rx_ctl(hw, addr)); + } } static void @@ -9325,12 +9541,6 @@ i40e_filter_input_set_init(struct i40e_pf *pf) pf->hash_input_set[pctype] = input_set; pf->fdir.input_set[pctype] = input_set; } - - if (!pf->support_multi_driver) { - i40e_global_cfg_warning(I40E_WARNING_HASH_INSET); - i40e_global_cfg_warning(I40E_WARNING_FD_MSK); - i40e_global_cfg_warning(I40E_WARNING_HASH_MSK); - } } int @@ -9396,7 +9606,6 @@ i40e_hash_filter_inset_select(struct i40e_hw *hw, i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype), (uint32_t)((inset_reg >> I40E_32_BIT_WIDTH) & UINT32_MAX)); - i40e_global_cfg_warning(I40E_WARNING_HASH_INSET); for (i = 0; i < num; i++) i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype), @@ -9405,7 +9614,6 @@ i40e_hash_filter_inset_select(struct i40e_hw *hw, for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype), 0); - i40e_global_cfg_warning(I40E_WARNING_HASH_MSK); I40E_WRITE_FLUSH(hw); pf->hash_input_set[pctype] = input_set; @@ -9486,7 +9694,6 @@ i40e_fdir_filter_inset_select(struct i40e_pf *pf, i40e_check_write_global_reg(hw, I40E_GLQF_FD_MSK(i, pctype), 0); - i40e_global_cfg_warning(I40E_WARNING_FD_MSK); } else { PMD_DRV_LOG(ERR, "FDIR bit mask is not supported."); } @@ -9969,6 +10176,60 @@ i40e_pctype_to_flowtype(const struct i40e_adapter *adapter, #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606 #define I40E_GL_SWR_PM_UP_THR 0x269FBC +/* + * GL_SWR_PM_UP_THR: + * The value is not impacted from the link speed, its value is set according + * to the total number of ports for a better pipe-monitor configuration. + */ +static bool +i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value) +{ +#define I40E_GL_SWR_PM_EF_DEVICE(dev) \ + .device_id = (dev), \ + .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE + +#define I40E_GL_SWR_PM_SF_DEVICE(dev) \ + .device_id = (dev), \ + .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE + + static const struct { + uint16_t device_id; + uint32_t val; + } swr_pm_table[] = { + { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) }, + { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) }, + { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) }, + { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) }, + + { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) }, + { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) }, + { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) }, + { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) }, + { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) }, + { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) }, + { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) }, + }; + uint32_t i; + + if (value == NULL) { + PMD_DRV_LOG(ERR, "value is NULL"); + return false; + } + + for (i = 0; i < RTE_DIM(swr_pm_table); i++) { + if (hw->device_id == swr_pm_table[i].device_id) { + *value = swr_pm_table[i].val; + + PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR " + "value - 0x%08x", + hw->device_id, *value); + return true; + } + } + + return false; +} + static int i40e_dev_sync_phy_type(struct i40e_hw *hw) { @@ -10033,13 +10294,16 @@ i40e_configure_registers(struct i40e_hw *hw) } if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) { - if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */ - I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */ - reg_table[i].val = - I40E_GL_SWR_PM_UP_THR_SF_VALUE; - else /* For X710 */ - reg_table[i].val = - I40E_GL_SWR_PM_UP_THR_EF_VALUE; + uint32_t cfg_val; + + if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) { + PMD_DRV_LOG(DEBUG, "Device 0x%x skips " + "GL_SWR_PM_UP_THR value fixup", + hw->device_id); + continue; + } + + reg_table[i].val = cfg_val; } ret = i40e_aq_debug_read_register(hw, reg_table[i].addr, @@ -11108,6 +11372,16 @@ i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb) * LLDP MIB change event. */ if (sw_dcb == TRUE) { + /* When using NVM 6.01 or later, the RX data path does + * not hang if the FW LLDP is stopped. + */ + if (((hw->nvm.version >> 12) & 0xf) >= 6 && + ((hw->nvm.version >> 4) & 0xff) >= 1) { + ret = i40e_aq_stop_lldp(hw, TRUE, NULL); + if (ret != I40E_SUCCESS) + PMD_INIT_LOG(DEBUG, "Failed to stop lldp"); + } + ret = i40e_init_dcb(hw); /* If lldp agent is stopped, the return value from * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM @@ -12036,7 +12310,8 @@ i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg, ptype_mapping[i].sw_ptype |= RTE_PTYPE_TUNNEL_GRENAT; in_tunnel = true; - } else if (!strncasecmp(name, "L2TPV2CTL", 9)) { + } else if (!strncasecmp(name, "L2TPV2CTL", 9) || + !strncasecmp(name, "L2TPV2", 6)) { ptype_mapping[i].sw_ptype |= RTE_PTYPE_TUNNEL_L2TP; in_tunnel = true; @@ -12180,6 +12455,7 @@ i40e_cloud_filter_qinq_create(struct i40e_pf *pf) struct i40e_aqc_replace_cloud_filters_cmd filter_replace; struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf; struct i40e_hw *hw = I40E_PF_TO_HW(pf); + struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev; if (pf->support_multi_driver) { PMD_DRV_LOG(ERR, "Replace cloud filter is not supported."); @@ -12216,10 +12492,14 @@ i40e_cloud_filter_qinq_create(struct i40e_pf *pf) &filter_replace_buf); if (ret != I40E_SUCCESS) return ret; - PMD_DRV_LOG(DEBUG, "Global configuration modification: " - "cloud l1 type is changed from 0x%x to 0x%x", - filter_replace.old_filter_type, - filter_replace.new_filter_type); + + if (filter_replace.old_filter_type != + filter_replace.new_filter_type) + PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type." + " original: 0x%x, new: 0x%x", + dev->device->name, + filter_replace.old_filter_type, + filter_replace.new_filter_type); /* Apply the second L2 cloud filter */ memset(&filter_replace, 0, @@ -12241,13 +12521,14 @@ i40e_cloud_filter_qinq_create(struct i40e_pf *pf) I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; ret = i40e_aq_replace_cloud_filters(hw, &filter_replace, &filter_replace_buf); - if (!ret) { - i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER); - PMD_DRV_LOG(DEBUG, "Global configuration modification: " - "cloud filter type is changed from 0x%x to 0x%x", + if (!ret && (filter_replace.old_filter_type != + filter_replace.new_filter_type)) + PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type." + " original: 0x%x, new: 0x%x", + dev->device->name, filter_replace.old_filter_type, filter_replace.new_filter_type); - } + return ret; } @@ -12365,9 +12646,7 @@ i40e_config_rss_filter(struct i40e_pf *pf, return 0; } -RTE_INIT(i40e_init_log); -static void -i40e_init_log(void) +RTE_INIT(i40e_init_log) { i40e_logtype_init = rte_log_register("pmd.net.i40e.init"); if (i40e_logtype_init >= 0) @@ -12378,5 +12657,8 @@ i40e_init_log(void) } RTE_PMD_REGISTER_PARAM_STRING(net_i40e, - QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16" - ETH_I40E_SUPPORT_MULTI_DRIVER "=1"); + ETH_I40E_FLOATING_VEB_ARG "=1" + ETH_I40E_FLOATING_VEB_LIST_ARG "=" + ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16" + ETH_I40E_SUPPORT_MULTI_DRIVER "=1" + ETH_I40E_USE_LATEST_VEC "=0|1");