X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fiavf%2Fbase%2Fiavf_type.h;h=6f85f8c0453dc1eccf9a993b2722c176cf9f5455;hb=03ef7d47f7bbf441000691105bfd411aa6929a4b;hp=c1910ff758ab8c0a61f6e5baa6e81e2111291dc5;hpb=9e54112f822a241ccf14c05a5ffe720d85f32214;p=dpdk.git

diff --git a/drivers/net/iavf/base/iavf_type.h b/drivers/net/iavf/base/iavf_type.h
index c1910ff758..6f85f8c045 100644
--- a/drivers/net/iavf/base/iavf_type.h
+++ b/drivers/net/iavf/base/iavf_type.h
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2013 - 2015 Intel Corporation
+ * Copyright(c) 2001-2019
  */
 
 #ifndef _IAVF_TYPE_H_
@@ -11,7 +11,7 @@
 #include "iavf_adminq.h"
 #include "iavf_devids.h"
 
-#define IAVF_RXQ_CTX_DBUFF_SHIFT        7
+#define IAVF_RXQ_CTX_DBUFF_SHIFT	7
 
 #define UNREFERENCED_XPARAMETER
 #define UNREFERENCED_1PARAMETER(_p) (_p);
@@ -30,7 +30,7 @@
 #define IAVF_MAX_PF_VSI			64
 #define IAVF_MAX_PF_QP			128
 #define IAVF_MAX_VSI_QP			16
-#define IAVF_MAX_VF_VSI			3
+#define IAVF_MAX_VF_VSI			4
 #define IAVF_MAX_CHAINED_RX_BUFFERS	5
 
 /* something less than 1 minute */
@@ -332,7 +332,6 @@ struct iavf_hw {
 	u16 subsystem_device_id;
 	u16 subsystem_vendor_id;
 	u8 revision_id;
-	bool adapter_stopped;
 
 	/* capabilities for entire device and PCI func */
 	struct iavf_hw_capabilities dev_caps;
@@ -467,20 +466,20 @@ enum iavf_rx_desc_status_bits {
 	IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT	= 12, /* 2 BITS */
 	IAVF_RX_DESC_STATUS_LPBK_SHIFT		= 14,
 	IAVF_RX_DESC_STATUS_IPV6EXADD_SHIFT	= 15,
-	IAVF_RX_DESC_STATUS_RESERVED2_SHIFT	= 16, /* 2 BITS */
+	IAVF_RX_DESC_STATUS_RESERVED_SHIFT	= 16, /* 2 BITS */
 	IAVF_RX_DESC_STATUS_INT_UDP_0_SHIFT	= 18,
 	IAVF_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 };
 
 #define IAVF_RXD_QW1_STATUS_SHIFT	0
-#define IAVF_RXD_QW1_STATUS_MASK	((BIT(IAVF_RX_DESC_STATUS_LAST) - 1) << \
-					 IAVF_RXD_QW1_STATUS_SHIFT)
+#define IAVF_RXD_QW1_STATUS_MASK	((BIT(IAVF_RX_DESC_STATUS_LAST) - 1) \
+					 << IAVF_RXD_QW1_STATUS_SHIFT)
 
-#define IAVF_RXD_QW1_STATUS_TSYNINDX_SHIFT   IAVF_RX_DESC_STATUS_TSYNINDX_SHIFT
-#define IAVF_RXD_QW1_STATUS_TSYNINDX_MASK	(0x3UL << \
-					     IAVF_RXD_QW1_STATUS_TSYNINDX_SHIFT)
+#define IAVF_RXD_QW1_STATUS_TSYNINDX_SHIFT IAVF_RX_DESC_STATUS_TSYNINDX_SHIFT
+#define IAVF_RXD_QW1_STATUS_TSYNINDX_MASK  (0x3UL << \
+					    IAVF_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 
-#define IAVF_RXD_QW1_STATUS_TSYNVALID_SHIFT  IAVF_RX_DESC_STATUS_TSYNVALID_SHIFT
+#define IAVF_RXD_QW1_STATUS_TSYNVALID_SHIFT IAVF_RX_DESC_STATUS_TSYNVALID_SHIFT
 #define IAVF_RXD_QW1_STATUS_TSYNVALID_MASK   BIT_ULL(IAVF_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 
 #define IAVF_RXD_QW1_STATUS_UMBCAST_SHIFT	IAVF_RX_DESC_STATUS_UMBCAST
@@ -892,7 +891,8 @@ enum iavf_tx_ctx_desc_eipt_offload {
 #define IAVF_TXD_CTX_GRE_TUNNELING	(0x2ULL << IAVF_TXD_CTX_QW0_NATT_SHIFT)
 
 #define IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT	11
-#define IAVF_TXD_CTX_QW0_EIP_NOINC_MASK	BIT_ULL(IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT)
+#define IAVF_TXD_CTX_QW0_EIP_NOINC_MASK \
+				       BIT_ULL(IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT)
 
 #define IAVF_TXD_CTX_EIP_NOINC_IPID_CONST	IAVF_TXD_CTX_QW0_EIP_NOINC_MASK