X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fice%2Fbase%2Fice_adminq_cmd.h;h=34c05815f3e8f173969279c00e4c244a85cdec09;hb=486d29fda54c362ec3a96ab13327064458de0b03;hp=cc42180eac834cf2202ece2ca706370c9b1fe8e8;hpb=d13ad9cf1721cc84b4507c5e4ce96001155b9f4a;p=dpdk.git diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h index cc42180eac..34c05815f3 100644 --- a/drivers/net/ice/base/ice_adminq_cmd.h +++ b/drivers/net/ice/base/ice_adminq_cmd.h @@ -9,12 +9,10 @@ * descriptor format. It is shared between Firmware and Software. */ - #define ICE_MAX_VSI 768 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 - struct ice_aqc_generic { __le32 param0; __le32 param1; @@ -22,7 +20,6 @@ struct ice_aqc_generic { __le32 addr_low; }; - /* Get version (direct 0x0001) */ struct ice_aqc_get_ver { __le32 rom_ver; @@ -37,7 +34,6 @@ struct ice_aqc_get_ver { u8 api_patch; }; - /* Send driver version (indirect 0x0002) */ struct ice_aqc_driver_ver { u8 major_ver; @@ -49,7 +45,6 @@ struct ice_aqc_driver_ver { __le32 addr_low; }; - /* Queue Shutdown (direct 0x0003) */ struct ice_aqc_q_shutdown { u8 driver_unloading; @@ -57,9 +52,6 @@ struct ice_aqc_q_shutdown { u8 reserved[15]; }; - - - /* Request resource ownership (direct 0x0008) * Release resource ownership (direct 0x0009) */ @@ -92,7 +84,6 @@ struct ice_aqc_req_res { u8 reserved[2]; }; - /* Get function capabilities (indirect 0x000A) * Get device capabilities (indirect 0x000B) */ @@ -105,7 +96,6 @@ struct ice_aqc_list_caps { __le32 addr_low; }; - /* Device/Function buffer entry, repeated per reported capability */ struct ice_aqc_list_caps_elem { __le16 cap; @@ -132,7 +122,6 @@ struct ice_aqc_list_caps_elem { __le64 rsvd2; }; - /* Manage MAC address, read command - indirect (0x0107) * This struct is also used for the response */ @@ -153,7 +142,6 @@ struct ice_aqc_manage_mac_read { __le32 addr_low; }; - /* Response buffer format for manage MAC read command */ struct ice_aqc_manage_mac_read_resp { u8 lport_num; @@ -163,7 +151,6 @@ struct ice_aqc_manage_mac_read_resp { u8 mac_addr[ETH_ALEN]; }; - /* Manage MAC address, write command - direct (0x0108) */ struct ice_aqc_manage_mac_write { u8 rsvd; @@ -182,7 +169,6 @@ struct ice_aqc_manage_mac_write { __le32 addr_low; }; - /* Clear PXE Command and response (direct 0x0110) */ struct ice_aqc_clear_pxe { u8 rx_cnt; @@ -190,7 +176,6 @@ struct ice_aqc_clear_pxe { u8 reserved[15]; }; - /* Configure No-Drop Policy Command (direct 0x0112) */ struct ice_aqc_config_no_drop_policy { u8 opts; @@ -215,7 +200,6 @@ struct ice_aqc_get_sw_cfg { __le32 addr_low; }; - /* Each entry in the response buffer is of the following type: */ struct ice_aqc_get_sw_cfg_resp_elem { /* VSI/Port Number */ @@ -242,7 +226,6 @@ struct ice_aqc_get_sw_cfg_resp_elem { #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) }; - /* The response buffer is as follows. Note that the length of the * elements array varies with the length of the command response. */ @@ -250,8 +233,6 @@ struct ice_aqc_get_sw_cfg_resp { struct ice_aqc_get_sw_cfg_resp_elem elements[1]; }; - - /* These resource type defines are used for all switch resource * commands where a resource type is required, such as: * Get Resource Allocation command (indirect 0x0204) @@ -324,7 +305,6 @@ struct ice_aqc_get_res_resp { struct ice_aqc_get_res_resp_elem elem[1]; }; - /* Allocate Resources command (indirect 0x0208) * Free Resources command (indirect 0x0209) */ @@ -335,7 +315,6 @@ struct ice_aqc_alloc_free_res_cmd { __le32 addr_low; }; - /* Resource descriptor */ struct ice_aqc_res_elem { union { @@ -344,7 +323,6 @@ struct ice_aqc_res_elem { } e; }; - /* Buffer for Allocate/Free Resources commands */ struct ice_aqc_alloc_free_res_elem { __le16 res_type; /* Types defined above cmd 0x0204 */ @@ -355,7 +333,6 @@ struct ice_aqc_alloc_free_res_elem { struct ice_aqc_res_elem elem[1]; }; - /* Get Allocated Resource Descriptors Command (indirect 0x020A) */ struct ice_aqc_get_allocd_res_desc { union { @@ -379,7 +356,6 @@ struct ice_aqc_get_allocd_res_desc_resp { struct ice_aqc_res_elem elem[1]; }; - /* Add VSI (indirect 0x0210) * Update VSI (indirect 0x0211) * Get VSI (indirect 0x0212) @@ -405,7 +381,6 @@ struct ice_aqc_add_get_update_free_vsi { __le32 addr_low; }; - /* Response descriptor for: * Add VSI (indirect 0x0210) * Update VSI (indirect 0x0211) @@ -420,7 +395,6 @@ struct ice_aqc_add_update_free_vsi_resp { __le32 addr_low; }; - struct ice_aqc_get_vsi_resp { __le16 vsi_num; u8 vf_id; @@ -434,7 +408,6 @@ struct ice_aqc_get_vsi_resp { __le32 addr_low; }; - struct ice_aqc_vsi_props { __le16 valid_sections; #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) @@ -589,7 +562,6 @@ struct ice_aqc_vsi_props { u8 reserved[24]; }; - /* Add/update mirror rule - direct (0x0260) */ #define ICE_AQC_RULE_ID_VALID_S 7 #define ICE_AQC_RULE_ID_VALID_M (0x1 << ICE_AQC_RULE_ID_VALID_S) @@ -694,7 +666,6 @@ struct ice_aqc_storm_cfg { __le32 reserved; }; - #define ICE_MAX_NUM_RECIPES 64 /* Add/Get Recipe (indirect 0x0290/0x0292)*/ @@ -779,7 +750,6 @@ struct ice_aqc_sw_rules { __le32 addr_low; }; - #pragma pack(1) /* Add/Update/Get/Remove lookup Rx/Tx command/response entry * This structures describes the lookup rules and associated actions. "index" @@ -867,7 +837,6 @@ struct ice_sw_rule_lkup_rx_tx { }; #pragma pack() - /* Add/Update/Remove large action command/response entry * "index" is returned as part of a response to a successful Add command, and * can be used to identify the action for Update/Get/Remove commands. @@ -928,7 +897,6 @@ struct ice_sw_rule_lg_act { #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) }; - /* Add/Update/Remove VSI list command/response entry * "index" is returned as part of a response to a successful Add command, and * can be used to identify the VSI list for Update/Get/Remove commands. @@ -939,7 +907,6 @@ struct ice_sw_rule_vsi_list { __le16 vsi[1]; /* Array of number_vsi VSI numbers */ }; - #pragma pack(1) /* Query VSI list command/response entry */ struct ice_sw_rule_vsi_list_query { @@ -948,7 +915,6 @@ struct ice_sw_rule_vsi_list_query { }; #pragma pack() - #pragma pack(1) /* Add switch rule response: * Content of return buffer is same as the input buffer. The status field and @@ -974,7 +940,6 @@ struct ice_aqc_sw_rules_elem { #pragma pack() - /* PFC Ignore (direct 0x0301) * The command and response use the same descriptor structure */ @@ -1009,7 +974,6 @@ struct ice_aqc_set_dcb_params { u8 rsvd[14]; }; - /* Get Default Topology (indirect 0x0400) */ struct ice_aqc_get_topo { u8 port_num; @@ -1020,7 +984,6 @@ struct ice_aqc_get_topo { __le32 addr_low; }; - /* Update TSE (indirect 0x0403) * Get TSE (indirect 0x0404) * Add TSE (indirect 0x0401) @@ -1037,7 +1000,6 @@ struct ice_aqc_sched_elem_cmd { __le32 addr_low; }; - /* This is the buffer for: * Suspend Nodes (indirect 0x0409) * Resume Nodes (indirect 0x040A) @@ -1046,7 +1008,6 @@ struct ice_aqc_suspend_resume_elem { __le32 teid[1]; }; - struct ice_aqc_txsched_move_grp_info_hdr { __le32 src_parent_teid; __le32 dest_parent_teid; @@ -1054,19 +1015,16 @@ struct ice_aqc_txsched_move_grp_info_hdr { __le16 reserved; }; - struct ice_aqc_move_elem { struct ice_aqc_txsched_move_grp_info_hdr hdr; __le32 teid[1]; }; - struct ice_aqc_elem_info_bw { __le16 bw_profile_idx; __le16 bw_alloc; }; - struct ice_aqc_txsched_elem { u8 elem_type; /* Special field, reserved for some aq calls */ #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 @@ -1098,50 +1056,42 @@ struct ice_aqc_txsched_elem { __le16 reserved2; }; - struct ice_aqc_txsched_elem_data { __le32 parent_teid; __le32 node_teid; struct ice_aqc_txsched_elem data; }; - struct ice_aqc_txsched_topo_grp_info_hdr { __le32 parent_teid; __le16 num_elems; __le16 reserved2; }; - struct ice_aqc_add_elem { struct ice_aqc_txsched_topo_grp_info_hdr hdr; struct ice_aqc_txsched_elem_data generic[1]; }; - struct ice_aqc_conf_elem { struct ice_aqc_txsched_elem_data generic[1]; }; - struct ice_aqc_get_elem { struct ice_aqc_txsched_elem_data generic[1]; }; - struct ice_aqc_get_topo_elem { struct ice_aqc_txsched_topo_grp_info_hdr hdr; struct ice_aqc_txsched_elem_data generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; }; - struct ice_aqc_delete_elem { struct ice_aqc_txsched_topo_grp_info_hdr hdr; __le32 teid[1]; }; - /* Query Port ETS (indirect 0x040E) * * This indirect command is used to query port TC node configuration. @@ -1168,7 +1118,6 @@ struct ice_aqc_port_ets_elem { __le32 tc_node_teid[8]; /* Used for response, reserved in command */ }; - /* Rate limiting profile for * Add RL profile (indirect 0x0410) * Query RL profile (indirect 0x0411) @@ -1184,7 +1133,6 @@ struct ice_aqc_rl_profile { __le32 addr_low; }; - struct ice_aqc_rl_profile_elem { u8 level; u8 flags; @@ -1204,13 +1152,10 @@ struct ice_aqc_rl_profile_elem { __le16 rl_encode; }; - struct ice_aqc_rl_profile_generic_elem { struct ice_aqc_rl_profile_elem generic[1]; }; - - /* Configure L2 Node CGD (indirect 0x0414) * This indirect command allows configuring a congestion domain for given L2 * node TEIDs in the scheduler topology. @@ -1222,19 +1167,16 @@ struct ice_aqc_cfg_l2_node_cgd { __le32 addr_low; }; - struct ice_aqc_cfg_l2_node_cgd_elem { __le32 node_teid; u8 cgd; u8 reserved[3]; }; - struct ice_aqc_cfg_l2_node_cgd_data { struct ice_aqc_cfg_l2_node_cgd_elem elem[1]; }; - /* Query Scheduler Resource Allocation (indirect 0x0412) * This indirect command retrieves the scheduler resources allocated by * EMP Firmware to the given PF. @@ -1245,7 +1187,6 @@ struct ice_aqc_query_txsched_res { __le32 addr_low; }; - struct ice_aqc_generic_sched_props { __le16 phys_levels; __le16 logical_levels; @@ -1257,7 +1198,6 @@ struct ice_aqc_generic_sched_props { u8 rsvd1[22]; }; - struct ice_aqc_layer_props { u8 logical_layer; u8 chunk_size; @@ -1271,13 +1211,11 @@ struct ice_aqc_layer_props { u8 rsvd1[14]; }; - struct ice_aqc_query_txsched_res_resp { struct ice_aqc_generic_sched_props sched_props; struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; }; - /* Query Node to Root Topology (indirect 0x0413) * This command uses ice_aqc_get_elem as its data buffer. */ @@ -1288,7 +1226,6 @@ struct ice_aqc_query_node_to_root { __le32 addr_low; }; - /* Get PHY capabilities (indirect 0x0600) */ struct ice_aqc_get_phy_caps { u8 lport_num; @@ -1311,7 +1248,6 @@ struct ice_aqc_get_phy_caps { __le32 addr_low; }; - /* This is #define of PHY type (Extended): * The first set of defines is for phy_type_low. */ @@ -1427,7 +1363,8 @@ struct ice_aqc_get_phy_caps_data { #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) #define ICE_AQC_PHY_FEC_MASK MAKEMASK(0xdf, 0) - u8 rsvd1; /* Byte 35 reserved */ + u8 module_compliance_enforcement; +#define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0) u8 extended_compliance_code; #define ICE_MODULE_TYPE_TOTAL_BYTE 3 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; @@ -1453,7 +1390,6 @@ struct ice_aqc_get_phy_caps_data { } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; }; - /* Set PHY capabilities (direct 0x0601) * NOTE: This command must be followed by setup link and restart auto-neg */ @@ -1464,7 +1400,6 @@ struct ice_aqc_set_phy_cfg { __le32 addr_low; }; - /* Set PHY config command data structure */ struct ice_aqc_set_phy_cfg_data { __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ @@ -1482,10 +1417,9 @@ struct ice_aqc_set_phy_cfg_data { __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */ __le16 eeer_value; u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */ - u8 rsvd1; + u8 module_compliance_enforcement; }; - /* Set MAC Config command data structure (direct 0x0603) */ struct ice_aqc_set_mac_cfg { __le16 max_frame_size; @@ -1505,7 +1439,6 @@ struct ice_aqc_set_mac_cfg { u8 reserved[7]; }; - /* Restart AN command data structure (direct 0x0605) * Also used for response, with only the lport_num field present. */ @@ -1518,7 +1451,6 @@ struct ice_aqc_restart_an { u8 reserved2[13]; }; - /* Get link status (indirect 0x0607), also used for Link Status Event */ struct ice_aqc_get_link_status { u8 lport_num; @@ -1535,7 +1467,6 @@ struct ice_aqc_get_link_status { __le32 addr_low; }; - /* Get link status response data structure, also used for Link Status Event */ struct ice_aqc_get_link_status_data { u8 topo_media_conflict; @@ -1575,7 +1506,12 @@ struct ice_aqc_get_link_status_data { #define ICE_AQ_LINK_TX_ACTIVE 0 #define ICE_AQ_LINK_TX_DRAINED 1 #define ICE_AQ_LINK_TX_FLUSHED 3 - u8 reserved2; + u8 lb_status; +#define ICE_AQ_LINK_LB_PHY_LCL BIT(0) +#define ICE_AQ_LINK_LB_PHY_RMT BIT(1) +#define ICE_AQ_LINK_LB_MAC_LCL BIT(2) +#define ICE_AQ_LINK_LB_PHY_IDX_S 3 +#define ICE_AQ_LINK_LB_PHY_IDX_M (0x7 << ICE_AQ_LB_PHY_IDX_S) __le16 max_frame_size; u8 cfg; #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) @@ -1616,7 +1552,6 @@ struct ice_aqc_get_link_status_data { __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ }; - /* Set event mask command (direct 0x0613) */ struct ice_aqc_set_event_mask { u8 lport_num; @@ -1631,11 +1566,11 @@ struct ice_aqc_set_event_mask { #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7) #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) +#define ICE_AQ_LINK_EVENT_TOPO_CONFLICT BIT(10) +#define ICE_AQ_LINK_EVENT_MEDIA_CONFLICT BIT(11) u8 reserved1[6]; }; - - /* Set MAC Loopback command (direct 0x0620) */ struct ice_aqc_set_mac_lb { u8 lb_mode; @@ -1644,9 +1579,56 @@ struct ice_aqc_set_mac_lb { u8 reserved[15]; }; - - - +struct ice_aqc_link_topo_addr { + u8 lport_num; + u8 lport_num_valid; +#define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0) + u8 node_type_ctx; +#define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0 +#define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S) +#define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0 +#define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1 +#define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2 +#define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3 +#define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4 +#define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5 +#define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6 +#define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7 +#define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8 +#define ICE_AQC_LINK_TOPO_NODE_CTX_S 4 +#define ICE_AQC_LINK_TOPO_NODE_CTX_M \ + (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S) +#define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0 +#define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1 +#define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2 +#define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3 +#define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4 +#define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5 + u8 index; + __le16 handle; +#define ICE_AQC_LINK_TOPO_HANDLE_S 0 +#define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S) +/* Used to decode the handle field */ +#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9) +#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9) +#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0 +#define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0 +/* In case of a Mezzanine type */ +#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \ + (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) +#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6 +#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S) +/* In case of a LOM type */ +#define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \ + (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) +}; + +/* Get Link Topology Handle (direct, 0x06E0) */ +struct ice_aqc_get_link_topo { + struct ice_aqc_link_topo_addr addr; + u8 node_part_num; + u8 rsvd[9]; +}; /* Set Port Identification LED (direct, 0x06E9) */ struct ice_aqc_set_port_id_led { @@ -1659,8 +1641,6 @@ struct ice_aqc_set_port_id_led { u8 rsvd[13]; }; - - /* Read/Write SFF EEPROM command (indirect 0x06EE) */ struct ice_aqc_sff_eeprom { u8 lport_num; @@ -1690,20 +1670,27 @@ struct ice_aqc_sff_eeprom { /* NVM Read command (indirect 0x0701) * NVM Erase commands (direct 0x0702) - * NVM Update commands (indirect 0x0703) + * NVM Write commands (indirect 0x0703) + * NVM Write Activate commands (direct 0x0707) + * NVM Shadow RAM Dump commands (direct 0x0707) */ struct ice_aqc_nvm { __le16 offset_low; u8 offset_high; u8 cmd_flags; #define ICE_AQC_NVM_LAST_CMD BIT(0) -#define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */ -#define ICE_AQC_NVM_PRESERVATION_S 1 +#define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Write reply */ +#define ICE_AQC_NVM_PRESERVATION_S 1 /* Used by NVM Write Activate only */ #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S) #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S) #define ICE_AQC_NVM_PRESERVE_ALL BIT(1) #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S) #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S) +#define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */ +#define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4) +#define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5) +#define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6) +#define ICE_AQC_NVM_ACTIV_SEL_MASK MAKEMASK(0x7, 3) #define ICE_AQC_NVM_FLASH_ONLY BIT(7) __le16 module_typeid; __le16 length; @@ -1734,6 +1721,31 @@ struct ice_aqc_nvm { #define ICE_AQC_NVM_LLDP_STATUS_M_LEN 4 /* In Bits */ #define ICE_AQC_NVM_LLDP_STATUS_RD_LEN 4 /* In Bytes */ +/* The result of netlist NVM read comes in a TLV format. The actual data + * (netlist header) starts from word offset 1 (byte 2). The FW strips + * out the type field from the TLV header so all the netlist fields + * should adjust their offset value by 1 word (2 bytes) in order to map + * their correct location. + */ +#define ICE_AQC_NVM_LINK_TOPO_NETLIST_MOD_ID 0x11B +#define ICE_AQC_NVM_LINK_TOPO_NETLIST_LEN_OFFSET 1 +#define ICE_AQC_NVM_LINK_TOPO_NETLIST_LEN 2 /* In bytes */ +#define ICE_AQC_NVM_NETLIST_NODE_COUNT_OFFSET 2 +#define ICE_AQC_NVM_NETLIST_NODE_COUNT_LEN 2 /* In bytes */ +#define ICE_AQC_NVM_NETLIST_ID_BLK_START_OFFSET 5 +#define ICE_AQC_NVM_NETLIST_ID_BLK_LEN 0x30 /* In words */ + +/* netlist ID block field offsets (word offsets) */ +#define ICE_AQC_NVM_NETLIST_ID_BLK_MAJOR_VER_LOW 2 +#define ICE_AQC_NVM_NETLIST_ID_BLK_MAJOR_VER_HIGH 3 +#define ICE_AQC_NVM_NETLIST_ID_BLK_MINOR_VER_LOW 4 +#define ICE_AQC_NVM_NETLIST_ID_BLK_MINOR_VER_HIGH 5 +#define ICE_AQC_NVM_NETLIST_ID_BLK_TYPE_LOW 6 +#define ICE_AQC_NVM_NETLIST_ID_BLK_TYPE_HIGH 7 +#define ICE_AQC_NVM_NETLIST_ID_BLK_REV_LOW 8 +#define ICE_AQC_NVM_NETLIST_ID_BLK_REV_HIGH 9 +#define ICE_AQC_NVM_NETLIST_ID_BLK_SHA_HASH 0xA +#define ICE_AQC_NVM_NETLIST_ID_BLK_CUST_VER 0x2F /* Used for 0x0704 as well as for 0x0705 commands */ struct ice_aqc_nvm_cfg { @@ -1749,14 +1761,12 @@ struct ice_aqc_nvm_cfg { __le32 addr_low; }; - struct ice_aqc_nvm_cfg_data { __le16 field_id; __le16 field_options; __le16 field_value; }; - /* NVM Checksum Command (direct, 0x0706) */ struct ice_aqc_nvm_checksum { u8 flags; @@ -1768,9 +1778,6 @@ struct ice_aqc_nvm_checksum { u8 rsvd2[12]; }; - - - /* Get LLDP MIB (indirect 0x0A00) * Note: This is also used by the LLDP MIB Change Event (0x0A01) * as the format is the same. @@ -1922,7 +1929,6 @@ struct ice_aqc_lldp_stop_start_specific_agent { u8 reserved[15]; }; - /* Get/Set RSS key (indirect 0x0B04/0x0B02) */ struct ice_aqc_get_set_rss_key { #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15) @@ -1934,7 +1940,6 @@ struct ice_aqc_get_set_rss_key { __le32 addr_low; }; - #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \ @@ -1956,7 +1961,6 @@ struct ice_aqc_get_set_rss_keys { u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; }; - /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ struct ice_aqc_get_set_rss_lut { #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15) @@ -1992,7 +1996,6 @@ struct ice_aqc_get_set_rss_lut { __le32 addr_low; }; - /* Clear FD Table Command (direct, 0x0B06) */ struct ice_aqc_clear_fd_table { u8 clear_type; @@ -2003,9 +2006,6 @@ struct ice_aqc_clear_fd_table { u8 reserved[12]; }; - - - /* Add Tx LAN Queues (indirect 0x0C30) */ struct ice_aqc_add_txqs { u8 num_qgrps; @@ -2015,7 +2015,6 @@ struct ice_aqc_add_txqs { __le32 addr_low; }; - /* This is the descriptor of each queue entry for the Add Tx LAN Queues * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. */ @@ -2028,7 +2027,6 @@ struct ice_aqc_add_txqs_perq { struct ice_aqc_txsched_elem info; }; - /* The format of the command buffer for Add Tx LAN Queues (0x0C30) * is an array of the following structs. Please note that the length of * each struct ice_aqc_add_tx_qgrp is variable due @@ -2041,7 +2039,6 @@ struct ice_aqc_add_tx_qgrp { struct ice_aqc_add_txqs_perq txqs[1]; }; - /* Disable Tx LAN Queues (indirect 0x0C31) */ struct ice_aqc_dis_txqs { u8 cmd_type; @@ -2064,7 +2061,6 @@ struct ice_aqc_dis_txqs { __le32 addr_low; }; - /* The buffer for Disable Tx LAN Queues (indirect 0x0C31) * contains the following structures, arrayed one after the * other. @@ -2087,12 +2083,10 @@ struct ice_aqc_dis_txq_item { (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) }; - struct ice_aqc_dis_txq { struct ice_aqc_dis_txq_item qgrps[1]; }; - /* Tx LAN Queues Cleanup Event (0x0C31) */ struct ice_aqc_txqs_cleanup { __le16 caller_opc; @@ -2100,7 +2094,6 @@ struct ice_aqc_txqs_cleanup { u8 reserved[12]; }; - /* Move / Reconfigure Tx Queues (indirect 0x0C32) */ struct ice_aqc_move_txqs { u8 cmd_type; @@ -2121,7 +2114,6 @@ struct ice_aqc_move_txqs { __le32 addr_low; }; - /* This is the descriptor of each queue entry for the move Tx LAN Queues * command (0x0C32). */ @@ -2132,15 +2124,12 @@ struct ice_aqc_move_txqs_elem { __le32 q_teid; }; - struct ice_aqc_move_txqs_data { __le32 src_teid; __le32 dest_teid; struct ice_aqc_move_txqs_elem txqs[1]; }; - - /* Download Package (indirect 0x0C40) */ /* Also used for Update Package (indirect 0x0C42) */ struct ice_aqc_download_pkg { @@ -2192,9 +2181,6 @@ struct ice_aqc_get_pkg_info_resp { struct ice_aqc_get_pkg_info pkg_info[1]; }; - - - /* Lan Queue Overflow Event (direct, 0x1001) */ struct ice_aqc_event_lan_overflow { __le32 prtdcb_ruptq; @@ -2202,9 +2188,6 @@ struct ice_aqc_event_lan_overflow { u8 reserved[8]; }; - - - /** * struct ice_aq_desc - Admin Queue (AQ) descriptor * @flags: ICE_AQ_FLAG_* flags @@ -2279,6 +2262,7 @@ struct ice_aq_desc { struct ice_aqc_clear_fd_table clear_fd_table; struct ice_aqc_add_txqs add_txqs; struct ice_aqc_dis_txqs dis_txqs; + struct ice_aqc_move_txqs move_txqs; struct ice_aqc_txqs_cleanup txqs_cleanup; struct ice_aqc_add_get_update_free_vsi vsi_cmd; struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res; @@ -2292,10 +2276,11 @@ struct ice_aq_desc { struct ice_aqc_set_mac_cfg set_mac_cfg; struct ice_aqc_set_event_mask set_event_mask; struct ice_aqc_get_link_status get_link_status; + struct ice_aqc_event_lan_overflow lan_overflow; + struct ice_aqc_get_link_topo get_link_topo; } params; }; - /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ #define ICE_AQ_LG_BUF 512 @@ -2455,6 +2440,7 @@ enum ice_adminq_opc { ice_aqc_opc_get_link_status = 0x0607, ice_aqc_opc_set_event_mask = 0x0613, ice_aqc_opc_set_mac_lb = 0x0620, + ice_aqc_opc_get_link_topo = 0x06E0, ice_aqc_opc_set_port_id_led = 0x06E9, ice_aqc_opc_get_port_options = 0x06EA, ice_aqc_opc_set_port_option = 0x06EB, @@ -2465,10 +2451,14 @@ enum ice_adminq_opc { /* NVM commands */ ice_aqc_opc_nvm_read = 0x0701, ice_aqc_opc_nvm_erase = 0x0702, - ice_aqc_opc_nvm_update = 0x0703, + ice_aqc_opc_nvm_write = 0x0703, ice_aqc_opc_nvm_cfg_read = 0x0704, ice_aqc_opc_nvm_cfg_write = 0x0705, ice_aqc_opc_nvm_checksum = 0x0706, + ice_aqc_opc_nvm_write_activate = 0x0707, + ice_aqc_opc_nvm_sr_dump = 0x0707, + ice_aqc_opc_nvm_save_factory_settings = 0x0708, + ice_aqc_opc_nvm_update_empr = 0x0709, /* LLDP commands */ ice_aqc_opc_lldp_get_mib = 0x0A00, @@ -2501,8 +2491,6 @@ enum ice_adminq_opc { ice_aqc_opc_update_pkg = 0x0C42, ice_aqc_opc_get_pkg_info_list = 0x0C43, - - /* Standalone Commands/Events */ ice_aqc_opc_event_lan_overflow = 0x1001, };