X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fice%2Fbase%2Fice_lan_tx_rx.h;h=696c6a30ae6896bf86b4a3ab2720ae76e278c1d4;hb=028c9d4da2b7bc843fe65c13432b26700b5e29a6;hp=d27045f7ec20a4df7e60d9c0def260a0d292c8ee;hpb=64e9587d5629fe8864f113c5c0d6116f3cb5352d;p=dpdk.git diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h index d27045f7ec..696c6a30ae 100644 --- a/drivers/net/ice/base/ice_lan_tx_rx.h +++ b/drivers/net/ice/base/ice_lan_tx_rx.h @@ -1,12 +1,12 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2018 + * Copyright(c) 2001-2021 Intel Corporation */ #ifndef _ICE_LAN_TX_RX_H_ #define _ICE_LAN_TX_RX_H_ #include "ice_osdep.h" -/* RX Descriptors */ +/* Rx Descriptors */ union ice_16byte_rx_desc { struct { __le64 pkt_addr; /* Packet buffer address */ @@ -20,7 +20,7 @@ union ice_16byte_rx_desc { } lo_dword; union { __le32 rss; /* RSS Hash */ - __le32 fd_id; /* Flow Director filter id */ + __le32 fd_id; /* Flow Director filter ID */ } hi_dword; } qword0; struct { @@ -46,7 +46,7 @@ union ice_32byte_rx_desc { } lo_dword; union { __le32 rss; /* RSS Hash */ - __le32 fd_id; /* Flow Director filter id */ + __le32 fd_id; /* Flow Director filter ID */ } hi_dword; } qword0; struct { @@ -163,6 +163,8 @@ struct ice_fltr_desc { #define ICE_FXD_FLTR_QW1_FDID_PRI_S 25 #define ICE_FXD_FLTR_QW1_FDID_PRI_M (0x7ULL << ICE_FXD_FLTR_QW1_FDID_PRI_S) #define ICE_FXD_FLTR_QW1_FDID_PRI_ZERO 0x0ULL +#define ICE_FXD_FLTR_QW1_FDID_PRI_ONE 0x1ULL +#define ICE_FXD_FLTR_QW1_FDID_PRI_THREE 0x3ULL #define ICE_FXD_FLTR_QW1_FDID_MDID_S 28 #define ICE_FXD_FLTR_QW1_FDID_MDID_M (0xFULL << ICE_FXD_FLTR_QW1_FDID_MDID_S) @@ -173,6 +175,49 @@ struct ice_fltr_desc { (0xFFFFFFFFULL << ICE_FXD_FLTR_QW1_FDID_S) #define ICE_FXD_FLTR_QW1_FDID_ZERO 0x0ULL +/* definition for FD filter programming status descriptor WB format */ +#define ICE_FXD_FLTR_WB_QW0_BUKT_LEN_S 28 +#define ICE_FXD_FLTR_WB_QW0_BUKT_LEN_M \ + (0xFULL << ICE_FXD_FLTR_WB_QW0_BUKT_LEN_S) + +#define ICE_FXD_FLTR_WB_QW0_FLTR_STAT_S 32 +#define ICE_FXD_FLTR_WB_QW0_FLTR_STAT_M \ + (0xFFFFFFFFULL << ICE_FXD_FLTR_WB_QW0_FLTR_STAT_S) + +#define ICE_FXD_FLTR_WB_QW1_DD_S 0 +#define ICE_FXD_FLTR_WB_QW1_DD_M (0x1ULL << ICE_FXD_FLTR_WB_QW1_DD_S) +#define ICE_FXD_FLTR_WB_QW1_DD_YES 0x1ULL + +#define ICE_FXD_FLTR_WB_QW1_PROG_ID_S 1 +#define ICE_FXD_FLTR_WB_QW1_PROG_ID_M \ + (0x3ULL << ICE_FXD_FLTR_WB_QW1_PROG_ID_S) +#define ICE_FXD_FLTR_WB_QW1_PROG_ADD 0x0ULL +#define ICE_FXD_FLTR_WB_QW1_PROG_DEL 0x1ULL + +#define ICE_FXD_FLTR_WB_QW1_FAIL_S 4 +#define ICE_FXD_FLTR_WB_QW1_FAIL_M (0x1ULL << ICE_FXD_FLTR_WB_QW1_FAIL_S) +#define ICE_FXD_FLTR_WB_QW1_FAIL_YES 0x1ULL + +#define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_S 5 +#define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_M \ + (0x1ULL << ICE_FXD_FLTR_WB_QW1_FAIL_PROF_S) +#define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_YES 0x1ULL + +#define ICE_FXD_FLTR_WB_QW1_FLT_ADDR_S 8 +#define ICE_FXD_FLTR_WB_QW1_FLT_ADDR_M \ + (0x3FFFULL << ICE_FXD_FLTR_WB_QW1_FLT_ADDR_S) + +#define ICE_FXD_FLTR_WB_QW1_PKT_PROF_S 28 +#define ICE_FXD_FLTR_WB_QW1_PKT_PROF_M \ + (0x7FULL << ICE_FXD_FLTR_WB_QW1_PKT_PROF_S) + +#define ICE_FXD_FLTR_WB_QW1_BUKT_HASH_S 38 +#define ICE_FXD_FLTR_WB_QW1_BUKT_HASH_M \ + (0x3FFFFFF << ICE_FXD_FLTR_WB_QW1_BUKT_HASH_S) + +#define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_M \ + (0x1ULL << ICE_FXD_FLTR_WB_QW1_FAIL_PROF_S) +#define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_YES 0x1ULL enum ice_rx_desc_status_bits { /* Note: These are predefined bit offsets */ @@ -181,15 +226,15 @@ enum ice_rx_desc_status_bits { ICE_RX_DESC_STATUS_L2TAG1P_S = 2, ICE_RX_DESC_STATUS_L3L4P_S = 3, ICE_RX_DESC_STATUS_CRCP_S = 4, - ICE_RX_DESC_STATUS_TSYNINDX_S = 5, /* 2 BITS */ + ICE_RX_DESC_STATUS_TSYNINDX_S = 5, ICE_RX_DESC_STATUS_TSYNVALID_S = 7, ICE_RX_DESC_STATUS_EXT_UDP_0_S = 8, - ICE_RX_DESC_STATUS_UMBCAST_S = 9, /* 2 BITS */ + ICE_RX_DESC_STATUS_UMBCAST_S = 9, ICE_RX_DESC_STATUS_FLM_S = 11, - ICE_RX_DESC_STATUS_FLTSTAT_S = 12, /* 2 BITS */ + ICE_RX_DESC_STATUS_FLTSTAT_S = 12, ICE_RX_DESC_STATUS_LPBK_S = 14, ICE_RX_DESC_STATUS_IPV6EXADD_S = 15, - ICE_RX_DESC_STATUS_RESERVED2_S = 16, /* 2 BITS */ + ICE_RX_DESC_STATUS_RESERVED2_S = 16, ICE_RX_DESC_STATUS_INT_UDP_0_S = 18, ICE_RX_DESC_STATUS_LAST /* this entry must be last!!! */ }; @@ -204,7 +249,6 @@ enum ice_rx_desc_status_bits { #define ICE_RXD_QW1_STATUS_TSYNVALID_S ICE_RX_DESC_STATUS_TSYNVALID_S #define ICE_RXD_QW1_STATUS_TSYNVALID_M BIT_ULL(ICE_RXD_QW1_STATUS_TSYNVALID_S) - enum ice_rx_desc_fltstat_values { ICE_RX_DESC_FLTSTAT_NO_DATA = 0, ICE_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */ @@ -212,7 +256,6 @@ enum ice_rx_desc_fltstat_values { ICE_RX_DESC_FLTSTAT_RSS_HASH = 3, }; - #define ICE_RXD_QW1_ERROR_S 19 #define ICE_RXD_QW1_ERROR_M (0xFFUL << ICE_RXD_QW1_ERROR_S) @@ -253,7 +296,6 @@ enum ice_rx_l2_ptype { }; struct ice_rx_ptype_decoded { - u32 ptype:10; u32 known:1; u32 outer_ip:1; u32 outer_ip_ver:2; @@ -310,7 +352,6 @@ enum ice_rx_ptype_payload_layer { ICE_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3, }; - #define ICE_RXD_QW1_LEN_PBUF_S 38 #define ICE_RXD_QW1_LEN_PBUF_M (0x3FFFULL << ICE_RXD_QW1_LEN_PBUF_S) @@ -320,18 +361,16 @@ enum ice_rx_ptype_payload_layer { #define ICE_RXD_QW1_LEN_SPH_S 63 #define ICE_RXD_QW1_LEN_SPH_M BIT_ULL(ICE_RXD_QW1_LEN_SPH_S) - enum ice_rx_desc_ext_status_bits { /* Note: These are predefined bit offsets */ ICE_RX_DESC_EXT_STATUS_L2TAG2P_S = 0, ICE_RX_DESC_EXT_STATUS_L2TAG3P_S = 1, - ICE_RX_DESC_EXT_STATUS_FLEXBL_S = 2, /* 2 BITS */ - ICE_RX_DESC_EXT_STATUS_FLEXBH_S = 4, /* 2 BITS */ + ICE_RX_DESC_EXT_STATUS_FLEXBL_S = 2, + ICE_RX_DESC_EXT_STATUS_FLEXBH_S = 4, ICE_RX_DESC_EXT_STATUS_FDLONGB_S = 9, ICE_RX_DESC_EXT_STATUS_PELONGB_S = 11, }; - enum ice_rx_desc_pe_status_bits { /* Note: These are predefined bit offsets */ ICE_RX_DESC_PE_STATUS_QPID_S = 0, /* 18 BITS */ @@ -352,7 +391,6 @@ enum ice_rx_desc_pe_status_bits { #define ICE_RX_PROG_STATUS_DESC_QW1_PROGID_M \ (0x7UL << ICE_RX_PROG_STATUS_DESC_QW1_PROGID_S) - #define ICE_RX_PROG_STATUS_DESC_QW1_ERROR_S 19 #define ICE_RX_PROG_STATUS_DESC_QW1_ERROR_M \ (0x3FUL << ICE_RX_PROG_STATUS_DESC_QW1_ERROR_S) @@ -373,10 +411,34 @@ enum ice_rx_prog_status_desc_error_bits { ICE_RX_PROG_STATUS_DESC_NO_FD_ENTRY_S = 1, }; -/* RX Flex Descriptor - * This descriptor is used instead of the legacy version descriptor when +/* Rx Flex Descriptors + * These descriptors are used instead of the legacy version descriptors when * ice_rlan_ctx.adv_desc is set */ +union ice_16b_rx_flex_desc { + struct { + __le64 pkt_addr; /* Packet buffer address */ + __le64 hdr_addr; /* Header buffer address */ + /* bit 0 of hdr_addr is DD bit */ + } read; + struct { + /* Qword 0 */ + u8 rxdid; /* descriptor builder profile ID */ + u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */ + __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */ + __le16 pkt_len; /* [15:14] are reserved */ + __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */ + /* sph=[11:11] */ + /* ff1/ext=[15:12] */ + + /* Qword 1 */ + __le16 status_error0; + __le16 l2tag1; + __le16 flex_meta0; + __le16 flex_meta1; + } wb; /* writeback */ +}; + union ice_32b_rx_flex_desc { struct { __le64 pkt_addr; /* Packet buffer address */ @@ -387,7 +449,7 @@ union ice_32b_rx_flex_desc { } read; struct { /* Qword 0 */ - u8 rxdid; /* descriptor builder profile id */ + u8 rxdid; /* descriptor builder profile ID */ u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */ __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */ __le16 pkt_len; /* [15:14] are reserved */ @@ -422,12 +484,12 @@ union ice_32b_rx_flex_desc { }; /* Rx Flex Descriptor NIC Profile - * RxDID Profile Id 2 + * RxDID Profile ID 2 * Flex-field 0: RSS hash lower 16-bits * Flex-field 1: RSS hash upper 16-bits - * Flex-field 2: Flow Id lower 16-bits - * Flex-field 3: Flow Id higher 16-bits - * Flex-field 4: reserved, Vlan id taken from L2Tag + * Flex-field 2: Flow ID lower 16-bits + * Flex-field 3: Flow ID higher 16-bits + * Flex-field 4: reserved, VLAN ID taken from L2Tag */ struct ice_32b_rx_flex_desc_nic { /* Qword 0 */ @@ -461,8 +523,8 @@ struct ice_32b_rx_flex_desc_nic { }; /* Rx Flex Descriptor Switch Profile - * RxDID Profile Id 3 - * Flex-field 0: Source Vsi + * RxDID Profile ID 3 + * Flex-field 0: Source VSI */ struct ice_32b_rx_flex_desc_sw { /* Qword 0 */ @@ -491,8 +553,8 @@ struct ice_32b_rx_flex_desc_sw { }; /* Rx Flex Descriptor NIC VEB Profile - * RxDID Profile Id 4 - * Flex-field 0: Destination Vsi + * RxDID Profile ID 4 + * Flex-field 0: Destination VSI */ struct ice_32b_rx_flex_desc_nic_veb_dbg { /* Qword 0 */ @@ -505,8 +567,8 @@ struct ice_32b_rx_flex_desc_nic_veb_dbg { /* Qword 1 */ __le16 status_error0; __le16 l2tag1; - __le16 dst_vsi; /* [0:12]: destination vsi */ - /* 13: vsi valid bit */ + __le16 dst_vsi; /* [0:12]: destination VSI */ + /* 13: VSI valid bit */ /* [14:15] are reserved */ __le16 flex_field_1; @@ -523,7 +585,7 @@ struct ice_32b_rx_flex_desc_nic_veb_dbg { }; /* Rx Flex Descriptor NIC ACL Profile - * RxDID Profile Id 5 + * RxDID Profile ID 5 * Flex-field 0: ACL Counter 0 * Flex-field 1: ACL Counter 1 * Flex-field 2: ACL Counter 2 @@ -556,12 +618,12 @@ struct ice_32b_rx_flex_desc_nic_acl_dbg { }; /* Rx Flex Descriptor NIC Profile - * RxDID Profile Id 6 + * RxDID Profile ID 6 * Flex-field 0: RSS hash lower 16-bits * Flex-field 1: RSS hash upper 16-bits - * Flex-field 2: Flow Id lower 16-bits - * Flex-field 3: Source Vsi - * Flex-field 4: reserved, Vlan id taken from L2Tag + * Flex-field 2: Flow ID lower 16-bits + * Flex-field 3: Source VSI + * Flex-field 4: reserved, VLAN ID taken from L2Tag */ struct ice_32b_rx_flex_desc_nic_2 { /* Qword 0 */ @@ -595,6 +657,46 @@ struct ice_32b_rx_flex_desc_nic_2 { } flex_ts; }; +/* Rx Flex Descriptor for Comms Package Profile + * RxDID Profile ID 16-21 + * Flex-field 0: RSS hash lower 16-bits + * Flex-field 1: RSS hash upper 16-bits + * Flex-field 2: Flow ID lower 16-bits + * Flex-field 3: Flow ID upper 16-bits + * Flex-field 4: AUX0 + * Flex-field 5: AUX1 + */ +struct ice_32b_rx_flex_desc_comms { + /* Qword 0 */ + u8 rxdid; + u8 mir_id_umb_cast; + __le16 ptype_flexi_flags0; + __le16 pkt_len; + __le16 hdr_len_sph_flex_flags1; + + /* Qword 1 */ + __le16 status_error0; + __le16 l2tag1; + __le32 rss_hash; + + /* Qword 2 */ + __le16 status_error1; + u8 flexi_flags2; + u8 ts_low; + __le16 l2tag2_1st; + __le16 l2tag2_2nd; + + /* Qword 3 */ + __le32 flow_id; + union { + struct { + __le16 aux0; + __le16 aux1; + } flex; + __le32 ts_high; + } flex_ts; +}; + /* Receive Flex Descriptor profile IDs: There are a total * of 64 profiles where profile IDs 0/1 are for legacy; and * profiles 2-63 are flex profiles that can be programmed @@ -606,6 +708,13 @@ enum ice_rxdid { ICE_RXDID_FLEX_NIC = 2, ICE_RXDID_FLEX_NIC_2 = 6, ICE_RXDID_HW = 7, + ICE_RXDID_COMMS_GENERIC = 16, + ICE_RXDID_COMMS_AUX_VLAN = 17, + ICE_RXDID_COMMS_AUX_IPV4 = 18, + ICE_RXDID_COMMS_AUX_IPV6 = 19, + ICE_RXDID_COMMS_AUX_IPV6_FLOW = 20, + ICE_RXDID_COMMS_AUX_TCP = 21, + ICE_RXDID_COMMS_AUX_IP_OFFSET = 25, ICE_RXDID_LAST = 63, }; @@ -627,39 +736,60 @@ enum ice_flex_opcode { ICE_RX_OPC_PROTID }; -/* Receive Descriptor MDID values */ -enum ice_flex_rx_mdid { - ICE_RX_MDID_FLOW_ID_LOWER = 5, - ICE_RX_MDID_FLOW_ID_HIGH, - ICE_RX_MDID_DST_VSI = 13, - ICE_RX_MDID_SRC_VSI = 19, - ICE_RX_MDID_HASH_LOW = 56, - ICE_RX_MDID_HASH_HIGH, - ICE_RX_MDID_ACL_CTR0 = ICE_RX_MDID_HASH_LOW, - ICE_RX_MDID_ACL_CTR1 = ICE_RX_MDID_HASH_HIGH, - ICE_RX_MDID_ACL_CTR2 = 59 +/* Receive Descriptor MDID values that access packet flags */ +enum ice_flex_mdid_pkt_flags { + ICE_RX_MDID_PKT_FLAGS_15_0 = 20, + ICE_RX_MDID_PKT_FLAGS_31_16, + ICE_RX_MDID_PKT_FLAGS_47_32, + ICE_RX_MDID_PKT_FLAGS_63_48, +}; + +/* Generic descriptor MDID values */ +enum ice_flex_mdid { + ICE_MDID_GENERIC_WORD_0, + ICE_MDID_GENERIC_WORD_1, + ICE_MDID_GENERIC_WORD_2, + ICE_MDID_GENERIC_WORD_3, + ICE_MDID_GENERIC_WORD_4, + ICE_MDID_FLOW_ID_LOWER, + ICE_MDID_FLOW_ID_HIGH, + ICE_MDID_RX_DESCR_PROF_IDX, + ICE_MDID_RX_PKT_DROP, + ICE_MDID_RX_DST_Q = 12, + ICE_MDID_RX_DST_VSI, + ICE_MDID_SRC_VSI = 19, + ICE_MDID_ACL_NOP = 55, + /* Entry 56 */ + ICE_MDID_RX_HASH_LOW, + ICE_MDID_ACL_CNTR_PKT = ICE_MDID_RX_HASH_LOW, + /* Entry 57 */ + ICE_MDID_RX_HASH_HIGH, + ICE_MDID_ACL_CNTR_BYTES = ICE_MDID_RX_HASH_HIGH, + ICE_MDID_ACL_CNTR_PKT_BYTES }; /* for ice_32byte_rx_flex_desc.mir_id_umb_cast member */ #define ICE_RX_FLEX_DESC_MIRROR_M (0x3F) /* 6-bits */ -/* Rx Flag64 packet flag bits */ -enum ice_rx_flg64_bits { - ICE_RXFLG_PKT_DSI = 0, - ICE_RXFLG_EVLAN_x8100 = 15, - ICE_RXFLG_EVLAN_x9100, - ICE_RXFLG_VLAN_x8100, - ICE_RXFLG_TNL_MAC = 22, - ICE_RXFLG_TNL_VLAN, - ICE_RXFLG_PKT_FRG, - ICE_RXFLG_FIN = 32, - ICE_RXFLG_SYN, - ICE_RXFLG_RST, - ICE_RXFLG_TNL0 = 38, - ICE_RXFLG_TNL1, - ICE_RXFLG_TNL2, - ICE_RXFLG_UDP_GRE, - ICE_RXFLG_RSVD = 63 +/* Rx/Tx Flag64 packet flag bits */ +enum ice_flg64_bits { + ICE_FLG_PKT_DSI = 0, + /* If there is a 1 in this bit position then that means Rx packet */ + ICE_FLG_PKT_DIR = 4, + ICE_FLG_EVLAN_x8100 = 14, + ICE_FLG_EVLAN_x9100, + ICE_FLG_VLAN_x8100, + ICE_FLG_TNL_MAC = 22, + ICE_FLG_TNL_VLAN, + ICE_FLG_PKT_FRG, + ICE_FLG_FIN = 32, + ICE_FLG_SYN, + ICE_FLG_RST, + ICE_FLG_TNL0 = 38, + ICE_FLG_TNL1, + ICE_FLG_TNL2, + ICE_FLG_UDP_GRE, + ICE_FLG_RSVD = 63 }; enum ice_rx_flex_desc_umb_cast_bits { /* field is 2 bits long */ @@ -749,7 +879,6 @@ enum ice_rx_flex_desc_exstat_bits { ICE_RX_FLEX_DESC_EXSTAT_OVERSIZE_S = 3, }; - #define ICE_RXQ_CTX_SIZE_DWORDS 8 #define ICE_RXQ_CTX_SZ (ICE_RXQ_CTX_SIZE_DWORDS * sizeof(u32)) #define ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS 22 @@ -786,6 +915,7 @@ struct ice_rlan_ctx { u8 tphdata_ena; u8 tphhead_ena; u16 lrxqthresh; /* bigger than needed, see above for reason */ + u8 prefena; /* NOTE: normally must be set to 1 at init */ }; struct ice_ctx_ele { @@ -818,7 +948,7 @@ enum ice_rlan_ctx_rx_hsplit_1 { ICE_RLAN_RX_HSPLIT_1_SPLIT_ALWAYS = 2, }; -/* TX Descriptor */ +/* Tx Descriptor */ struct ice_tx_desc { __le64 buf_addr; /* Address of descriptor's data buf */ __le64 cmd_type_offset_bsz; @@ -846,15 +976,15 @@ enum ice_tx_desc_cmd_bits { ICE_TX_DESC_CMD_RSVD = 0x0004, ICE_TX_DESC_CMD_IL2TAG1 = 0x0008, ICE_TX_DESC_CMD_DUMMY = 0x0010, - ICE_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */ - ICE_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */ - ICE_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */ - ICE_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */ + ICE_TX_DESC_CMD_IIPT_NONIP = 0x0000, + ICE_TX_DESC_CMD_IIPT_IPV6 = 0x0020, + ICE_TX_DESC_CMD_IIPT_IPV4 = 0x0040, + ICE_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, ICE_TX_DESC_CMD_RSVD2 = 0x0080, - ICE_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */ - ICE_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */ - ICE_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */ - ICE_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */ + ICE_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, + ICE_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, + ICE_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, + ICE_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, ICE_TX_DESC_CMD_RE = 0x0400, ICE_TX_DESC_CMD_RSVD3 = 0x0800, }; @@ -964,7 +1094,6 @@ enum ice_tx_ctx_desc_eipt_offload { #define ICE_TXD_CTX_QW0_L4T_CS_S 23 #define ICE_TXD_CTX_QW0_L4T_CS_M BIT_ULL(ICE_TXD_CTX_QW0_L4T_CS_S) - #define ICE_LAN_TXQ_MAX_QGRPS 127 #define ICE_LAN_TXQ_MAX_QDIS 1023 @@ -987,6 +1116,7 @@ struct ice_tlan_ctx { #define ICE_TLAN_CTX_VMVF_TYPE_PF 2 u16 src_vsi; u8 tsyn_ena; + u8 internal_usage_flag; u8 alt_vlan; u16 cpuid; /* bigger than needed, see above for reason */ u8 wb_mode; @@ -1005,7 +1135,7 @@ struct ice_tlan_ctx { u8 drop_ena; u8 cache_prof_idx; u8 pkt_shaper_prof_idx; - u8 int_q_state; /* width not needed - internal do not write */ + u8 int_q_state; /* width not needed - internal - DO NOT WRITE!!! */ }; /* LAN Tx Completion Queue data */ @@ -1018,7 +1148,6 @@ struct ice_tx_cmpltnq { }; #pragma pack() - /* LAN Tx Completion Queue Context */ #pragma pack(1) struct ice_tx_cmpltnq_ctx { @@ -1087,8 +1216,7 @@ struct ice_tx_drbell_q_ctx { /* macro to make the table lines short */ #define ICE_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ - { PTYPE, \ - 1, \ + { 1, \ ICE_RX_PTYPE_OUTER_##OUTER_IP, \ ICE_RX_PTYPE_OUTER_##OUTER_IP_VER, \ ICE_RX_PTYPE_##OUTER_FRAG, \ @@ -1098,18 +1226,18 @@ struct ice_tx_drbell_q_ctx { ICE_RX_PTYPE_INNER_PROT_##I, \ ICE_RX_PTYPE_PAYLOAD_LAYER_##PL } -#define ICE_PTT_UNUSED_ENTRY(PTYPE) { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } +#define ICE_PTT_UNUSED_ENTRY(PTYPE) { 0, 0, 0, 0, 0, 0, 0, 0, 0 } /* shorter macros makes the table fit but are terse */ #define ICE_RX_PTYPE_NOF ICE_RX_PTYPE_NOT_FRAG #define ICE_RX_PTYPE_FRG ICE_RX_PTYPE_FRAG -/* Lookup table mapping the HW PTYPE to the bit field for decoding */ -static const struct ice_rx_ptype_decoded ice_ptype_lkup[] = { +/* Lookup table mapping the 10-bit HW PTYPE to the bit field for decoding */ +static const struct ice_rx_ptype_decoded ice_ptype_lkup[1024] = { /* L2 Packet types */ ICE_PTT_UNUSED_ENTRY(0), ICE_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), - ICE_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), + ICE_PTT_UNUSED_ENTRY(2), ICE_PTT_UNUSED_ENTRY(3), ICE_PTT_UNUSED_ENTRY(4), ICE_PTT_UNUSED_ENTRY(5), @@ -1223,7 +1351,7 @@ static const struct ice_rx_ptype_decoded ice_ptype_lkup[] = { /* Non Tunneled IPv6 */ ICE_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3), ICE_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3), - ICE_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3), + ICE_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4), ICE_PTT_UNUSED_ENTRY(91), ICE_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4), ICE_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),