X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fice%2Fbase%2Fice_lan_tx_rx.h;h=a97c63cc971a84a58524a7ebdf731beeb8eeecb4;hb=89a532ba87ccf64bd53be6f2c384d5747d616612;hp=e1c2f0d01dedfa96fe4a7b81fb72f400eed5008c;hpb=a6d7b12cabeceb2bb3f27f52e8b692321754f25e;p=dpdk.git

diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h
index e1c2f0d01d..a97c63cc97 100644
--- a/drivers/net/ice/base/ice_lan_tx_rx.h
+++ b/drivers/net/ice/base/ice_lan_tx_rx.h
@@ -173,7 +173,6 @@ struct ice_fltr_desc {
 			(0xFFFFFFFFULL << ICE_FXD_FLTR_QW1_FDID_S)
 #define ICE_FXD_FLTR_QW1_FDID_ZERO	0x0ULL
 
-
 enum ice_rx_desc_status_bits {
 	/* Note: These are predefined bit offsets */
 	ICE_RX_DESC_STATUS_DD_S			= 0,
@@ -204,7 +203,6 @@ enum ice_rx_desc_status_bits {
 #define ICE_RXD_QW1_STATUS_TSYNVALID_S ICE_RX_DESC_STATUS_TSYNVALID_S
 #define ICE_RXD_QW1_STATUS_TSYNVALID_M BIT_ULL(ICE_RXD_QW1_STATUS_TSYNVALID_S)
 
-
 enum ice_rx_desc_fltstat_values {
 	ICE_RX_DESC_FLTSTAT_NO_DATA	= 0,
 	ICE_RX_DESC_FLTSTAT_RSV_FD_ID	= 1, /* 16byte desc? FD_ID : RSV */
@@ -212,7 +210,6 @@ enum ice_rx_desc_fltstat_values {
 	ICE_RX_DESC_FLTSTAT_RSS_HASH	= 3,
 };
 
-
 #define ICE_RXD_QW1_ERROR_S	19
 #define ICE_RXD_QW1_ERROR_M		(0xFFUL << ICE_RXD_QW1_ERROR_S)
 
@@ -310,7 +307,6 @@ enum ice_rx_ptype_payload_layer {
 	ICE_RX_PTYPE_PAYLOAD_LAYER_PAY4	= 3,
 };
 
-
 #define ICE_RXD_QW1_LEN_PBUF_S	38
 #define ICE_RXD_QW1_LEN_PBUF_M	(0x3FFFULL << ICE_RXD_QW1_LEN_PBUF_S)
 
@@ -320,7 +316,6 @@ enum ice_rx_ptype_payload_layer {
 #define ICE_RXD_QW1_LEN_SPH_S	63
 #define ICE_RXD_QW1_LEN_SPH_M	BIT_ULL(ICE_RXD_QW1_LEN_SPH_S)
 
-
 enum ice_rx_desc_ext_status_bits {
 	/* Note: These are predefined bit offsets */
 	ICE_RX_DESC_EXT_STATUS_L2TAG2P_S	= 0,
@@ -331,7 +326,6 @@ enum ice_rx_desc_ext_status_bits {
 	ICE_RX_DESC_EXT_STATUS_PELONGB_S	= 11,
 };
 
-
 enum ice_rx_desc_pe_status_bits {
 	/* Note: These are predefined bit offsets */
 	ICE_RX_DESC_PE_STATUS_QPID_S		= 0, /* 18 BITS */
@@ -352,7 +346,6 @@ enum ice_rx_desc_pe_status_bits {
 #define ICE_RX_PROG_STATUS_DESC_QW1_PROGID_M	\
 			(0x7UL << ICE_RX_PROG_STATUS_DESC_QW1_PROGID_S)
 
-
 #define ICE_RX_PROG_STATUS_DESC_QW1_ERROR_S	19
 #define ICE_RX_PROG_STATUS_DESC_QW1_ERROR_M	\
 			(0x3FUL << ICE_RX_PROG_STATUS_DESC_QW1_ERROR_S)
@@ -737,7 +730,7 @@ enum ice_flg64_bits {
 	ICE_FLG_PKT_DSI		= 0,
 	/* If there is a 1 in this bit position then that means Rx packet */
 	ICE_FLG_PKT_DIR		= 4,
-	ICE_FLG_EVLAN_x8100	= 15,
+	ICE_FLG_EVLAN_x8100	= 14,
 	ICE_FLG_EVLAN_x9100,
 	ICE_FLG_VLAN_x8100,
 	ICE_FLG_TNL_MAC		= 22,
@@ -840,7 +833,6 @@ enum ice_rx_flex_desc_exstat_bits {
 	ICE_RX_FLEX_DESC_EXSTAT_OVERSIZE_S = 3,
 };
 
-
 #define ICE_RXQ_CTX_SIZE_DWORDS		8
 #define ICE_RXQ_CTX_SZ			(ICE_RXQ_CTX_SIZE_DWORDS * sizeof(u32))
 #define ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS	22
@@ -1056,7 +1048,6 @@ enum ice_tx_ctx_desc_eipt_offload {
 #define ICE_TXD_CTX_QW0_L4T_CS_S	23
 #define ICE_TXD_CTX_QW0_L4T_CS_M	BIT_ULL(ICE_TXD_CTX_QW0_L4T_CS_S)
 
-
 #define ICE_LAN_TXQ_MAX_QGRPS	127
 #define ICE_LAN_TXQ_MAX_QDIS	1023