X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fice%2Fice_ethdev.c;h=c9fd3de2bd6f7c9941c9b3fdf356e06f15ad098a;hb=a631c98a96a20358d5cad00c605ebd71f8feeed8;hp=3498a5075432698889d31c9717bbee47d99b5c12;hpb=ac882a0eda6950f58271ee507b46f1a0a7ff9672;p=dpdk.git diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index 3498a50754..c9fd3de2bd 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -3,17 +3,22 @@ */ #include -#include +#include #include #include #include #include +#include + +#include "eal_firmware.h" + #include "base/ice_sched.h" #include "base/ice_flow.h" #include "base/ice_dcb.h" #include "base/ice_common.h" +#include "base/ice_ptp_hw.h" #include "rte_pmd_ice.h" #include "ice_ethdev.h" @@ -23,19 +28,30 @@ /* devargs */ #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support" #define ICE_PIPELINE_MODE_SUPPORT_ARG "pipeline-mode-support" -#define ICE_FLOW_MARK_SUPPORT_ARG "flow-mark-support" #define ICE_PROTO_XTR_ARG "proto_xtr" +#define ICE_HW_DEBUG_MASK_ARG "hw_debug_mask" +#define ICE_ONE_PPS_OUT_ARG "pps_out" +#define ICE_RX_LOW_LATENCY_ARG "rx_low_latency" + +#define ICE_CYCLECOUNTER_MASK 0xffffffffffffffffULL + +uint64_t ice_timestamp_dynflag; +int ice_timestamp_dynfield_offset = -1; static const char * const ice_valid_args[] = { ICE_SAFE_MODE_SUPPORT_ARG, ICE_PIPELINE_MODE_SUPPORT_ARG, - ICE_FLOW_MARK_SUPPORT_ARG, ICE_PROTO_XTR_ARG, + ICE_HW_DEBUG_MASK_ARG, + ICE_ONE_PPS_OUT_ARG, + ICE_RX_LOW_LATENCY_ARG, NULL }; +#define PPS_OUT_DELAY_NS 1 + static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = { - .name = "ice_dynfield_proto_xtr_metadata", + .name = "intel_pmd_dynfield_proto_xtr_metadata", .size = sizeof(uint32_t), .align = __alignof__(uint32_t), .flags = 0, @@ -47,53 +63,37 @@ struct proto_xtr_ol_flag { bool required; }; +static bool ice_proto_xtr_hw_support[PROTO_XTR_MAX]; + static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = { [PROTO_XTR_VLAN] = { - .param = { .name = "ice_dynflag_proto_xtr_vlan" }, + .param = { .name = "intel_pmd_dynflag_proto_xtr_vlan" }, .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask }, [PROTO_XTR_IPV4] = { - .param = { .name = "ice_dynflag_proto_xtr_ipv4" }, + .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv4" }, .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask }, [PROTO_XTR_IPV6] = { - .param = { .name = "ice_dynflag_proto_xtr_ipv6" }, + .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6" }, .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask }, [PROTO_XTR_IPV6_FLOW] = { - .param = { .name = "ice_dynflag_proto_xtr_ipv6_flow" }, + .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6_flow" }, .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask }, [PROTO_XTR_TCP] = { - .param = { .name = "ice_dynflag_proto_xtr_tcp" }, + .param = { .name = "intel_pmd_dynflag_proto_xtr_tcp" }, .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask }, + [PROTO_XTR_IP_OFFSET] = { + .param = { .name = "intel_pmd_dynflag_proto_xtr_ip_offset" }, + .ol_flag = &rte_net_ice_dynflag_proto_xtr_ip_offset_mask }, }; -#define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100 - -/* DDP package search path */ -#define ICE_PKG_FILE_DEFAULT "/lib/firmware/intel/ice/ddp/ice.pkg" -#define ICE_PKG_FILE_UPDATES "/lib/firmware/updates/intel/ice/ddp/ice.pkg" -#define ICE_PKG_FILE_SEARCH_PATH_DEFAULT "/lib/firmware/intel/ice/ddp/" -#define ICE_PKG_FILE_SEARCH_PATH_UPDATES "/lib/firmware/updates/intel/ice/ddp/" - #define ICE_OS_DEFAULT_PKG_NAME "ICE OS Default Package" #define ICE_COMMS_PKG_NAME "ICE COMMS Package" -#define ICE_MAX_PKG_FILENAME_SIZE 256 #define ICE_MAX_RES_DESC_NUM 1024 -int ice_logtype_init; -int ice_logtype_driver; -#ifdef RTE_LIBRTE_ICE_DEBUG_RX -int ice_logtype_rx; -#endif -#ifdef RTE_LIBRTE_ICE_DEBUG_TX -int ice_logtype_tx; -#endif -#ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE -int ice_logtype_tx_free; -#endif - static int ice_dev_configure(struct rte_eth_dev *dev); static int ice_dev_start(struct rte_eth_dev *dev); -static void ice_dev_stop(struct rte_eth_dev *dev); -static void ice_dev_close(struct rte_eth_dev *dev); +static int ice_dev_stop(struct rte_eth_dev *dev); +static int ice_dev_close(struct rte_eth_dev *dev); static int ice_dev_reset(struct rte_eth_dev *dev); static int ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info); @@ -147,27 +147,51 @@ static int ice_xstats_get(struct rte_eth_dev *dev, static int ice_xstats_get_names(struct rte_eth_dev *dev, struct rte_eth_xstat_name *xstats_names, unsigned int limit); -static int ice_dev_filter_ctrl(struct rte_eth_dev *dev, - enum rte_filter_type filter_type, - enum rte_filter_op filter_op, - void *arg); +static int ice_dev_flow_ops_get(struct rte_eth_dev *dev, + const struct rte_flow_ops **ops); static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, struct rte_eth_udp_tunnel *udp_tunnel); static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, struct rte_eth_udp_tunnel *udp_tunnel); +static int ice_timesync_enable(struct rte_eth_dev *dev); +static int ice_timesync_read_rx_timestamp(struct rte_eth_dev *dev, + struct timespec *timestamp, + uint32_t flags); +static int ice_timesync_read_tx_timestamp(struct rte_eth_dev *dev, + struct timespec *timestamp); +static int ice_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); +static int ice_timesync_read_time(struct rte_eth_dev *dev, + struct timespec *timestamp); +static int ice_timesync_write_time(struct rte_eth_dev *dev, + const struct timespec *timestamp); +static int ice_timesync_disable(struct rte_eth_dev *dev); static const struct rte_pci_id pci_id_ice_map[] = { + { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_BACKPLANE) }, + { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_SFP) }, + { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_10G_BASE_T) }, + { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_1GBE) }, + { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_QSFP) }, { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) }, { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) }, { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) }, { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) }, { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) }, { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) }, + { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_BACKPLANE) }, + { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_QSFP) }, + { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SFP) }, + { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_10G_BASE_T) }, + { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SGMII) }, { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_BACKPLANE) }, { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_QSFP) }, { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SFP) }, { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_10G_BASE_T) }, { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SGMII) }, + { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_BACKPLANE) }, + { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SFP) }, + { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_10G_BASE_T) }, + { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SGMII) }, { .vendor_id = 0, /* sentinel */ }, }; @@ -184,9 +208,9 @@ static const struct eth_dev_ops ice_eth_dev_ops = { .tx_queue_start = ice_tx_queue_start, .tx_queue_stop = ice_tx_queue_stop, .rx_queue_setup = ice_rx_queue_setup, - .rx_queue_release = ice_rx_queue_release, + .rx_queue_release = ice_dev_rx_queue_release, .tx_queue_setup = ice_tx_queue_setup, - .tx_queue_release = ice_tx_queue_release, + .tx_queue_release = ice_dev_tx_queue_release, .dev_infos_get = ice_dev_info_get, .dev_supported_ptypes_get = ice_dev_supported_ptypes_get, .link_update = ice_link_update, @@ -214,18 +238,23 @@ static const struct eth_dev_ops ice_eth_dev_ops = { .tx_burst_mode_get = ice_tx_burst_mode_get, .get_eeprom_length = ice_get_eeprom_length, .get_eeprom = ice_get_eeprom, - .rx_queue_count = ice_rx_queue_count, - .rx_descriptor_status = ice_rx_descriptor_status, - .tx_descriptor_status = ice_tx_descriptor_status, .stats_get = ice_stats_get, .stats_reset = ice_stats_reset, .xstats_get = ice_xstats_get, .xstats_get_names = ice_xstats_get_names, .xstats_reset = ice_stats_reset, - .filter_ctrl = ice_dev_filter_ctrl, + .flow_ops_get = ice_dev_flow_ops_get, .udp_tunnel_port_add = ice_dev_udp_tunnel_port_add, .udp_tunnel_port_del = ice_dev_udp_tunnel_port_del, .tx_done_cleanup = ice_tx_done_cleanup, + .get_monitor_addr = ice_get_monitor_addr, + .timesync_enable = ice_timesync_enable, + .timesync_read_rx_timestamp = ice_timesync_read_rx_timestamp, + .timesync_read_tx_timestamp = ice_timesync_read_tx_timestamp, + .timesync_adjust_time = ice_timesync_adjust_time, + .timesync_read_time = ice_timesync_read_time, + .timesync_write_time = ice_timesync_write_time, + .timesync_disable = ice_timesync_disable, }; /* store statistics names and its offset in stats structure */ @@ -321,6 +350,13 @@ ice_init_controlq_parameter(struct ice_hw *hw) hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN; hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ; hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ; + + /* fields for sideband queue */ + hw->sbq.num_rq_entries = ICE_SBQ_LEN; + hw->sbq.num_sq_entries = ICE_SBQ_LEN; + hw->sbq.rq_buf_size = ICE_SBQ_MAX_BUF_LEN; + hw->sbq.sq_buf_size = ICE_SBQ_MAX_BUF_LEN; + } static int @@ -335,6 +371,7 @@ lookup_proto_xtr_type(const char *xtr_name) { "ipv6", PROTO_XTR_IPV6 }, { "ipv6_flow", PROTO_XTR_IPV6_FLOW }, { "tcp", PROTO_XTR_TCP }, + { "ip_offset", PROTO_XTR_IP_OFFSET }, }; uint32_t i; @@ -550,25 +587,40 @@ handle_proto_xtr_arg(__rte_unused const char *key, const char *value, return 0; } -static bool -ice_proto_xtr_support(struct ice_hw *hw) +static void +ice_check_proto_xtr_support(struct ice_hw *hw) { #define FLX_REG(val, fld, idx) \ (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \ GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S) static struct { uint32_t rxdid; - uint16_t protid_0; - uint16_t protid_1; + uint8_t opcode; + uint8_t protid_0; + uint8_t protid_1; } xtr_sets[] = { - { ICE_RXDID_COMMS_AUX_VLAN, ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O }, - { ICE_RXDID_COMMS_AUX_IPV4, ICE_PROT_IPV4_OF_OR_S, - ICE_PROT_IPV4_OF_OR_S }, - { ICE_RXDID_COMMS_AUX_IPV6, ICE_PROT_IPV6_OF_OR_S, - ICE_PROT_IPV6_OF_OR_S }, - { ICE_RXDID_COMMS_AUX_IPV6_FLOW, ICE_PROT_IPV6_OF_OR_S, - ICE_PROT_IPV6_OF_OR_S }, - { ICE_RXDID_COMMS_AUX_TCP, ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL }, + [PROTO_XTR_VLAN] = { ICE_RXDID_COMMS_AUX_VLAN, + ICE_RX_OPC_EXTRACT, + ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O}, + [PROTO_XTR_IPV4] = { ICE_RXDID_COMMS_AUX_IPV4, + ICE_RX_OPC_EXTRACT, + ICE_PROT_IPV4_OF_OR_S, + ICE_PROT_IPV4_OF_OR_S }, + [PROTO_XTR_IPV6] = { ICE_RXDID_COMMS_AUX_IPV6, + ICE_RX_OPC_EXTRACT, + ICE_PROT_IPV6_OF_OR_S, + ICE_PROT_IPV6_OF_OR_S }, + [PROTO_XTR_IPV6_FLOW] = { ICE_RXDID_COMMS_AUX_IPV6_FLOW, + ICE_RX_OPC_EXTRACT, + ICE_PROT_IPV6_OF_OR_S, + ICE_PROT_IPV6_OF_OR_S }, + [PROTO_XTR_TCP] = { ICE_RXDID_COMMS_AUX_TCP, + ICE_RX_OPC_EXTRACT, + ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL }, + [PROTO_XTR_IP_OFFSET] = { ICE_RXDID_COMMS_AUX_IP_OFFSET, + ICE_RX_OPC_PROTID, + ICE_PROT_IPV4_OF_OR_S, + ICE_PROT_IPV6_OF_OR_S }, }; uint32_t i; @@ -579,21 +631,19 @@ ice_proto_xtr_support(struct ice_hw *hw) if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) { v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid)); - if (FLX_REG(v, PROT_MDID, 4) != xtr_sets[i].protid_0 || - FLX_REG(v, RXDID_OPCODE, 4) != ICE_RX_OPC_EXTRACT) - return false; + if (FLX_REG(v, PROT_MDID, 4) == xtr_sets[i].protid_0 && + FLX_REG(v, RXDID_OPCODE, 4) == xtr_sets[i].opcode) + ice_proto_xtr_hw_support[i] = true; } if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) { v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid)); - if (FLX_REG(v, PROT_MDID, 5) != xtr_sets[i].protid_1 || - FLX_REG(v, RXDID_OPCODE, 5) != ICE_RX_OPC_EXTRACT) - return false; + if (FLX_REG(v, PROT_MDID, 5) == xtr_sets[i].protid_1 && + FLX_REG(v, RXDID_OPCODE, 5) == xtr_sets[i].opcode) + ice_proto_xtr_hw_support[i] = true; } } - - return true; } static int @@ -801,7 +851,7 @@ ice_init_mac_address(struct rte_eth_dev *dev) (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr); dev->data->mac_addrs = - rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0); + rte_zmalloc(NULL, sizeof(struct rte_ether_addr) * ICE_NUM_MACADDR_MAX, 0); if (!dev->data->mac_addrs) { PMD_INIT_LOG(ERR, "Failed to allocate memory to store mac address"); @@ -940,12 +990,13 @@ DONE: /* Find out specific VLAN filter */ static struct ice_vlan_filter * -ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id) +ice_find_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan) { struct ice_vlan_filter *f; TAILQ_FOREACH(f, &vsi->vlan_list, next) { - if (vlan_id == f->vlan_info.vlan_id) + if (vlan->tpid == f->vlan_info.vlan.tpid && + vlan->vid == f->vlan_info.vlan.vid) return f; } @@ -953,7 +1004,7 @@ ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id) } static int -ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id) +ice_add_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan) { struct ice_fltr_list_entry *v_list_itr = NULL; struct ice_vlan_filter *f; @@ -961,13 +1012,13 @@ ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id) struct ice_hw *hw; int ret = 0; - if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID) + if (!vsi || vlan->vid > RTE_ETHER_MAX_VLAN_ID) return -EINVAL; hw = ICE_VSI_TO_HW(vsi); /* If it's added and configured, return. */ - f = ice_find_vlan_filter(vsi, vlan_id); + f = ice_find_vlan_filter(vsi, vlan); if (f) { PMD_DRV_LOG(INFO, "This VLAN filter already exists."); return 0; @@ -984,7 +1035,9 @@ ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id) ret = -ENOMEM; goto DONE; } - v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id; + v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan->vid; + v_list_itr->fltr_info.l_data.vlan.tpid = vlan->tpid; + v_list_itr->fltr_info.l_data.vlan.tpid_valid = true; v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN; @@ -1008,7 +1061,8 @@ ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id) ret = -ENOMEM; goto DONE; } - f->vlan_info.vlan_id = vlan_id; + f->vlan_info.vlan.tpid = vlan->tpid; + f->vlan_info.vlan.vid = vlan->vid; TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next); vsi->vlan_num++; @@ -1020,7 +1074,7 @@ DONE: } static int -ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id) +ice_remove_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan) { struct ice_fltr_list_entry *v_list_itr = NULL; struct ice_vlan_filter *f; @@ -1028,17 +1082,13 @@ ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id) struct ice_hw *hw; int ret = 0; - /** - * Vlan 0 is the generic filter for untagged packets - * and can't be removed. - */ - if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID) + if (!vsi || vlan->vid > RTE_ETHER_MAX_VLAN_ID) return -EINVAL; hw = ICE_VSI_TO_HW(vsi); /* Can't find it, return an error */ - f = ice_find_vlan_filter(vsi, vlan_id); + f = ice_find_vlan_filter(vsi, vlan); if (!f) return -EINVAL; @@ -1051,7 +1101,9 @@ ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id) goto DONE; } - v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id; + v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan->vid; + v_list_itr->fltr_info.l_data.vlan.tpid = vlan->tpid; + v_list_itr->fltr_info.l_data.vlan.tpid_valid = true; v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN; @@ -1084,12 +1136,13 @@ ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi) { struct ice_mac_filter *m_f; struct ice_vlan_filter *v_f; + void *temp; int ret = 0; if (!vsi || !vsi->mac_num) return -EINVAL; - TAILQ_FOREACH(m_f, &vsi->mac_list, next) { + RTE_TAILQ_FOREACH_SAFE(m_f, &vsi->mac_list, next, temp) { ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr); if (ret != ICE_SUCCESS) { ret = -EINVAL; @@ -1100,8 +1153,8 @@ ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi) if (vsi->vlan_num == 0) return 0; - TAILQ_FOREACH(v_f, &vsi->vlan_list, next) { - ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id); + RTE_TAILQ_FOREACH_SAFE(v_f, &vsi->vlan_list, next, temp) { + ret = ice_remove_vlan_filter(vsi, &v_f->vlan_info.vlan); if (ret != ICE_SUCCESS) { ret = -EINVAL; goto DONE; @@ -1112,127 +1165,6 @@ DONE: return ret; } -static int -ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on) -{ - struct ice_hw *hw = ICE_VSI_TO_HW(vsi); - struct ice_vsi_ctx ctxt; - uint8_t qinq_flags; - int ret = 0; - - /* Check if it has been already on or off */ - if (vsi->info.valid_sections & - rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) { - if (on) { - if ((vsi->info.outer_tag_flags & - ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) == - ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) - return 0; /* already on */ - } else { - if (!(vsi->info.outer_tag_flags & - ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)) - return 0; /* already off */ - } - } - - if (on) - qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST; - else - qinq_flags = 0; - /* clear global insertion and use per packet insertion */ - vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT); - vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST); - vsi->info.outer_tag_flags |= qinq_flags; - /* use default vlan type 0x8100 */ - vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M); - vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE << - ICE_AQ_VSI_OUTER_TAG_TYPE_S; - (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); - ctxt.info.valid_sections = - rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); - ctxt.vsi_num = vsi->vsi_id; - ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); - if (ret) { - PMD_DRV_LOG(INFO, - "Update VSI failed to %s qinq stripping", - on ? "enable" : "disable"); - return -EINVAL; - } - - vsi->info.valid_sections |= - rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); - - return ret; -} - -static int -ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on) -{ - struct ice_hw *hw = ICE_VSI_TO_HW(vsi); - struct ice_vsi_ctx ctxt; - uint8_t qinq_flags; - int ret = 0; - - /* Check if it has been already on or off */ - if (vsi->info.valid_sections & - rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) { - if (on) { - if ((vsi->info.outer_tag_flags & - ICE_AQ_VSI_OUTER_TAG_MODE_M) == - ICE_AQ_VSI_OUTER_TAG_COPY) - return 0; /* already on */ - } else { - if ((vsi->info.outer_tag_flags & - ICE_AQ_VSI_OUTER_TAG_MODE_M) == - ICE_AQ_VSI_OUTER_TAG_NOTHING) - return 0; /* already off */ - } - } - - if (on) - qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY; - else - qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING; - vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M); - vsi->info.outer_tag_flags |= qinq_flags; - /* use default vlan type 0x8100 */ - vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M); - vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE << - ICE_AQ_VSI_OUTER_TAG_TYPE_S; - (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); - ctxt.info.valid_sections = - rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); - ctxt.vsi_num = vsi->vsi_id; - ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); - if (ret) { - PMD_DRV_LOG(INFO, - "Update VSI failed to %s qinq stripping", - on ? "enable" : "disable"); - return -EINVAL; - } - - vsi->info.valid_sections |= - rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); - - return ret; -} - -static int -ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on) -{ - int ret; - - ret = ice_vsi_config_qinq_stripping(vsi, on); - if (ret) - PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret); - - ret = ice_vsi_config_qinq_insertion(vsi, on); - if (ret) - PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret); - - return ret; -} - /* Enable IRQ0 */ static void ice_pf_enable_irq0(struct ice_hw *hw) @@ -1312,7 +1244,7 @@ ice_handle_aq_msg(struct rte_eth_dev *dev) case ice_aqc_opc_get_link_status: ret = ice_link_update(dev, 0); if (!ret) - _rte_eth_dev_callback_process + rte_eth_dev_callback_process (dev, RTE_ETH_EVENT_INTR_LSC, NULL); break; default: @@ -1332,7 +1264,7 @@ ice_handle_aq_msg(struct rte_eth_dev *dev) * @param handle * Pointer to interrupt handle. * @param param - * The address of parameter (struct rte_eth_dev *) regsitered before. + * The address of parameter (struct rte_eth_dev *) registered before. * * @return * void @@ -1377,7 +1309,7 @@ ice_interrupt_handler(void *param) PMD_DRV_LOG(INFO, "OICR: link state change event"); ret = ice_link_update(dev, 0); if (!ret) - _rte_eth_dev_callback_process + rte_eth_dev_callback_process (dev, RTE_ETH_EVENT_INTR_LSC, NULL); } #endif @@ -1430,11 +1362,6 @@ ice_init_proto_xtr(struct rte_eth_dev *dev) int offset; uint16_t i; - if (!ice_proto_xtr_support(hw)) { - PMD_DRV_LOG(NOTICE, "Protocol extraction is not supported"); - return; - } - pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0); if (unlikely(pf->proto_xtr == NULL)) { PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table"); @@ -1457,6 +1384,8 @@ ice_init_proto_xtr(struct rte_eth_dev *dev) if (likely(!proto_xtr_enable)) return; + ice_check_proto_xtr_support(hw); + offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param); if (unlikely(offset == -1)) { PMD_DRV_LOG(ERR, @@ -1476,6 +1405,14 @@ ice_init_proto_xtr(struct rte_eth_dev *dev) if (!ol_flag->required) continue; + if (!ice_proto_xtr_hw_support[i]) { + PMD_DRV_LOG(ERR, + "Protocol extraction type %u is not supported in hardware", + i); + rte_net_ice_dynfield_proto_xtr_metadata_offs = -1; + break; + } + offset = rte_mbuf_dynflag_register(&ol_flag->param); if (unlikely(offset == -1)) { PMD_DRV_LOG(ERR, @@ -1550,9 +1487,9 @@ ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type) TAILQ_INIT(&vsi->mac_list); TAILQ_INIT(&vsi->vlan_list); - /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */ + /* Be sync with RTE_ETH_RSS_RETA_SIZE_x maximum value definition */ pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size > - ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 : + RTE_ETH_RSS_RETA_SIZE_512 ? RTE_ETH_RSS_RETA_SIZE_512 : hw->func_caps.common_cap.rss_table_size; pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE; @@ -1570,10 +1507,20 @@ ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type) vsi_ctx.info.sw_id = hw->port_info->sw_id; vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA; /* Allow all untagged or tagged packets */ - vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL; - vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING; + vsi_ctx.info.inner_vlan_flags = ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL; + vsi_ctx.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING; vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF | ICE_AQ_VSI_Q_OPT_RSS_TPLZ; + if (ice_is_dvm_ena(hw)) { + vsi_ctx.info.outer_vlan_flags = + (ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL << + ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) & + ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M; + vsi_ctx.info.outer_vlan_flags |= + (ICE_AQ_VSI_OUTER_TAG_VLAN_8100 << + ICE_AQ_VSI_OUTER_TAG_TYPE_S) & + ICE_AQ_VSI_OUTER_TAG_TYPE_M; + } /* FDIR */ cfg = ICE_AQ_VSI_PROP_SECURITY_VALID | @@ -1680,7 +1627,7 @@ ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type) } /* At the beginning, only TC0. */ - /* What we need here is the maximam number of the TX queues. + /* What we need here is the maximum number of the TX queues. * Currently vsi->nb_qps means it. * Correct it if any change. */ @@ -1744,95 +1691,6 @@ ice_pf_setup(struct ice_pf *pf) return 0; } -/* PCIe configuration space setting */ -#define PCI_CFG_SPACE_SIZE 256 -#define PCI_CFG_SPACE_EXP_SIZE 4096 -#define PCI_EXT_CAP_ID(header) (int)((header) & 0x0000ffff) -#define PCI_EXT_CAP_NEXT(header) (((header) >> 20) & 0xffc) -#define PCI_EXT_CAP_ID_DSN 0x03 - -static int -ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap) -{ - uint32_t header; - int ttl; - int pos = PCI_CFG_SPACE_SIZE; - - /* minimum 8 bytes per capability */ - ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; - - if (rte_pci_read_config(dev, &header, 4, pos) < 0) { - PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n"); - return -1; - } - - /* - * If we have no capabilities, this is indicated by cap ID, - * cap version and next pointer all being 0. - */ - if (header == 0) - return 0; - - while (ttl-- > 0) { - if (PCI_EXT_CAP_ID(header) == cap) - return pos; - - pos = PCI_EXT_CAP_NEXT(header); - - if (pos < PCI_CFG_SPACE_SIZE) - break; - - if (rte_pci_read_config(dev, &header, 4, pos) < 0) { - PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n"); - return -1; - } - } - - return 0; -} - -/* - * Extract device serial number from PCIe Configuration Space and - * determine the pkg file path according to the DSN. - */ -static int -ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file) -{ - int pos; - char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE]; - uint32_t dsn_low, dsn_high; - memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE); - - pos = ice_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN); - - if (pos) { - rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4); - rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8); - snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE, - "ice-%08x%08x.pkg", dsn_high, dsn_low); - } else { - PMD_INIT_LOG(ERR, "Failed to read device serial number\n"); - goto fail_dsn; - } - - strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES, - ICE_MAX_PKG_FILENAME_SIZE); - if (!access(strcat(pkg_file, opt_ddp_filename), 0)) - return 0; - - strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT, - ICE_MAX_PKG_FILENAME_SIZE); - if (!access(strcat(pkg_file, opt_ddp_filename), 0)) - return 0; - -fail_dsn: - strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE); - if (!access(pkg_file, 0)) - return 0; - strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE); - return 0; -} - static enum ice_pkg_type ice_load_pkg_type(struct ice_hw *hw) { @@ -1848,83 +1706,67 @@ ice_load_pkg_type(struct ice_hw *hw) else package_type = ICE_PKG_TYPE_UNKNOWN; - PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s", + PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s (%s VLAN mode)", hw->active_pkg_ver.major, hw->active_pkg_ver.minor, hw->active_pkg_ver.update, hw->active_pkg_ver.draft, - hw->active_pkg_name); + hw->active_pkg_name, + ice_is_dvm_ena(hw) ? "double" : "single"); return package_type; } -static int ice_load_pkg(struct rte_eth_dev *dev) +int ice_load_pkg(struct ice_adapter *adapter, bool use_dsn, uint64_t dsn) { - struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct ice_hw *hw = &adapter->hw; char pkg_file[ICE_MAX_PKG_FILENAME_SIZE]; + char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE]; + void *buf; + size_t bufsz; int err; - uint8_t *buf; - int buf_len; - FILE *file; - struct stat fstat; - struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); - struct ice_adapter *ad = - ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); - ice_pkg_file_search_path(pci_dev, pkg_file); + if (!use_dsn) + goto no_dsn; - file = fopen(pkg_file, "rb"); - if (!file) { - PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file); - return -1; - } + memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE); + snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE, + "ice-%016" PRIx64 ".pkg", dsn); + strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES, + ICE_MAX_PKG_FILENAME_SIZE); + strcat(pkg_file, opt_ddp_filename); + if (rte_firmware_read(pkg_file, &buf, &bufsz) == 0) + goto load_fw; - err = stat(pkg_file, &fstat); - if (err) { - PMD_INIT_LOG(ERR, "failed to get file stats\n"); - fclose(file); - return err; - } + strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT, + ICE_MAX_PKG_FILENAME_SIZE); + strcat(pkg_file, opt_ddp_filename); + if (rte_firmware_read(pkg_file, &buf, &bufsz) == 0) + goto load_fw; - buf_len = fstat.st_size; - buf = rte_malloc(NULL, buf_len, 0); +no_dsn: + strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE); + if (rte_firmware_read(pkg_file, &buf, &bufsz) == 0) + goto load_fw; - if (!buf) { - PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n", - buf_len); - fclose(file); + strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE); + if (rte_firmware_read(pkg_file, &buf, &bufsz) < 0) { + PMD_INIT_LOG(ERR, "failed to search file path\n"); return -1; } - err = fread(buf, buf_len, 1, file); - if (err != 1) { - PMD_INIT_LOG(ERR, "failed to read package data\n"); - fclose(file); - err = -1; - goto fail_exit; - } - - fclose(file); +load_fw: + PMD_INIT_LOG(DEBUG, "DDP package name: %s", pkg_file); - err = ice_copy_and_init_pkg(hw, buf, buf_len); + err = ice_copy_and_init_pkg(hw, buf, bufsz); if (err) { PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err); - goto fail_exit; + goto out; } /* store the loaded pkg type info */ - ad->active_pkg_type = ice_load_pkg_type(hw); - - err = ice_init_hw_tbls(hw); - if (err) { - PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err); - goto fail_init_tbls; - } - - return 0; + adapter->active_pkg_type = ice_load_pkg_type(hw); -fail_init_tbls: - rte_free(hw->pkg_copy); -fail_exit: - rte_free(buf); +out: + free(buf); return err; } @@ -1963,6 +1805,144 @@ parse_bool(const char *key, const char *value, void *args) return 0; } +static int +parse_u64(const char *key, const char *value, void *args) +{ + u64 *num = (u64 *)args; + u64 tmp; + + errno = 0; + tmp = strtoull(value, NULL, 16); + if (errno) { + PMD_DRV_LOG(WARNING, "%s: \"%s\" is not a valid u64", + key, value); + return -1; + } + + *num = tmp; + + return 0; +} + +static int +lookup_pps_type(const char *pps_name) +{ + static struct { + const char *name; + enum pps_type type; + } pps_type_map[] = { + { "pin", PPS_PIN }, + }; + + uint32_t i; + + for (i = 0; i < RTE_DIM(pps_type_map); i++) { + if (strcmp(pps_name, pps_type_map[i].name) == 0) + return pps_type_map[i].type; + } + + return -1; +} + +static int +parse_pin_set(const char *input, int pps_type, struct ice_devargs *devargs) +{ + const char *str = input; + char *end = NULL; + uint32_t idx; + + while (isblank(*str)) + str++; + + if (!isdigit(*str)) + return -1; + + if (pps_type == PPS_PIN) { + idx = strtoul(str, &end, 10); + if (end == NULL || idx >= ICE_MAX_PIN_NUM) + return -1; + while (isblank(*end)) + end++; + if (*end != ']') + return -1; + + devargs->pin_idx = idx; + devargs->pps_out_ena = 1; + + return 0; + } + + return -1; +} + +static int +parse_pps_out_parameter(const char *pins, struct ice_devargs *devargs) +{ + const char *pin_start; + uint32_t idx; + int pps_type; + char pps_name[32]; + + while (isblank(*pins)) + pins++; + + pins++; + while (isblank(*pins)) + pins++; + if (*pins == '\0') + return -1; + + for (idx = 0; ; idx++) { + if (isblank(pins[idx]) || + pins[idx] == ':' || + pins[idx] == '\0') + break; + + pps_name[idx] = pins[idx]; + } + pps_name[idx] = '\0'; + pps_type = lookup_pps_type(pps_name); + if (pps_type < 0) + return -1; + + pins += idx; + + pins += strcspn(pins, ":"); + if (*pins++ != ':') + return -1; + while (isblank(*pins)) + pins++; + + pin_start = pins; + + while (isblank(*pins)) + pins++; + + if (parse_pin_set(pin_start, pps_type, devargs) < 0) + return -1; + + return 0; +} + +static int +handle_pps_out_arg(__rte_unused const char *key, const char *value, + void *extra_args) +{ + struct ice_devargs *devargs = extra_args; + + if (value == NULL || extra_args == NULL) + return -EINVAL; + + if (parse_pps_out_parameter(value, devargs) < 0) { + PMD_DRV_LOG(ERR, + "The GPIO pin parameter is wrong : '%s'", + value); + return -1; + } + + return 0; +} + static int ice_parse_devargs(struct rte_eth_dev *dev) { struct ice_adapter *ad = @@ -1999,11 +1979,19 @@ static int ice_parse_devargs(struct rte_eth_dev *dev) if (ret) goto bail; - ret = rte_kvargs_process(kvlist, ICE_FLOW_MARK_SUPPORT_ARG, - &parse_bool, &ad->devargs.flow_mark_support); + ret = rte_kvargs_process(kvlist, ICE_HW_DEBUG_MASK_ARG, + &parse_u64, &ad->hw.debug_mask); if (ret) goto bail; + ret = rte_kvargs_process(kvlist, ICE_ONE_PPS_OUT_ARG, + &handle_pps_out_arg, &ad->devargs); + if (ret) + goto bail; + + ret = rte_kvargs_process(kvlist, ICE_RX_LOW_LATENCY_ARG, + &parse_bool, &ad->devargs.rx_low_latency); + bail: rte_kvargs_free(kvlist); return ret; @@ -2046,7 +2034,7 @@ ice_get_hw_res(struct ice_hw *hw, uint16_t res_type, uint16_t num, uint16_t desc_id, uint16_t *prof_buf, uint16_t *num_prof) { - struct ice_aqc_get_allocd_res_desc_resp *resp_buf; + struct ice_aqc_res_elem *resp_buf; int ret; uint16_t buf_len; bool res_shared = 1; @@ -2055,7 +2043,7 @@ ice_get_hw_res(struct ice_hw *hw, uint16_t res_type, struct ice_aqc_get_allocd_res_desc *cmd = &aq_desc.params.get_res_desc; - buf_len = sizeof(resp_buf->elem) * num; + buf_len = sizeof(*resp_buf) * num; resp_buf = ice_malloc(hw, buf_len); if (!resp_buf) return -ENOMEM; @@ -2074,7 +2062,7 @@ ice_get_hw_res(struct ice_hw *hw, uint16_t res_type, else goto exit; - ice_memcpy(prof_buf, resp_buf->elem, sizeof(resp_buf->elem) * + ice_memcpy(prof_buf, resp_buf, sizeof(*resp_buf) * (*num_prof), ICE_NONDMA_TO_NONDMA); exit: @@ -2127,6 +2115,30 @@ ice_reset_fxp_resource(struct ice_hw *hw) return 0; } +static void +ice_rss_ctx_init(struct ice_pf *pf) +{ + memset(&pf->hash_ctx, 0, sizeof(pf->hash_ctx)); +} + +static uint64_t +ice_get_supported_rxdid(struct ice_hw *hw) +{ + uint64_t supported_rxdid = 0; /* bitmap for supported RXDID */ + uint32_t regval; + int i; + + supported_rxdid |= BIT(ICE_RXDID_LEGACY_1); + + for (i = ICE_RXDID_FLEX_NIC; i < ICE_FLEX_DESC_RXDID_MAX_NUM; i++) { + regval = ICE_READ_REG(hw, GLFLXP_RXDID_FLAGS(i, 0)); + if ((regval >> GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S) + & GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M) + supported_rxdid |= BIT(i); + } + return supported_rxdid; +} + static int ice_dev_init(struct rte_eth_dev *dev) { @@ -2138,8 +2150,17 @@ ice_dev_init(struct rte_eth_dev *dev) ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); struct ice_vsi *vsi; int ret; +#ifndef RTE_EXEC_ENV_WINDOWS + off_t pos; + uint32_t dsn_low, dsn_high; + uint64_t dsn; + bool use_dsn; +#endif dev->dev_ops = &ice_eth_dev_ops; + dev->rx_queue_count = ice_rx_queue_count; + dev->rx_descriptor_status = ice_rx_descriptor_status; + dev->tx_descriptor_status = ice_tx_descriptor_status; dev->rx_pkt_burst = ice_recv_pkts; dev->tx_pkt_burst = ice_xmit_pkts; dev->tx_pkt_prepare = ice_prep_pkts; @@ -2153,12 +2174,13 @@ ice_dev_init(struct rte_eth_dev *dev) return 0; } + dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; + ice_set_default_ptype_table(dev); pci_dev = RTE_DEV_TO_PCI(dev->device); - intr_handle = &pci_dev->intr_handle; + intr_handle = pci_dev->intr_handle; pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); - pf->adapter->eth_dev = dev; pf->dev_data = dev->data; hw->back = pf->adapter; hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr; @@ -2183,18 +2205,43 @@ ice_dev_init(struct rte_eth_dev *dev) return -EINVAL; } - ret = ice_load_pkg(dev); +#ifndef RTE_EXEC_ENV_WINDOWS + use_dsn = false; + dsn = 0; + pos = rte_pci_find_ext_capability(pci_dev, RTE_PCI_EXT_CAP_ID_DSN); + if (pos) { + if (rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4) < 0 || + rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8) < 0) { + PMD_INIT_LOG(ERR, "Failed to read pci config space\n"); + } else { + use_dsn = true; + dsn = (uint64_t)dsn_high << 32 | dsn_low; + } + } else { + PMD_INIT_LOG(ERR, "Failed to read device serial number\n"); + } + + ret = ice_load_pkg(pf->adapter, use_dsn, dsn); + if (ret == 0) { + ret = ice_init_hw_tbls(hw); + if (ret) { + PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", ret); + rte_free(hw->pkg_copy); + } + } + if (ret) { if (ad->devargs.safe_mode_support == 0) { PMD_INIT_LOG(ERR, "Failed to load the DDP package," "Use safe-mode-support=1 to enter Safe Mode"); - return ret; + goto err_init_fw; } PMD_INIT_LOG(WARNING, "Failed to load the DDP package," "Entering Safe Mode"); ad->is_safe_mode = 1; } +#endif PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d", hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build, @@ -2207,11 +2254,6 @@ ice_dev_init(struct rte_eth_dev *dev) goto err_init_mac; } - /* Pass the information to the rte_eth_dev_close() that it should also - * release the private port resources. - */ - dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; - ret = ice_res_pool_init(&pf->msix_pool, 1, hw->func_caps.common_cap.num_msix_vectors - 1); if (ret) { @@ -2233,9 +2275,6 @@ ice_dev_init(struct rte_eth_dev *dev) vsi = pf->main_vsi; - /* Disable double vlan by default */ - ice_vsi_config_double_vlan(vsi, false); - ret = ice_aq_stop_lldp(hw, true, false, NULL); if (ret != ICE_SUCCESS) PMD_INIT_LOG(DEBUG, "lldp has already stopped\n"); @@ -2258,32 +2297,44 @@ ice_dev_init(struct rte_eth_dev *dev) /* get base queue pairs index in the device */ ice_base_queue_get(pf); + /* Initialize RSS context for gtpu_eh */ + ice_rss_ctx_init(pf); + if (!ad->is_safe_mode) { ret = ice_flow_init(ad); if (ret) { PMD_INIT_LOG(ERR, "Failed to initialize flow"); - return ret; + goto err_flow_init; } } ret = ice_reset_fxp_resource(hw); if (ret) { PMD_INIT_LOG(ERR, "Failed to reset fxp resource"); - return ret; + goto err_flow_init; } + pf->supported_rxdid = ice_get_supported_rxdid(hw); + return 0; +err_flow_init: + ice_flow_uninit(ad); + rte_intr_disable(intr_handle); + ice_pf_disable_irq0(hw); + rte_intr_callback_unregister(intr_handle, + ice_interrupt_handler, dev); err_pf_setup: ice_res_pool_destroy(&pf->msix_pool); err_msix_pool_init: rte_free(dev->data->mac_addrs); dev->data->mac_addrs = NULL; err_init_mac: - ice_sched_cleanup_all(hw); - rte_free(hw->port_info); - ice_shutdown_all_ctrlq(hw); rte_free(pf->proto_xtr); +#ifndef RTE_EXEC_ENV_WINDOWS +err_init_fw: +#endif + ice_deinit_hw(hw); return ret; } @@ -2294,9 +2345,10 @@ ice_release_vsi(struct ice_vsi *vsi) struct ice_hw *hw; struct ice_vsi_ctx vsi_ctx; enum ice_status ret; + int error = 0; if (!vsi) - return 0; + return error; hw = ICE_VSI_TO_HW(vsi); @@ -2309,20 +2361,21 @@ ice_release_vsi(struct ice_vsi *vsi) ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL); if (ret != ICE_SUCCESS) { PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id); - rte_free(vsi); - return -1; + error = -1; } + rte_free(vsi->rss_lut); + rte_free(vsi->rss_key); rte_free(vsi); - return 0; + return error; } void ice_vsi_disable_queues_intr(struct ice_vsi *vsi) { - struct rte_eth_dev *dev = vsi->adapter->eth_dev; + struct rte_eth_dev *dev = &rte_eth_devices[vsi->adapter->pf.dev_data->port_id]; struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); - struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; + struct rte_intr_handle *intr_handle = pci_dev->intr_handle; struct ice_hw *hw = ICE_VSI_TO_HW(vsi); uint16_t msix_intr, i; @@ -2345,19 +2398,19 @@ ice_vsi_disable_queues_intr(struct ice_vsi *vsi) ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M); } -static void +static int ice_dev_stop(struct rte_eth_dev *dev) { struct rte_eth_dev_data *data = dev->data; struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); struct ice_vsi *main_vsi = pf->main_vsi; struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); - struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; + struct rte_intr_handle *intr_handle = pci_dev->intr_handle; uint16_t i; /* avoid stopping again */ if (pf->adapter_stopped) - return; + return 0; /* stop and clear all Rx queues */ for (i = 0; i < data->nb_rx_queues; i++) @@ -2377,23 +2430,30 @@ ice_dev_stop(struct rte_eth_dev *dev) /* Clean datapath event and queue/vec mapping */ rte_intr_efd_disable(intr_handle); - if (intr_handle->intr_vec) { - rte_free(intr_handle->intr_vec); - intr_handle->intr_vec = NULL; - } + rte_intr_vec_list_free(intr_handle); pf->adapter_stopped = true; + dev->data->dev_started = 0; + + return 0; } -static void +static int ice_dev_close(struct rte_eth_dev *dev) { struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); - struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; + struct rte_intr_handle *intr_handle = pci_dev->intr_handle; struct ice_adapter *ad = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); + int ret; + uint32_t val; + uint8_t timer = hw->func_caps.ts_func_info.tmr_index_owned; + uint32_t pin_idx = ad->devargs.pin_idx; + + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return 0; /* Since stop will make link down, then the link event will be * triggered, disable the irq firstly to avoid the port_infoe etc @@ -2402,7 +2462,7 @@ ice_dev_close(struct rte_eth_dev *dev) */ ice_pf_disable_irq0(hw); - ice_dev_stop(dev); + ret = ice_dev_stop(dev); if (!ad->is_safe_mode) ice_flow_uninit(ad); @@ -2420,12 +2480,15 @@ ice_dev_close(struct rte_eth_dev *dev) rte_free(pf->proto_xtr); pf->proto_xtr = NULL; - dev->dev_ops = NULL; - dev->rx_pkt_burst = NULL; - dev->tx_pkt_burst = NULL; + if (ad->devargs.pps_out_ena) { + ICE_WRITE_REG(hw, GLTSYN_AUX_OUT(pin_idx, timer), 0); + ICE_WRITE_REG(hw, GLTSYN_CLKO(pin_idx, timer), 0); + ICE_WRITE_REG(hw, GLTSYN_TGT_L(pin_idx, timer), 0); + ICE_WRITE_REG(hw, GLTSYN_TGT_H(pin_idx, timer), 0); - rte_free(dev->data->mac_addrs); - dev->data->mac_addrs = NULL; + val = GLGEN_GPIO_CTL_PIN_DIR_M; + ICE_WRITE_REG(hw, GLGEN_GPIO_CTL(pin_idx), val); + } /* disable uio intr before callback unregister */ rte_intr_disable(intr_handle); @@ -2433,6 +2496,8 @@ ice_dev_close(struct rte_eth_dev *dev) /* unregister callback func from eal lib */ rte_intr_callback_unregister(intr_handle, ice_interrupt_handler, dev); + + return ret; } static int @@ -2443,29 +2508,684 @@ ice_dev_uninit(struct rte_eth_dev *dev) return 0; } +static bool +is_hash_cfg_valid(struct ice_rss_hash_cfg *cfg) +{ + return (cfg->hash_flds != 0 && cfg->addl_hdrs != 0) ? true : false; +} + +static void +hash_cfg_reset(struct ice_rss_hash_cfg *cfg) +{ + cfg->hash_flds = 0; + cfg->addl_hdrs = 0; + cfg->symm = 0; + cfg->hdr_type = ICE_RSS_OUTER_HEADERS; +} + static int -ice_dev_configure(struct rte_eth_dev *dev) +ice_hash_moveout(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg) { - struct ice_adapter *ad = - ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); + enum ice_status status = ICE_SUCCESS; + struct ice_hw *hw = ICE_PF_TO_HW(pf); + struct ice_vsi *vsi = pf->main_vsi; - /* Initialize to TRUE. If any of Rx queues doesn't meet the - * bulk allocation or vector Rx preconditions we will reset it. - */ - ad->rx_bulk_alloc_allowed = true; - ad->tx_simple_allowed = true; + if (!is_hash_cfg_valid(cfg)) + return -ENOENT; + + status = ice_rem_rss_cfg(hw, vsi->idx, cfg); + if (status && status != ICE_ERR_DOES_NOT_EXIST) { + PMD_DRV_LOG(ERR, + "ice_rem_rss_cfg failed for VSI:%d, error:%d\n", + vsi->idx, status); + return -EBUSY; + } + + return 0; +} + +static int +ice_hash_moveback(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg) +{ + enum ice_status status = ICE_SUCCESS; + struct ice_hw *hw = ICE_PF_TO_HW(pf); + struct ice_vsi *vsi = pf->main_vsi; + + if (!is_hash_cfg_valid(cfg)) + return -ENOENT; + + status = ice_add_rss_cfg(hw, vsi->idx, cfg); + if (status) { + PMD_DRV_LOG(ERR, + "ice_add_rss_cfg failed for VSI:%d, error:%d\n", + vsi->idx, status); + return -EBUSY; + } + + return 0; +} + +static int +ice_hash_remove(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg) +{ + int ret; + + ret = ice_hash_moveout(pf, cfg); + if (ret && (ret != -ENOENT)) + return ret; + + hash_cfg_reset(cfg); + + return 0; +} + +static int +ice_add_rss_cfg_pre_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx, + u8 ctx_idx) +{ + int ret; + + switch (ctx_idx) { + case ICE_HASH_GTPU_CTX_EH_IP: + ret = ice_hash_remove(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]); + if (ret && (ret != -ENOENT)) + return ret; + + ret = ice_hash_remove(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]); + if (ret && (ret != -ENOENT)) + return ret; + + ret = ice_hash_remove(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]); + if (ret && (ret != -ENOENT)) + return ret; + + ret = ice_hash_remove(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]); + if (ret && (ret != -ENOENT)) + return ret; + + ret = ice_hash_remove(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]); + if (ret && (ret != -ENOENT)) + return ret; + + ret = ice_hash_remove(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]); + if (ret && (ret != -ENOENT)) + return ret; + + ret = ice_hash_remove(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]); + if (ret && (ret != -ENOENT)) + return ret; + + ret = ice_hash_remove(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]); + if (ret && (ret != -ENOENT)) + return ret; + + break; + case ICE_HASH_GTPU_CTX_EH_IP_UDP: + ret = ice_hash_remove(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]); + if (ret && (ret != -ENOENT)) + return ret; + + ret = ice_hash_remove(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]); + if (ret && (ret != -ENOENT)) + return ret; + + ret = ice_hash_moveout(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]); + if (ret && (ret != -ENOENT)) + return ret; + + ret = ice_hash_moveout(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]); + if (ret && (ret != -ENOENT)) + return ret; + + ret = ice_hash_moveout(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]); + if (ret && (ret != -ENOENT)) + return ret; + + ret = ice_hash_moveout(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]); + if (ret && (ret != -ENOENT)) + return ret; + + break; + case ICE_HASH_GTPU_CTX_EH_IP_TCP: + ret = ice_hash_remove(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]); + if (ret && (ret != -ENOENT)) + return ret; + + ret = ice_hash_remove(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]); + if (ret && (ret != -ENOENT)) + return ret; + + ret = ice_hash_moveout(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]); + if (ret && (ret != -ENOENT)) + return ret; + + ret = ice_hash_moveout(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]); + if (ret && (ret != -ENOENT)) + return ret; + + ret = ice_hash_moveout(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]); + if (ret && (ret != -ENOENT)) + return ret; + + ret = ice_hash_moveout(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]); + if (ret && (ret != -ENOENT)) + return ret; + + break; + case ICE_HASH_GTPU_CTX_UP_IP: + ret = ice_hash_remove(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]); + if (ret && (ret != -ENOENT)) + return ret; + + ret = ice_hash_remove(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]); + if (ret && (ret != -ENOENT)) + return ret; + + ret = ice_hash_moveout(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]); + if (ret && (ret != -ENOENT)) + return ret; + + ret = ice_hash_moveout(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]); + if (ret && (ret != -ENOENT)) + return ret; + + ret = ice_hash_moveout(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]); + if (ret && (ret != -ENOENT)) + return ret; + + break; + case ICE_HASH_GTPU_CTX_UP_IP_UDP: + case ICE_HASH_GTPU_CTX_UP_IP_TCP: + ret = ice_hash_moveout(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]); + if (ret && (ret != -ENOENT)) + return ret; + + ret = ice_hash_moveout(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]); + if (ret && (ret != -ENOENT)) + return ret; + + ret = ice_hash_moveout(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]); + if (ret && (ret != -ENOENT)) + return ret; + + break; + case ICE_HASH_GTPU_CTX_DW_IP: + ret = ice_hash_remove(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]); + if (ret && (ret != -ENOENT)) + return ret; + + ret = ice_hash_remove(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]); + if (ret && (ret != -ENOENT)) + return ret; + + ret = ice_hash_moveout(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]); + if (ret && (ret != -ENOENT)) + return ret; + + ret = ice_hash_moveout(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]); + if (ret && (ret != -ENOENT)) + return ret; + + ret = ice_hash_moveout(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]); + if (ret && (ret != -ENOENT)) + return ret; + + break; + case ICE_HASH_GTPU_CTX_DW_IP_UDP: + case ICE_HASH_GTPU_CTX_DW_IP_TCP: + ret = ice_hash_moveout(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]); + if (ret && (ret != -ENOENT)) + return ret; + + ret = ice_hash_moveout(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]); + if (ret && (ret != -ENOENT)) + return ret; + + ret = ice_hash_moveout(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]); + if (ret && (ret != -ENOENT)) + return ret; + + break; + default: + break; + } + + return 0; +} + +static u8 calc_gtpu_ctx_idx(uint32_t hdr) +{ + u8 eh_idx, ip_idx; + + if (hdr & ICE_FLOW_SEG_HDR_GTPU_EH) + eh_idx = 0; + else if (hdr & ICE_FLOW_SEG_HDR_GTPU_UP) + eh_idx = 1; + else if (hdr & ICE_FLOW_SEG_HDR_GTPU_DWN) + eh_idx = 2; + else + return ICE_HASH_GTPU_CTX_MAX; + + ip_idx = 0; + if (hdr & ICE_FLOW_SEG_HDR_UDP) + ip_idx = 1; + else if (hdr & ICE_FLOW_SEG_HDR_TCP) + ip_idx = 2; + + if (hdr & (ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6)) + return eh_idx * 3 + ip_idx; + else + return ICE_HASH_GTPU_CTX_MAX; +} + +static int +ice_add_rss_cfg_pre(struct ice_pf *pf, uint32_t hdr) +{ + u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr); + + if (hdr & ICE_FLOW_SEG_HDR_IPV4) + return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu4, + gtpu_ctx_idx); + else if (hdr & ICE_FLOW_SEG_HDR_IPV6) + return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu6, + gtpu_ctx_idx); + + return 0; +} + +static int +ice_add_rss_cfg_post_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx, + u8 ctx_idx, struct ice_rss_hash_cfg *cfg) +{ + int ret; + + if (ctx_idx < ICE_HASH_GTPU_CTX_MAX) + ctx->ctx[ctx_idx] = *cfg; + + switch (ctx_idx) { + case ICE_HASH_GTPU_CTX_EH_IP: + break; + case ICE_HASH_GTPU_CTX_EH_IP_UDP: + ret = ice_hash_moveback(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]); + if (ret && (ret != -ENOENT)) + return ret; + + ret = ice_hash_moveback(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]); + if (ret && (ret != -ENOENT)) + return ret; + + ret = ice_hash_moveback(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]); + if (ret && (ret != -ENOENT)) + return ret; + + ret = ice_hash_moveback(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]); + if (ret && (ret != -ENOENT)) + return ret; + + break; + case ICE_HASH_GTPU_CTX_EH_IP_TCP: + ret = ice_hash_moveback(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]); + if (ret && (ret != -ENOENT)) + return ret; + + ret = ice_hash_moveback(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]); + if (ret && (ret != -ENOENT)) + return ret; + + ret = ice_hash_moveback(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]); + if (ret && (ret != -ENOENT)) + return ret; + + ret = ice_hash_moveback(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]); + if (ret && (ret != -ENOENT)) + return ret; + + break; + case ICE_HASH_GTPU_CTX_UP_IP: + case ICE_HASH_GTPU_CTX_UP_IP_UDP: + case ICE_HASH_GTPU_CTX_UP_IP_TCP: + case ICE_HASH_GTPU_CTX_DW_IP: + case ICE_HASH_GTPU_CTX_DW_IP_UDP: + case ICE_HASH_GTPU_CTX_DW_IP_TCP: + ret = ice_hash_moveback(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]); + if (ret && (ret != -ENOENT)) + return ret; + + ret = ice_hash_moveback(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]); + if (ret && (ret != -ENOENT)) + return ret; + + ret = ice_hash_moveback(pf, + &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]); + if (ret && (ret != -ENOENT)) + return ret; + + break; + default: + break; + } + + return 0; +} + +static int +ice_add_rss_cfg_post(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg) +{ + u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(cfg->addl_hdrs); - if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) - dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; + if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV4) + return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu4, + gtpu_ctx_idx, cfg); + else if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV6) + return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu6, + gtpu_ctx_idx, cfg); return 0; } +static void +ice_rem_rss_cfg_post(struct ice_pf *pf, uint32_t hdr) +{ + u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr); + + if (gtpu_ctx_idx >= ICE_HASH_GTPU_CTX_MAX) + return; + + if (hdr & ICE_FLOW_SEG_HDR_IPV4) + hash_cfg_reset(&pf->hash_ctx.gtpu4.ctx[gtpu_ctx_idx]); + else if (hdr & ICE_FLOW_SEG_HDR_IPV6) + hash_cfg_reset(&pf->hash_ctx.gtpu6.ctx[gtpu_ctx_idx]); +} + +int +ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id, + struct ice_rss_hash_cfg *cfg) +{ + struct ice_hw *hw = ICE_PF_TO_HW(pf); + int ret; + + ret = ice_rem_rss_cfg(hw, vsi_id, cfg); + if (ret && ret != ICE_ERR_DOES_NOT_EXIST) + PMD_DRV_LOG(ERR, "remove rss cfg failed\n"); + + ice_rem_rss_cfg_post(pf, cfg->addl_hdrs); + + return 0; +} + +int +ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id, + struct ice_rss_hash_cfg *cfg) +{ + struct ice_hw *hw = ICE_PF_TO_HW(pf); + int ret; + + ret = ice_add_rss_cfg_pre(pf, cfg->addl_hdrs); + if (ret) + PMD_DRV_LOG(ERR, "add rss cfg pre failed\n"); + + ret = ice_add_rss_cfg(hw, vsi_id, cfg); + if (ret) + PMD_DRV_LOG(ERR, "add rss cfg failed\n"); + + ret = ice_add_rss_cfg_post(pf, cfg); + if (ret) + PMD_DRV_LOG(ERR, "add rss cfg post failed\n"); + + return 0; +} + +static void +ice_rss_hash_set(struct ice_pf *pf, uint64_t rss_hf) +{ + struct ice_hw *hw = ICE_PF_TO_HW(pf); + struct ice_vsi *vsi = pf->main_vsi; + struct ice_rss_hash_cfg cfg; + int ret; + +#define ICE_RSS_HF_ALL ( \ + RTE_ETH_RSS_IPV4 | \ + RTE_ETH_RSS_IPV6 | \ + RTE_ETH_RSS_NONFRAG_IPV4_UDP | \ + RTE_ETH_RSS_NONFRAG_IPV6_UDP | \ + RTE_ETH_RSS_NONFRAG_IPV4_TCP | \ + RTE_ETH_RSS_NONFRAG_IPV6_TCP | \ + RTE_ETH_RSS_NONFRAG_IPV4_SCTP | \ + RTE_ETH_RSS_NONFRAG_IPV6_SCTP) + + ret = ice_rem_vsi_rss_cfg(hw, vsi->idx); + if (ret) + PMD_DRV_LOG(ERR, "%s Remove rss vsi fail %d", + __func__, ret); + + cfg.symm = 0; + cfg.hdr_type = ICE_RSS_OUTER_HEADERS; + /* Configure RSS for IPv4 with src/dst addr as input set */ + if (rss_hf & RTE_ETH_RSS_IPV4) { + cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER; + cfg.hash_flds = ICE_FLOW_HASH_IPV4; + ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); + if (ret) + PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", + __func__, ret); + } + + /* Configure RSS for IPv6 with src/dst addr as input set */ + if (rss_hf & RTE_ETH_RSS_IPV6) { + cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER; + cfg.hash_flds = ICE_FLOW_HASH_IPV6; + ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); + if (ret) + PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", + __func__, ret); + } + + /* Configure RSS for udp4 with src/dst addr and port as input set */ + if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_UDP) { + cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4 | + ICE_FLOW_SEG_HDR_IPV_OTHER; + cfg.hash_flds = ICE_HASH_UDP_IPV4; + ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); + if (ret) + PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", + __func__, ret); + } + + /* Configure RSS for udp6 with src/dst addr and port as input set */ + if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV6_UDP) { + cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6 | + ICE_FLOW_SEG_HDR_IPV_OTHER; + cfg.hash_flds = ICE_HASH_UDP_IPV6; + ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); + if (ret) + PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", + __func__, ret); + } + + /* Configure RSS for tcp4 with src/dst addr and port as input set */ + if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_TCP) { + cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4 | + ICE_FLOW_SEG_HDR_IPV_OTHER; + cfg.hash_flds = ICE_HASH_TCP_IPV4; + ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); + if (ret) + PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", + __func__, ret); + } + + /* Configure RSS for tcp6 with src/dst addr and port as input set */ + if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV6_TCP) { + cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6 | + ICE_FLOW_SEG_HDR_IPV_OTHER; + cfg.hash_flds = ICE_HASH_TCP_IPV6; + ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); + if (ret) + PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", + __func__, ret); + } + + /* Configure RSS for sctp4 with src/dst addr and port as input set */ + if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_SCTP) { + cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4 | + ICE_FLOW_SEG_HDR_IPV_OTHER; + cfg.hash_flds = ICE_HASH_SCTP_IPV4; + ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); + if (ret) + PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d", + __func__, ret); + } + + /* Configure RSS for sctp6 with src/dst addr and port as input set */ + if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV6_SCTP) { + cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6 | + ICE_FLOW_SEG_HDR_IPV_OTHER; + cfg.hash_flds = ICE_HASH_SCTP_IPV6; + ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); + if (ret) + PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d", + __func__, ret); + } + + if (rss_hf & RTE_ETH_RSS_IPV4) { + cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV4 | + ICE_FLOW_SEG_HDR_IPV_OTHER; + cfg.hash_flds = ICE_FLOW_HASH_IPV4; + ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); + if (ret) + PMD_DRV_LOG(ERR, "%s PPPoE_IPV4 rss flow fail %d", + __func__, ret); + } + + if (rss_hf & RTE_ETH_RSS_IPV6) { + cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV6 | + ICE_FLOW_SEG_HDR_IPV_OTHER; + cfg.hash_flds = ICE_FLOW_HASH_IPV6; + ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); + if (ret) + PMD_DRV_LOG(ERR, "%s PPPoE_IPV6 rss flow fail %d", + __func__, ret); + } + + if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_UDP) { + cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP | + ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER; + cfg.hash_flds = ICE_HASH_UDP_IPV4; + ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); + if (ret) + PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_UDP rss flow fail %d", + __func__, ret); + } + + if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV6_UDP) { + cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP | + ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER; + cfg.hash_flds = ICE_HASH_UDP_IPV6; + ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); + if (ret) + PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_UDP rss flow fail %d", + __func__, ret); + } + + if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_TCP) { + cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP | + ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER; + cfg.hash_flds = ICE_HASH_TCP_IPV4; + ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); + if (ret) + PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_TCP rss flow fail %d", + __func__, ret); + } + + if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV6_TCP) { + cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP | + ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER; + cfg.hash_flds = ICE_HASH_TCP_IPV6; + ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); + if (ret) + PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_TCP rss flow fail %d", + __func__, ret); + } + + pf->rss_hf = rss_hf & ICE_RSS_HF_ALL; +} + +static void +ice_get_default_rss_key(uint8_t *rss_key, uint32_t rss_key_size) +{ + static struct ice_aqc_get_set_rss_keys default_key; + static bool default_key_done; + uint8_t *key = (uint8_t *)&default_key; + size_t i; + + if (rss_key_size > sizeof(default_key)) { + PMD_DRV_LOG(WARNING, + "requested size %u is larger than default %zu, " + "only %zu bytes are gotten for key\n", + rss_key_size, sizeof(default_key), + sizeof(default_key)); + } + + if (!default_key_done) { + /* Calculate the default hash key */ + for (i = 0; i < sizeof(default_key); i++) + key[i] = (uint8_t)rte_rand(); + default_key_done = true; + } + rte_memcpy(rss_key, key, RTE_MIN(rss_key_size, sizeof(default_key))); +} + static int ice_init_rss(struct ice_pf *pf) { struct ice_hw *hw = ICE_PF_TO_HW(pf); struct ice_vsi *vsi = pf->main_vsi; - struct rte_eth_dev *dev = pf->adapter->eth_dev; + struct rte_eth_dev_data *dev_data = pf->dev_data; + struct ice_aq_get_set_rss_lut_params lut_params; struct rte_eth_rss_conf *rss_conf; struct ice_aqc_get_set_rss_keys key; uint16_t i, nb_q; @@ -2473,47 +3193,65 @@ static int ice_init_rss(struct ice_pf *pf) bool is_safe_mode = pf->adapter->is_safe_mode; uint32_t reg; - rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf; - nb_q = dev->data->nb_rx_queues; + rss_conf = &dev_data->dev_conf.rx_adv_conf.rss_conf; + nb_q = dev_data->nb_rx_queues; vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE; vsi->rss_lut_size = pf->hash_lut_size; + if (nb_q == 0) { + PMD_DRV_LOG(WARNING, + "RSS is not supported as rx queues number is zero\n"); + return 0; + } + if (is_safe_mode) { PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n"); return 0; } - if (!vsi->rss_key) + if (!vsi->rss_key) { vsi->rss_key = rte_zmalloc(NULL, vsi->rss_key_size, 0); - if (!vsi->rss_lut) + if (vsi->rss_key == NULL) { + PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key"); + return -ENOMEM; + } + } + if (!vsi->rss_lut) { vsi->rss_lut = rte_zmalloc(NULL, vsi->rss_lut_size, 0); - + if (vsi->rss_lut == NULL) { + PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key"); + rte_free(vsi->rss_key); + vsi->rss_key = NULL; + return -ENOMEM; + } + } /* configure RSS key */ - if (!rss_conf->rss_key) { - /* Calculate the default hash key */ - for (i = 0; i <= vsi->rss_key_size; i++) - vsi->rss_key[i] = (uint8_t)rte_rand(); - } else { + if (!rss_conf->rss_key) + ice_get_default_rss_key(vsi->rss_key, vsi->rss_key_size); + else rte_memcpy(vsi->rss_key, rss_conf->rss_key, RTE_MIN(rss_conf->rss_key_len, vsi->rss_key_size)); - } + rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size); ret = ice_aq_set_rss_key(hw, vsi->idx, &key); if (ret) - return -EINVAL; + goto out; /* init RSS LUT table */ for (i = 0; i < vsi->rss_lut_size; i++) vsi->rss_lut[i] = i % nb_q; - ret = ice_aq_set_rss_lut(hw, vsi->idx, - ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, - vsi->rss_lut, vsi->rss_lut_size); + lut_params.vsi_handle = vsi->idx; + lut_params.lut_size = vsi->rss_lut_size; + lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF; + lut_params.lut = vsi->rss_lut; + lut_params.global_lut_id = 0; + ret = ice_aq_set_rss_lut(hw, &lut_params); if (ret) - return -EINVAL; + goto out; /* Enable registers for symmetric_toeplitz function. */ reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id)); @@ -2521,72 +3259,42 @@ static int ice_init_rss(struct ice_pf *pf) (1 << VSIQF_HASH_CTL_HASH_SCHEME_S); ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg); - /* configure RSS for IPv4 with input set IPv4 src/dst */ - ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4, - ICE_FLOW_SEG_HDR_IPV4, 0); - if (ret) - PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", __func__, ret); - - /* configure RSS for IPv6 with input set IPv6 src/dst */ - ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6, - ICE_FLOW_SEG_HDR_IPV6, 0); - if (ret) - PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", __func__, ret); - - /* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */ - ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6, - ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6, 0); - if (ret) - PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", __func__, ret); - - /* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */ - ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6, - ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6, 0); - if (ret) - PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", __func__, ret); - - /* configure RSS for sctp6 with input set IPv6 src/dst */ - ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6, - ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6, 0); - if (ret) - PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d", - __func__, ret); + /* RSS hash configuration */ + ice_rss_hash_set(pf, rss_conf->rss_hf); - /* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */ - ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4, - ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4, 0); - if (ret) - PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", __func__, ret); + return 0; +out: + rte_free(vsi->rss_key); + vsi->rss_key = NULL; + rte_free(vsi->rss_lut); + vsi->rss_lut = NULL; + return -EINVAL; +} - /* configure RSS for udp4 with input set IP src/dst, UDP src/dst */ - ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4, - ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4, 0); - if (ret) - PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", __func__, ret); +static int +ice_dev_configure(struct rte_eth_dev *dev) +{ + struct ice_adapter *ad = + ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); + struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); + int ret; - /* configure RSS for sctp4 with input set IP src/dst */ - ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4, - ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4, 0); - if (ret) - PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d", - __func__, ret); + /* Initialize to TRUE. If any of Rx queues doesn't meet the + * bulk allocation or vector Rx preconditions we will reset it. + */ + ad->rx_bulk_alloc_allowed = true; + ad->tx_simple_allowed = true; - /* configure RSS for gtpu with input set TEID */ - ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_GTP_U_IPV4_TEID, - ICE_FLOW_SEG_HDR_GTPU_IP, 0); - if (ret) - PMD_DRV_LOG(ERR, "%s GTPU_TEID rss flow fail %d", - __func__, ret); + if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) + dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH; - /** - * configure RSS for pppoe/pppod with input set - * Source MAC and Session ID - */ - ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_PPPOE_SESS_ID_ETH, - ICE_FLOW_SEG_HDR_PPPOE, 0); - if (ret) - PMD_DRV_LOG(ERR, "%s PPPoE/PPPoD_SessionID rss flow fail %d", - __func__, ret); + if (dev->data->nb_rx_queues) { + ret = ice_init_rss(pf); + if (ret) { + PMD_DRV_LOG(ERR, "Failed to enable rss for PF"); + return ret; + } + } return 0; } @@ -2597,8 +3305,9 @@ __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect, { struct ice_hw *hw = ICE_VSI_TO_HW(vsi); uint32_t val, val_tx; - int i; + int rx_low_latency, i; + rx_low_latency = vsi->adapter->devargs.rx_low_latency; for (i = 0; i < nb_queue; i++) { /*do actual bind*/ val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) | @@ -2608,8 +3317,21 @@ __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect, PMD_DRV_LOG(INFO, "queue %d is binding to vect %d", base_queue + i, msix_vect); + /* set ITR0 value */ - ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10); + if (rx_low_latency) { + /** + * Empirical configuration for optimal real time + * latency reduced interrupt throttling to 2us + */ + ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x1); + ICE_WRITE_REG(hw, QRX_ITR(base_queue + i), + QRX_ITR_NO_EXPR_M); + } else { + ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x2); + ICE_WRITE_REG(hw, QRX_ITR(base_queue + i), 0); + } + ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val); ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx); } @@ -2618,12 +3340,13 @@ __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect, void ice_vsi_queues_bind_intr(struct ice_vsi *vsi) { - struct rte_eth_dev *dev = vsi->adapter->eth_dev; + struct rte_eth_dev *dev = &rte_eth_devices[vsi->adapter->pf.dev_data->port_id]; struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); - struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; + struct rte_intr_handle *intr_handle = pci_dev->intr_handle; struct ice_hw *hw = ICE_VSI_TO_HW(vsi); uint16_t msix_vect = vsi->msix_intr; - uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd); + uint16_t nb_msix = RTE_MIN(vsi->nb_msix, + rte_intr_nb_efd_get(intr_handle)); uint16_t queue_idx = 0; int record = 0; int i; @@ -2651,8 +3374,9 @@ ice_vsi_queues_bind_intr(struct ice_vsi *vsi) vsi->nb_used_qps - i); for (; !!record && i < vsi->nb_used_qps; i++) - intr_handle->intr_vec[queue_idx + i] = - msix_vect; + rte_intr_vec_list_index_set(intr_handle, + queue_idx + i, msix_vect); + break; } @@ -2661,7 +3385,9 @@ ice_vsi_queues_bind_intr(struct ice_vsi *vsi) vsi->base_queue + i, 1); if (!!record) - intr_handle->intr_vec[queue_idx + i] = msix_vect; + rte_intr_vec_list_index_set(intr_handle, + queue_idx + i, + msix_vect); msix_vect++; nb_msix--; @@ -2671,9 +3397,9 @@ ice_vsi_queues_bind_intr(struct ice_vsi *vsi) void ice_vsi_enable_queues_intr(struct ice_vsi *vsi) { - struct rte_eth_dev *dev = vsi->adapter->eth_dev; + struct rte_eth_dev *dev = &rte_eth_devices[vsi->adapter->pf.dev_data->port_id]; struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); - struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; + struct rte_intr_handle *intr_handle = pci_dev->intr_handle; struct ice_hw *hw = ICE_VSI_TO_HW(vsi); uint16_t msix_intr, i; @@ -2699,7 +3425,7 @@ ice_rxq_intr_setup(struct rte_eth_dev *dev) { struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); - struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; + struct rte_intr_handle *intr_handle = pci_dev->intr_handle; struct ice_vsi *vsi = pf->main_vsi; uint32_t intr_vector = 0; @@ -2719,11 +3445,9 @@ ice_rxq_intr_setup(struct rte_eth_dev *dev) return -1; } - if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { - intr_handle->intr_vec = - rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int), - 0); - if (!intr_handle->intr_vec) { + if (rte_intr_dp_is_en(intr_handle)) { + if (rte_intr_vec_list_alloc(intr_handle, NULL, + dev->data->nb_rx_queues)) { PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues intr_vec", dev->data->nb_rx_queues); @@ -2764,6 +3488,49 @@ ice_get_init_link_status(struct rte_eth_dev *dev) pf->init_link_up = true; } +static int +ice_pps_out_cfg(struct ice_hw *hw, int idx, int timer) +{ + uint64_t current_time, start_time; + uint32_t hi, lo, lo2, func, val; + + lo = ICE_READ_REG(hw, GLTSYN_TIME_L(timer)); + hi = ICE_READ_REG(hw, GLTSYN_TIME_H(timer)); + lo2 = ICE_READ_REG(hw, GLTSYN_TIME_L(timer)); + + if (lo2 < lo) { + lo = ICE_READ_REG(hw, GLTSYN_TIME_L(timer)); + hi = ICE_READ_REG(hw, GLTSYN_TIME_H(timer)); + } + + current_time = ((uint64_t)hi << 32) | lo; + + start_time = (current_time + NSEC_PER_SEC) / + NSEC_PER_SEC * NSEC_PER_SEC; + start_time = start_time - PPS_OUT_DELAY_NS; + + func = 8 + idx + timer * 4; + val = GLGEN_GPIO_CTL_PIN_DIR_M | + ((func << GLGEN_GPIO_CTL_PIN_FUNC_S) & + GLGEN_GPIO_CTL_PIN_FUNC_M); + + /* Write clkout with half of period value */ + ICE_WRITE_REG(hw, GLTSYN_CLKO(idx, timer), NSEC_PER_SEC / 2); + + /* Write TARGET time register */ + ICE_WRITE_REG(hw, GLTSYN_TGT_L(idx, timer), start_time & 0xffffffff); + ICE_WRITE_REG(hw, GLTSYN_TGT_H(idx, timer), start_time >> 32); + + /* Write AUX_OUT register */ + ICE_WRITE_REG(hw, GLTSYN_AUX_OUT(idx, timer), + GLTSYN_AUX_OUT_0_OUT_ENA_M | GLTSYN_AUX_OUT_0_OUTMOD_M); + + /* Write GPIO CTL register */ + ICE_WRITE_REG(hw, GLGEN_GPIO_CTL(idx), val); + + return 0; +} + static int ice_dev_start(struct rte_eth_dev *dev) { @@ -2771,10 +3538,14 @@ ice_dev_start(struct rte_eth_dev *dev) struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); struct ice_vsi *vsi = pf->main_vsi; + struct ice_adapter *ad = + ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); uint16_t nb_rxq = 0; uint16_t nb_txq, i; uint16_t max_frame_size; int mask, ret; + uint8_t timer = hw->func_caps.ts_func_info.tmr_index_owned; + uint32_t pin_idx = ad->devargs.pin_idx; /* program Tx queues' context in hardware */ for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) { @@ -2794,24 +3565,18 @@ ice_dev_start(struct rte_eth_dev *dev) } } - ret = ice_init_rss(pf); - if (ret) { - PMD_DRV_LOG(ERR, "Failed to enable rss for PF"); - goto rx_err; - } - ice_set_rx_function(dev); ice_set_tx_function(dev); - mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | - ETH_VLAN_EXTEND_MASK; + mask = RTE_ETH_VLAN_STRIP_MASK | RTE_ETH_VLAN_FILTER_MASK | + RTE_ETH_VLAN_EXTEND_MASK; ret = ice_vlan_offload_set(dev, mask); if (ret) { PMD_INIT_LOG(ERR, "Unable to set VLAN offload"); goto rx_err; } - /* enable Rx interrput and mapping Rx queue to interrupt vector */ + /* enable Rx interrupt and mapping Rx queue to interrupt vector */ if (ice_rxq_intr_setup(dev)) return -EIO; @@ -2838,19 +3603,27 @@ ice_dev_start(struct rte_eth_dev *dev) ice_dev_set_link_up(dev); - /* Call get_link_info aq commond to enable/disable LSE */ + /* Call get_link_info aq command to enable/disable LSE */ ice_link_update(dev, 0); pf->adapter_stopped = false; /* Set the max frame size to default value*/ - max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ? - pf->dev_data->dev_conf.rxmode.max_rx_pkt_len : + max_frame_size = pf->dev_data->mtu ? + pf->dev_data->mtu + ICE_ETH_OVERHEAD : ICE_FRAME_SIZE_MAX; /* Set the max frame size to HW*/ ice_aq_set_mac_cfg(hw, max_frame_size, NULL); + if (ad->devargs.pps_out_ena) { + ret = ice_pps_out_cfg(hw, pin_idx, timer); + if (ret) { + PMD_DRV_LOG(ERR, "Fail to configure 1pps out"); + goto rx_err; + } + } + return 0; /* stop the started queues if failed to start all queues */ @@ -2908,40 +3681,40 @@ ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) dev_info->min_mtu = RTE_ETHER_MIN_MTU; dev_info->rx_offload_capa = - DEV_RX_OFFLOAD_VLAN_STRIP | - DEV_RX_OFFLOAD_JUMBO_FRAME | - DEV_RX_OFFLOAD_KEEP_CRC | - DEV_RX_OFFLOAD_SCATTER | - DEV_RX_OFFLOAD_VLAN_FILTER; + RTE_ETH_RX_OFFLOAD_VLAN_STRIP | + RTE_ETH_RX_OFFLOAD_KEEP_CRC | + RTE_ETH_RX_OFFLOAD_SCATTER | + RTE_ETH_RX_OFFLOAD_VLAN_FILTER; dev_info->tx_offload_capa = - DEV_TX_OFFLOAD_VLAN_INSERT | - DEV_TX_OFFLOAD_TCP_TSO | - DEV_TX_OFFLOAD_MULTI_SEGS | - DEV_TX_OFFLOAD_MBUF_FAST_FREE; + RTE_ETH_TX_OFFLOAD_VLAN_INSERT | + RTE_ETH_TX_OFFLOAD_TCP_TSO | + RTE_ETH_TX_OFFLOAD_MULTI_SEGS | + RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE; dev_info->flow_type_rss_offloads = 0; if (!is_safe_mode) { dev_info->rx_offload_capa |= - DEV_RX_OFFLOAD_IPV4_CKSUM | - DEV_RX_OFFLOAD_UDP_CKSUM | - DEV_RX_OFFLOAD_TCP_CKSUM | - DEV_RX_OFFLOAD_QINQ_STRIP | - DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | - DEV_RX_OFFLOAD_VLAN_EXTEND | - DEV_RX_OFFLOAD_RSS_HASH; + RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | + RTE_ETH_RX_OFFLOAD_UDP_CKSUM | + RTE_ETH_RX_OFFLOAD_TCP_CKSUM | + RTE_ETH_RX_OFFLOAD_QINQ_STRIP | + RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM | + RTE_ETH_RX_OFFLOAD_VLAN_EXTEND | + RTE_ETH_RX_OFFLOAD_RSS_HASH | + RTE_ETH_RX_OFFLOAD_TIMESTAMP; dev_info->tx_offload_capa |= - DEV_TX_OFFLOAD_QINQ_INSERT | - DEV_TX_OFFLOAD_IPV4_CKSUM | - DEV_TX_OFFLOAD_UDP_CKSUM | - DEV_TX_OFFLOAD_TCP_CKSUM | - DEV_TX_OFFLOAD_SCTP_CKSUM | - DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | - DEV_TX_OFFLOAD_OUTER_UDP_CKSUM; + RTE_ETH_TX_OFFLOAD_QINQ_INSERT | + RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | + RTE_ETH_TX_OFFLOAD_UDP_CKSUM | + RTE_ETH_TX_OFFLOAD_TCP_CKSUM | + RTE_ETH_TX_OFFLOAD_SCTP_CKSUM | + RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | + RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM; dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL; } dev_info->rx_queue_offload_capa = 0; - dev_info->tx_queue_offload_capa = 0; + dev_info->tx_queue_offload_capa = RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE; dev_info->reta_size = pf->hash_lut_size; dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t); @@ -2980,24 +3753,24 @@ ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) .nb_align = ICE_ALIGN_RING_DESC, }; - dev_info->speed_capa = ETH_LINK_SPEED_10M | - ETH_LINK_SPEED_100M | - ETH_LINK_SPEED_1G | - ETH_LINK_SPEED_2_5G | - ETH_LINK_SPEED_5G | - ETH_LINK_SPEED_10G | - ETH_LINK_SPEED_20G | - ETH_LINK_SPEED_25G; + dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M | + RTE_ETH_LINK_SPEED_100M | + RTE_ETH_LINK_SPEED_1G | + RTE_ETH_LINK_SPEED_2_5G | + RTE_ETH_LINK_SPEED_5G | + RTE_ETH_LINK_SPEED_10G | + RTE_ETH_LINK_SPEED_20G | + RTE_ETH_LINK_SPEED_25G; phy_type_low = hw->port_info->phy.phy_type_low; phy_type_high = hw->port_info->phy.phy_type_high; if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low)) - dev_info->speed_capa |= ETH_LINK_SPEED_50G; + dev_info->speed_capa |= RTE_ETH_LINK_SPEED_50G; if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) || ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high)) - dev_info->speed_capa |= ETH_LINK_SPEED_100G; + dev_info->speed_capa |= RTE_ETH_LINK_SPEED_100G; dev_info->nb_rx_queues = dev->data->nb_rx_queues; dev_info->nb_tx_queues = dev->data->nb_tx_queues; @@ -3062,8 +3835,8 @@ ice_link_update(struct rte_eth_dev *dev, int wait_to_complete) status = ice_aq_get_link_info(hw->port_info, enable_lse, &link_status, NULL); if (status != ICE_SUCCESS) { - link.link_speed = ETH_SPEED_NUM_100M; - link.link_duplex = ETH_LINK_FULL_DUPLEX; + link.link_speed = RTE_ETH_SPEED_NUM_100M; + link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX; PMD_DRV_LOG(ERR, "Failed to get link info"); goto out; } @@ -3079,52 +3852,55 @@ ice_link_update(struct rte_eth_dev *dev, int wait_to_complete) goto out; /* Full-duplex operation at all supported speeds */ - link.link_duplex = ETH_LINK_FULL_DUPLEX; + link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX; /* Parse the link status */ switch (link_status.link_speed) { case ICE_AQ_LINK_SPEED_10MB: - link.link_speed = ETH_SPEED_NUM_10M; + link.link_speed = RTE_ETH_SPEED_NUM_10M; break; case ICE_AQ_LINK_SPEED_100MB: - link.link_speed = ETH_SPEED_NUM_100M; + link.link_speed = RTE_ETH_SPEED_NUM_100M; break; case ICE_AQ_LINK_SPEED_1000MB: - link.link_speed = ETH_SPEED_NUM_1G; + link.link_speed = RTE_ETH_SPEED_NUM_1G; break; case ICE_AQ_LINK_SPEED_2500MB: - link.link_speed = ETH_SPEED_NUM_2_5G; + link.link_speed = RTE_ETH_SPEED_NUM_2_5G; break; case ICE_AQ_LINK_SPEED_5GB: - link.link_speed = ETH_SPEED_NUM_5G; + link.link_speed = RTE_ETH_SPEED_NUM_5G; break; case ICE_AQ_LINK_SPEED_10GB: - link.link_speed = ETH_SPEED_NUM_10G; + link.link_speed = RTE_ETH_SPEED_NUM_10G; break; case ICE_AQ_LINK_SPEED_20GB: - link.link_speed = ETH_SPEED_NUM_20G; + link.link_speed = RTE_ETH_SPEED_NUM_20G; break; case ICE_AQ_LINK_SPEED_25GB: - link.link_speed = ETH_SPEED_NUM_25G; + link.link_speed = RTE_ETH_SPEED_NUM_25G; break; case ICE_AQ_LINK_SPEED_40GB: - link.link_speed = ETH_SPEED_NUM_40G; + link.link_speed = RTE_ETH_SPEED_NUM_40G; break; case ICE_AQ_LINK_SPEED_50GB: - link.link_speed = ETH_SPEED_NUM_50G; + link.link_speed = RTE_ETH_SPEED_NUM_50G; break; case ICE_AQ_LINK_SPEED_100GB: - link.link_speed = ETH_SPEED_NUM_100G; + link.link_speed = RTE_ETH_SPEED_NUM_100G; break; case ICE_AQ_LINK_SPEED_UNKNOWN: - default: PMD_DRV_LOG(ERR, "Unknown link speed"); - link.link_speed = ETH_SPEED_NUM_NONE; + link.link_speed = RTE_ETH_SPEED_NUM_UNKNOWN; + break; + default: + PMD_DRV_LOG(ERR, "None link speed"); + link.link_speed = RTE_ETH_SPEED_NUM_NONE; break; } link.link_autoneg = !(dev->data->dev_conf.link_speeds & - ETH_LINK_SPEED_FIXED); + RTE_ETH_LINK_SPEED_FIXED); out: ice_atomic_write_link_status(dev, &link); @@ -3157,8 +3933,8 @@ ice_force_phys_link_state(struct ice_hw *hw, bool link_up) if (!pcaps) return ICE_ERR_NO_MEMORY; - status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps, - NULL); + status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, + pcaps, NULL); if (status) goto out; @@ -3203,33 +3979,16 @@ ice_dev_set_link_down(struct rte_eth_dev *dev) } static int -ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) +ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu __rte_unused) { - struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); - struct rte_eth_dev_data *dev_data = pf->dev_data; - uint32_t frame_size = mtu + ICE_ETH_OVERHEAD; - - /* check if mtu is within the allowed range */ - if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX) - return -EINVAL; - /* mtu setting is forbidden if port is start */ - if (dev_data->dev_started) { + if (dev->data->dev_started != 0) { PMD_DRV_LOG(ERR, "port %d must be stopped before configuration", - dev_data->port_id); + dev->data->port_id); return -EBUSY; } - if (frame_size > RTE_ETHER_MAX_LEN) - dev_data->dev_conf.rxmode.offloads |= - DEV_RX_OFFLOAD_JUMBO_FRAME; - else - dev_data->dev_conf.rxmode.offloads &= - ~DEV_RX_OFFLOAD_JUMBO_FRAME; - - dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size; - return 0; } @@ -3317,26 +4076,105 @@ ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index) } static int -ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) +ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) +{ + struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); + struct ice_vlan vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, vlan_id); + struct ice_vsi *vsi = pf->main_vsi; + int ret; + + PMD_INIT_FUNC_TRACE(); + + /** + * Vlan 0 is the generic filter for untagged packets + * and can't be removed or added by user. + */ + if (vlan_id == 0) + return 0; + + if (on) { + ret = ice_add_vlan_filter(vsi, &vlan); + if (ret < 0) { + PMD_DRV_LOG(ERR, "Failed to add vlan filter"); + return -EINVAL; + } + } else { + ret = ice_remove_vlan_filter(vsi, &vlan); + if (ret < 0) { + PMD_DRV_LOG(ERR, "Failed to remove vlan filter"); + return -EINVAL; + } + } + + return 0; +} + +/* In Single VLAN Mode (SVM), single VLAN filters via ICE_SW_LKUP_VLAN are + * based on the inner VLAN ID, so the VLAN TPID (i.e. 0x8100 or 0x888a8) + * doesn't matter. In Double VLAN Mode (DVM), outer/single VLAN filters via + * ICE_SW_LKUP_VLAN are based on the outer/single VLAN ID + VLAN TPID. + * + * For both modes add a VLAN 0 + no VLAN TPID filter to handle untagged traffic + * when VLAN pruning is enabled. Also, this handles VLAN 0 priority tagged + * traffic in SVM, since the VLAN TPID isn't part of filtering. + * + * If DVM is enabled then an explicit VLAN 0 + VLAN TPID filter needs to be + * added to allow VLAN 0 priority tagged traffic in DVM, since the VLAN TPID is + * part of filtering. + */ +static int +ice_vsi_add_vlan_zero(struct ice_vsi *vsi) +{ + struct ice_vlan vlan; + int err; + + vlan = ICE_VLAN(0, 0); + err = ice_add_vlan_filter(vsi, &vlan); + if (err) { + PMD_DRV_LOG(DEBUG, "Failed to add VLAN ID 0"); + return err; + } + + /* in SVM both VLAN 0 filters are identical */ + if (!ice_is_dvm_ena(&vsi->adapter->hw)) + return 0; + + vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, 0); + err = ice_add_vlan_filter(vsi, &vlan); + if (err) { + PMD_DRV_LOG(DEBUG, "Failed to add VLAN ID 0 in double VLAN mode"); + return err; + } + + return 0; +} + +/* + * Delete the VLAN 0 filters in the same manner that they were added in + * ice_vsi_add_vlan_zero. + */ +static int +ice_vsi_del_vlan_zero(struct ice_vsi *vsi) { - struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); - struct ice_vsi *vsi = pf->main_vsi; - int ret; + struct ice_vlan vlan; + int err; - PMD_INIT_FUNC_TRACE(); + vlan = ICE_VLAN(0, 0); + err = ice_remove_vlan_filter(vsi, &vlan); + if (err) { + PMD_DRV_LOG(DEBUG, "Failed to remove VLAN ID 0"); + return err; + } - if (on) { - ret = ice_add_vlan_filter(vsi, vlan_id); - if (ret < 0) { - PMD_DRV_LOG(ERR, "Failed to add vlan filter"); - return -EINVAL; - } - } else { - ret = ice_remove_vlan_filter(vsi, vlan_id); - if (ret < 0) { - PMD_DRV_LOG(ERR, "Failed to remove vlan filter"); - return -EINVAL; - } + /* in SVM both VLAN 0 filters are identical */ + if (!ice_is_dvm_ena(&vsi->adapter->hw)) + return 0; + + vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, 0); + err = ice_remove_vlan_filter(vsi, &vlan); + if (err) { + PMD_DRV_LOG(DEBUG, "Failed to remove VLAN ID 0 in double VLAN mode"); + return err; } return 0; @@ -3348,20 +4186,16 @@ ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on) { struct ice_hw *hw = ICE_VSI_TO_HW(vsi); struct ice_vsi_ctx ctxt; - uint8_t sec_flags, sw_flags2; + uint8_t sw_flags2; int ret = 0; - sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA << - ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S; sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA; - if (on) { - vsi->info.sec_flags |= sec_flags; + if (on) vsi->info.sw_flags2 |= sw_flags2; - } else { - vsi->info.sec_flags &= ~sec_flags; + else vsi->info.sw_flags2 &= ~sw_flags2; - } + vsi->info.sw_id = hw->port_info->sw_id; (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); ctxt.info.valid_sections = @@ -3382,56 +4216,154 @@ ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on) /* consist with other drivers, allow untagged packet when vlan filter on */ if (on) - ret = ice_add_vlan_filter(vsi, 0); + ret = ice_vsi_add_vlan_zero(vsi); else - ret = ice_remove_vlan_filter(vsi, 0); + ret = ice_vsi_del_vlan_zero(vsi); return 0; } +/* Manage VLAN stripping for the VSI for Rx */ static int -ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on) +ice_vsi_manage_vlan_stripping(struct ice_vsi *vsi, bool ena) { struct ice_hw *hw = ICE_VSI_TO_HW(vsi); struct ice_vsi_ctx ctxt; - uint8_t vlan_flags; - int ret = 0; + enum ice_status status; + int err = 0; - /* Check if it has been already on or off */ - if (vsi->info.valid_sections & - rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) { - if (on) { - if ((vsi->info.vlan_flags & - ICE_AQ_VSI_VLAN_EMOD_M) == - ICE_AQ_VSI_VLAN_EMOD_STR_BOTH) - return 0; /* already on */ - } else { - if ((vsi->info.vlan_flags & - ICE_AQ_VSI_VLAN_EMOD_M) == - ICE_AQ_VSI_VLAN_EMOD_NOTHING) - return 0; /* already off */ - } - } + /* do not allow modifying VLAN stripping when a port VLAN is configured + * on this VSI + */ + if (vsi->info.port_based_inner_vlan) + return 0; - if (on) - vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH; + memset(&ctxt, 0, sizeof(ctxt)); + + if (ena) + /* Strip VLAN tag from Rx packet and put it in the desc */ + ctxt.info.inner_vlan_flags = + ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH; else - vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING; - vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M); - vsi->info.vlan_flags |= vlan_flags; - (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); + /* Disable stripping. Leave tag in packet */ + ctxt.info.inner_vlan_flags = + ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING; + + /* Allow all packets untagged/tagged */ + ctxt.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL; + + ctxt.info.valid_sections = rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); + + status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); + if (status) { + PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan stripping", + ena ? "enable" : "disable"); + err = -EIO; + } else { + vsi->info.inner_vlan_flags = ctxt.info.inner_vlan_flags; + } + + return err; +} + +static int +ice_vsi_ena_inner_stripping(struct ice_vsi *vsi) +{ + return ice_vsi_manage_vlan_stripping(vsi, true); +} + +static int +ice_vsi_dis_inner_stripping(struct ice_vsi *vsi) +{ + return ice_vsi_manage_vlan_stripping(vsi, false); +} + +static int ice_vsi_ena_outer_stripping(struct ice_vsi *vsi) +{ + struct ice_hw *hw = ICE_VSI_TO_HW(vsi); + struct ice_vsi_ctx ctxt; + enum ice_status status; + int err = 0; + + /* do not allow modifying VLAN stripping when a port VLAN is configured + * on this VSI + */ + if (vsi->info.port_based_outer_vlan) + return 0; + + memset(&ctxt, 0, sizeof(ctxt)); + ctxt.info.valid_sections = - rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); - ctxt.vsi_num = vsi->vsi_id; - ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); - if (ret) { - PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping", - on ? "enable" : "disable"); - return -EINVAL; + rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); + /* clear current outer VLAN strip settings */ + ctxt.info.outer_vlan_flags = vsi->info.outer_vlan_flags & + ~(ICE_AQ_VSI_OUTER_VLAN_EMODE_M | ICE_AQ_VSI_OUTER_TAG_TYPE_M); + ctxt.info.outer_vlan_flags |= + (ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH << + ICE_AQ_VSI_OUTER_VLAN_EMODE_S) | + (ICE_AQ_VSI_OUTER_TAG_VLAN_8100 << + ICE_AQ_VSI_OUTER_TAG_TYPE_S); + + status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); + if (status) { + PMD_DRV_LOG(ERR, "Update VSI failed to enable outer VLAN stripping"); + err = -EIO; + } else { + vsi->info.outer_vlan_flags = ctxt.info.outer_vlan_flags; } - vsi->info.valid_sections |= - rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); + return err; +} + +static int +ice_vsi_dis_outer_stripping(struct ice_vsi *vsi) +{ + struct ice_hw *hw = ICE_VSI_TO_HW(vsi); + struct ice_vsi_ctx ctxt; + enum ice_status status; + int err = 0; + + if (vsi->info.port_based_outer_vlan) + return 0; + + memset(&ctxt, 0, sizeof(ctxt)); + + ctxt.info.valid_sections = + rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); + /* clear current outer VLAN strip settings */ + ctxt.info.outer_vlan_flags = vsi->info.outer_vlan_flags & + ~ICE_AQ_VSI_OUTER_VLAN_EMODE_M; + ctxt.info.outer_vlan_flags |= ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING << + ICE_AQ_VSI_OUTER_VLAN_EMODE_S; + + status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); + if (status) { + PMD_DRV_LOG(ERR, "Update VSI failed to disable outer VLAN stripping"); + err = -EIO; + } else { + vsi->info.outer_vlan_flags = ctxt.info.outer_vlan_flags; + } + + return err; +} + +static int +ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool ena) +{ + struct ice_hw *hw = ICE_VSI_TO_HW(vsi); + int ret; + + if (ice_is_dvm_ena(hw)) { + if (ena) + ret = ice_vsi_ena_outer_stripping(vsi); + else + ret = ice_vsi_dis_outer_stripping(vsi); + } else { + if (ena) + ret = ice_vsi_ena_inner_stripping(vsi); + else + ret = ice_vsi_dis_inner_stripping(vsi); + } return ret; } @@ -3444,33 +4376,27 @@ ice_vlan_offload_set(struct rte_eth_dev *dev, int mask) struct rte_eth_rxmode *rxmode; rxmode = &dev->data->dev_conf.rxmode; - if (mask & ETH_VLAN_FILTER_MASK) { - if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) + if (mask & RTE_ETH_VLAN_FILTER_MASK) { + if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) ice_vsi_config_vlan_filter(vsi, true); else ice_vsi_config_vlan_filter(vsi, false); } - if (mask & ETH_VLAN_STRIP_MASK) { - if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) + if (mask & RTE_ETH_VLAN_STRIP_MASK) { + if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) ice_vsi_config_vlan_stripping(vsi, true); else ice_vsi_config_vlan_stripping(vsi, false); } - if (mask & ETH_VLAN_EXTEND_MASK) { - if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) - ice_vsi_config_double_vlan(vsi, true); - else - ice_vsi_config_double_vlan(vsi, false); - } - return 0; } static int ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size) { + struct ice_aq_get_set_rss_lut_params lut_params; struct ice_pf *pf = ICE_VSI_TO_PF(vsi); struct ice_hw *hw = ICE_VSI_TO_HW(vsi); int ret; @@ -3479,8 +4405,12 @@ ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size) return -EINVAL; if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) { - ret = ice_aq_get_rss_lut(hw, vsi->idx, - ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size); + lut_params.vsi_handle = vsi->idx; + lut_params.lut_size = lut_size; + lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF; + lut_params.lut = lut; + lut_params.global_lut_id = 0; + ret = ice_aq_get_rss_lut(hw, &lut_params); if (ret) { PMD_DRV_LOG(ERR, "Failed to get RSS lookup table"); return -EINVAL; @@ -3499,6 +4429,7 @@ ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size) static int ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size) { + struct ice_aq_get_set_rss_lut_params lut_params; struct ice_pf *pf; struct ice_hw *hw; int ret; @@ -3510,8 +4441,12 @@ ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size) hw = ICE_VSI_TO_HW(vsi); if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) { - ret = ice_aq_set_rss_lut(hw, vsi->idx, - ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size); + lut_params.vsi_handle = vsi->idx; + lut_params.lut_size = lut_size; + lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF; + lut_params.lut = lut; + lut_params.global_lut_id = 0; + ret = ice_aq_set_rss_lut(hw, &lut_params); if (ret) { PMD_DRV_LOG(ERR, "Failed to set RSS lookup table"); return -EINVAL; @@ -3564,8 +4499,8 @@ ice_rss_reta_update(struct rte_eth_dev *dev, goto out; for (i = 0; i < reta_size; i++) { - idx = i / RTE_RETA_GROUP_SIZE; - shift = i % RTE_RETA_GROUP_SIZE; + idx = i / RTE_ETH_RETA_GROUP_SIZE; + shift = i % RTE_ETH_RETA_GROUP_SIZE; if (reta_conf[idx].mask & (1ULL << shift)) lut[i] = reta_conf[idx].reta[shift]; } @@ -3614,8 +4549,8 @@ ice_rss_reta_query(struct rte_eth_dev *dev, goto out; for (i = 0; i < reta_size; i++) { - idx = i / RTE_RETA_GROUP_SIZE; - shift = i % RTE_RETA_GROUP_SIZE; + idx = i / RTE_ETH_RETA_GROUP_SIZE; + shift = i % RTE_ETH_RETA_GROUP_SIZE; if (reta_conf[idx].mask & (1ULL << shift)) reta_conf[idx].reta[shift] = lut[i]; } @@ -3687,7 +4622,14 @@ ice_rss_hash_update(struct rte_eth_dev *dev, if (status) return status; - /* TODO: hash enable config, ice_add_rss_cfg */ + if (rss_conf->rss_hf == 0) { + pf->rss_hf = 0; + return 0; + } + + /* RSS hash configuration */ + ice_rss_hash_set(pf, rss_conf->rss_hf); + return 0; } @@ -3701,8 +4643,7 @@ ice_rss_hash_conf_get(struct rte_eth_dev *dev, ice_get_rss_key(vsi, rss_conf->rss_key, &rss_conf->rss_key_len); - /* TODO: default set to 0 as hf config is not supported now */ - rss_conf->rss_hf = 0; + rss_conf->rss_hf = pf->rss_hf; return 0; } @@ -3743,8 +4684,11 @@ ice_promisc_disable(struct rte_eth_dev *dev) uint8_t pmask; int ret = 0; - pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX | - ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; + if (dev->data->all_multicast == 1) + pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX; + else + pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX | + ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0); if (status != ICE_SUCCESS) { @@ -3810,19 +4754,19 @@ static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) { struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); - struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; + struct rte_intr_handle *intr_handle = pci_dev->intr_handle; struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); uint32_t val; uint16_t msix_intr; - msix_intr = intr_handle->intr_vec[queue_id]; + msix_intr = rte_intr_vec_list_index_get(intr_handle, queue_id); val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M | GLINT_DYN_CTL_ITR_INDX_M; val &= ~GLINT_DYN_CTL_WB_ON_ITR_M; ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val); - rte_intr_ack(&pci_dev->intr_handle); + rte_intr_ack(pci_dev->intr_handle); return 0; } @@ -3831,11 +4775,11 @@ static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) { struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); - struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; + struct rte_intr_handle *intr_handle = pci_dev->intr_handle; struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); uint16_t msix_intr; - msix_intr = intr_handle->intr_vec[queue_id]; + msix_intr = rte_intr_vec_list_index_get(intr_handle, queue_id); ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M); @@ -3850,20 +4794,22 @@ ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) u16 build; int ret; - ver = hw->nvm.orom.major; - patch = hw->nvm.orom.patch; - build = hw->nvm.orom.build; + ver = hw->flash.orom.major; + patch = hw->flash.orom.patch; + build = hw->flash.orom.build; ret = snprintf(fw_version, fw_size, - "%d.%d 0x%08x %d.%d.%d", - hw->nvm.major_ver, - hw->nvm.minor_ver, - hw->nvm.eetrack, + "%x.%02x 0x%08x %d.%d.%d", + hw->flash.nvm.major, + hw->flash.nvm.minor, + hw->flash.nvm.eetrack, ver, build, patch); + if (ret < 0) + return -EINVAL; /* add the size of '\0' */ ret += 1; - if (fw_size < (u32)ret) + if (fw_size < (size_t)ret) return ret; else return 0; @@ -3883,24 +4829,24 @@ ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info) } if (info->on) { - vsi->info.pvid = info->config.pvid; + vsi->info.port_based_inner_vlan = info->config.pvid; /** * If insert pvid is enabled, only tagged pkts are * allowed to be sent out. */ - vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID | - ICE_AQ_VSI_VLAN_MODE_UNTAGGED; + vlan_flags = ICE_AQ_VSI_INNER_VLAN_INSERT_PVID | + ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED; } else { - vsi->info.pvid = 0; + vsi->info.port_based_inner_vlan = 0; if (info->config.reject.tagged == 0) - vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED; + vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED; if (info->config.reject.untagged == 0) - vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED; + vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED; } - vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID | - ICE_AQ_VSI_VLAN_MODE_M); - vsi->info.vlan_flags |= vlan_flags; + vsi->info.inner_vlan_flags &= ~(ICE_AQ_VSI_INNER_VLAN_INSERT_PVID | + ICE_AQ_VSI_INNER_VLAN_EMODE_M); + vsi->info.inner_vlan_flags |= vlan_flags; memset(&ctxt, 0, sizeof(ctxt)); rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); ctxt.info.valid_sections = @@ -3956,8 +4902,7 @@ ice_get_eeprom_length(struct rte_eth_dev *dev) { struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); - /* Convert word count to byte count */ - return hw->nvm.sr_words << 1; + return hw->flash.flash_size; } static int @@ -3965,26 +4910,24 @@ ice_get_eeprom(struct rte_eth_dev *dev, struct rte_dev_eeprom_info *eeprom) { struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); - uint16_t *data = eeprom->data; - uint16_t first_word, last_word, nwords; enum ice_status status = ICE_SUCCESS; + uint8_t *data = eeprom->data; - first_word = eeprom->offset >> 1; - last_word = (eeprom->offset + eeprom->length - 1) >> 1; - nwords = last_word - first_word + 1; + eeprom->magic = hw->vendor_id | (hw->device_id << 16); - if (first_word >= hw->nvm.sr_words || - last_word >= hw->nvm.sr_words) { - PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range."); - return -EINVAL; + status = ice_acquire_nvm(hw, ICE_RES_READ); + if (status) { + PMD_DRV_LOG(ERR, "acquire nvm failed."); + return -EIO; } - eeprom->magic = hw->vendor_id | (hw->device_id << 16); + status = ice_read_flat_nvm(hw, eeprom->offset, &eeprom->length, + data, false); + + ice_release_nvm(hw); - status = ice_read_sr_buf(hw, first_word, &nwords, data); if (status) { PMD_DRV_LOG(ERR, "EEPROM read failed."); - eeprom->length = sizeof(uint16_t) * nwords; return -EIO; } @@ -4060,6 +5003,13 @@ ice_update_vsi_stats(struct ice_vsi *vsi) ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx), vsi->offset_loaded, &oes->rx_broadcast, &nes->rx_broadcast); + /* enlarge the limitation when rx_bytes overflowed */ + if (vsi->offset_loaded) { + if (ICE_RXTX_BYTES_LOW(vsi->old_rx_bytes) > nes->rx_bytes) + nes->rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH; + nes->rx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_rx_bytes); + } + vsi->old_rx_bytes = nes->rx_bytes; /* exclude CRC bytes */ nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast + nes->rx_broadcast) * RTE_ETHER_CRC_LEN; @@ -4086,6 +5036,13 @@ ice_update_vsi_stats(struct ice_vsi *vsi) /* GLV_TDPC not supported */ ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded, &oes->tx_errors, &nes->tx_errors); + /* enlarge the limitation when tx_bytes overflowed */ + if (vsi->offset_loaded) { + if (ICE_RXTX_BYTES_LOW(vsi->old_tx_bytes) > nes->tx_bytes) + nes->tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH; + nes->tx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_tx_bytes); + } + vsi->old_tx_bytes = nes->tx_bytes; vsi->offset_loaded = true; PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************", @@ -4133,6 +5090,13 @@ ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw) ice_stat_update_32(hw, PRTRPB_RDPC, pf->offset_loaded, &os->eth.rx_discards, &ns->eth.rx_discards); + /* enlarge the limitation when rx_bytes overflowed */ + if (pf->offset_loaded) { + if (ICE_RXTX_BYTES_LOW(pf->old_rx_bytes) > ns->eth.rx_bytes) + ns->eth.rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH; + ns->eth.rx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_rx_bytes); + } + pf->old_rx_bytes = ns->eth.rx_bytes; /* Workaround: CRC size should not be included in byte statistics, * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx @@ -4163,6 +5127,13 @@ ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw) GLPRT_BPTCL(hw->port_info->lport), pf->offset_loaded, &os->eth.tx_broadcast, &ns->eth.tx_broadcast); + /* enlarge the limitation when tx_bytes overflowed */ + if (pf->offset_loaded) { + if (ICE_RXTX_BYTES_LOW(pf->old_tx_bytes) > ns->eth.tx_bytes) + ns->eth.tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH; + ns->eth.tx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_tx_bytes); + } + pf->old_tx_bytes = ns->eth.tx_bytes; ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast + ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN; @@ -4424,7 +5395,7 @@ ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, count++; } - /* Get individiual stats from ice_hw_port struct */ + /* Get individual stats from ice_hw_port struct */ for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) { xstats[count].value = *(uint64_t *)((char *)hw_stats + @@ -4455,7 +5426,7 @@ static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev, count++; } - /* Get individiual stats from ice_hw_port struct */ + /* Get individual stats from ice_hw_port struct */ for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) { strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name, sizeof(xstats_names[count].name)); @@ -4466,30 +5437,14 @@ static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev, } static int -ice_dev_filter_ctrl(struct rte_eth_dev *dev, - enum rte_filter_type filter_type, - enum rte_filter_op filter_op, - void *arg) +ice_dev_flow_ops_get(struct rte_eth_dev *dev, + const struct rte_flow_ops **ops) { - int ret = 0; - if (!dev) return -EINVAL; - switch (filter_type) { - case RTE_ETH_FILTER_GENERIC: - if (filter_op != RTE_ETH_FILTER_GET) - return -EINVAL; - *(const void **)arg = &ice_flow_ops; - break; - default: - PMD_DRV_LOG(WARNING, "Filter type (%d) not supported", - filter_type); - ret = -EINVAL; - break; - } - - return ret; + *ops = &ice_flow_ops; + return 0; } /* Add UDP tunneling port */ @@ -4504,7 +5459,7 @@ ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, return -EINVAL; switch (udp_tunnel->prot_type) { - case RTE_TUNNEL_TYPE_VXLAN: + case RTE_ETH_TUNNEL_TYPE_VXLAN: ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port); break; default: @@ -4528,7 +5483,7 @@ ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, return -EINVAL; switch (udp_tunnel->prot_type) { - case RTE_TUNNEL_TYPE_VXLAN: + case RTE_ETH_TUNNEL_TYPE_VXLAN: ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0); break; default: @@ -4540,6 +5495,184 @@ ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, return ret; } +static int +ice_timesync_enable(struct rte_eth_dev *dev) +{ + struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct ice_adapter *ad = + ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); + int ret; + + if (dev->data->dev_started && !(dev->data->dev_conf.rxmode.offloads & + RTE_ETH_RX_OFFLOAD_TIMESTAMP)) { + PMD_DRV_LOG(ERR, "Rx timestamp offload not configured"); + return -1; + } + + if (hw->func_caps.ts_func_info.src_tmr_owned) { + ret = ice_ptp_init_phc(hw); + if (ret) { + PMD_DRV_LOG(ERR, "Failed to initialize PHC"); + return -1; + } + + ret = ice_ptp_write_incval(hw, ICE_PTP_NOMINAL_INCVAL_E810); + if (ret) { + PMD_DRV_LOG(ERR, + "Failed to write PHC increment time value"); + return -1; + } + } + + /* Initialize cycle counters for system time/RX/TX timestamp */ + memset(&ad->systime_tc, 0, sizeof(struct rte_timecounter)); + memset(&ad->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); + memset(&ad->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); + + ad->systime_tc.cc_mask = ICE_CYCLECOUNTER_MASK; + ad->systime_tc.cc_shift = 0; + ad->systime_tc.nsec_mask = 0; + + ad->rx_tstamp_tc.cc_mask = ICE_CYCLECOUNTER_MASK; + ad->rx_tstamp_tc.cc_shift = 0; + ad->rx_tstamp_tc.nsec_mask = 0; + + ad->tx_tstamp_tc.cc_mask = ICE_CYCLECOUNTER_MASK; + ad->tx_tstamp_tc.cc_shift = 0; + ad->tx_tstamp_tc.nsec_mask = 0; + + ad->ptp_ena = 1; + + return 0; +} + +static int +ice_timesync_read_rx_timestamp(struct rte_eth_dev *dev, + struct timespec *timestamp, uint32_t flags) +{ + struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct ice_adapter *ad = + ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); + struct ice_rx_queue *rxq; + uint32_t ts_high; + uint64_t ts_ns, ns; + + rxq = dev->data->rx_queues[flags]; + + ts_high = rxq->time_high; + ts_ns = ice_tstamp_convert_32b_64b(hw, ad, 1, ts_high); + ns = rte_timecounter_update(&ad->rx_tstamp_tc, ts_ns); + *timestamp = rte_ns_to_timespec(ns); + + return 0; +} + +static int +ice_timesync_read_tx_timestamp(struct rte_eth_dev *dev, + struct timespec *timestamp) +{ + struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct ice_adapter *ad = + ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); + uint8_t lport; + uint64_t ts_ns, ns, tstamp; + const uint64_t mask = 0xFFFFFFFF; + int ret; + + lport = hw->port_info->lport; + + ret = ice_read_phy_tstamp(hw, lport, 0, &tstamp); + if (ret) { + PMD_DRV_LOG(ERR, "Failed to read phy timestamp"); + return -1; + } + + ts_ns = ice_tstamp_convert_32b_64b(hw, ad, 1, (tstamp >> 8) & mask); + ns = rte_timecounter_update(&ad->tx_tstamp_tc, ts_ns); + *timestamp = rte_ns_to_timespec(ns); + + return 0; +} + +static int +ice_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) +{ + struct ice_adapter *ad = + ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); + + ad->systime_tc.nsec += delta; + ad->rx_tstamp_tc.nsec += delta; + ad->tx_tstamp_tc.nsec += delta; + + return 0; +} + +static int +ice_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) +{ + struct ice_adapter *ad = + ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); + uint64_t ns; + + ns = rte_timespec_to_ns(ts); + + ad->systime_tc.nsec = ns; + ad->rx_tstamp_tc.nsec = ns; + ad->tx_tstamp_tc.nsec = ns; + + return 0; +} + +static int +ice_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) +{ + struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct ice_adapter *ad = + ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); + uint32_t hi, lo, lo2; + uint64_t time, ns; + + lo = ICE_READ_REG(hw, GLTSYN_TIME_L(0)); + hi = ICE_READ_REG(hw, GLTSYN_TIME_H(0)); + lo2 = ICE_READ_REG(hw, GLTSYN_TIME_L(0)); + + if (lo2 < lo) { + lo = ICE_READ_REG(hw, GLTSYN_TIME_L(0)); + hi = ICE_READ_REG(hw, GLTSYN_TIME_H(0)); + } + + time = ((uint64_t)hi << 32) | lo; + ns = rte_timecounter_update(&ad->systime_tc, time); + *ts = rte_ns_to_timespec(ns); + + return 0; +} + +static int +ice_timesync_disable(struct rte_eth_dev *dev) +{ + struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct ice_adapter *ad = + ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); + uint64_t val; + uint8_t lport; + + lport = hw->port_info->lport; + + ice_clear_phy_tstamp(hw, lport, 0); + + val = ICE_READ_REG(hw, GLTSYN_ENA(0)); + val &= ~GLTSYN_ENA_TSYN_ENA_M; + ICE_WRITE_REG(hw, GLTSYN_ENA(0), val); + + ICE_WRITE_REG(hw, GLTSYN_INCVAL_L(0), 0); + ICE_WRITE_REG(hw, GLTSYN_INCVAL_H(0), 0); + + ad->ptp_ena = 0; + + return 0; +} + static int ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, struct rte_pci_device *pci_dev) @@ -4571,35 +5704,17 @@ RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd); RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map); RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci"); RTE_PMD_REGISTER_PARAM_STRING(net_ice, - ICE_PROTO_XTR_ARG "=[queue:]" + ICE_HW_DEBUG_MASK_ARG "=0xXXX" + ICE_PROTO_XTR_ARG "=[queue:]" ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>" ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>" - ICE_FLOW_MARK_SUPPORT_ARG "=<0|1>"); - -RTE_INIT(ice_init_log) -{ - ice_logtype_init = rte_log_register("pmd.net.ice.init"); - if (ice_logtype_init >= 0) - rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE); - ice_logtype_driver = rte_log_register("pmd.net.ice.driver"); - if (ice_logtype_driver >= 0) - rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE); + ICE_RX_LOW_LATENCY_ARG "=<0|1>"); -#ifdef RTE_LIBRTE_ICE_DEBUG_RX - ice_logtype_rx = rte_log_register("pmd.net.ice.rx"); - if (ice_logtype_rx >= 0) - rte_log_set_level(ice_logtype_rx, RTE_LOG_DEBUG); +RTE_LOG_REGISTER_SUFFIX(ice_logtype_init, init, NOTICE); +RTE_LOG_REGISTER_SUFFIX(ice_logtype_driver, driver, NOTICE); +#ifdef RTE_ETHDEV_DEBUG_RX +RTE_LOG_REGISTER_SUFFIX(ice_logtype_rx, rx, DEBUG); #endif - -#ifdef RTE_LIBRTE_ICE_DEBUG_TX - ice_logtype_tx = rte_log_register("pmd.net.ice.tx"); - if (ice_logtype_tx >= 0) - rte_log_set_level(ice_logtype_tx, RTE_LOG_DEBUG); -#endif - -#ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE - ice_logtype_tx_free = rte_log_register("pmd.net.ice.tx_free"); - if (ice_logtype_tx_free >= 0) - rte_log_set_level(ice_logtype_tx_free, RTE_LOG_DEBUG); +#ifdef RTE_ETHDEV_DEBUG_TX +RTE_LOG_REGISTER_SUFFIX(ice_logtype_tx, tx, DEBUG); #endif -}