X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fice%2Fice_ethdev.h;h=182c6f611ed9b6ceb6ab949364ec8cc1fecfa7e9;hb=2048f3a965d85f264ffe62a5dc7b272a85464331;hp=1516cf6cb1a7105cc1f282fd53d89196f1f89b56;hpb=37f4ac5f5946655fddedb8a78c079f2b190fa70e;p=dpdk.git

diff --git a/drivers/net/ice/ice_ethdev.h b/drivers/net/ice/ice_ethdev.h
index 1516cf6cb1..182c6f611e 100644
--- a/drivers/net/ice/ice_ethdev.h
+++ b/drivers/net/ice/ice_ethdev.h
@@ -117,13 +117,27 @@
 	ETH_RSS_NONFRAG_IPV6_OTHER | \
 	ETH_RSS_L2_PAYLOAD)
 
+/**
+ * The overhead from MTU to max frame size.
+ * Considering QinQ packet, the VLAN tag needs to be counted twice.
+ */
+#define ICE_ETH_OVERHEAD \
+	(RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + ICE_VLAN_TAG_SIZE * 2)
+
+/* DDP package type */
+enum ice_pkg_type {
+	ICE_PKG_TYPE_UNKNOWN,
+	ICE_PKG_TYPE_OS_DEFAULT,
+	ICE_PKG_TYPE_COMMS,
+};
+
 struct ice_adapter;
 
 /**
  * MAC filter structure
  */
 struct ice_mac_filter_info {
-	struct ether_addr mac_addr;
+	struct rte_ether_addr mac_addr;
 };
 
 TAILQ_HEAD(ice_mac_filter_list, ice_mac_filter);
@@ -227,6 +241,16 @@ struct ice_vsi {
 	bool offset_loaded;
 };
 
+extern const struct rte_flow_ops ice_flow_ops;
+
+/* Struct to store flow created. */
+struct rte_flow {
+	TAILQ_ENTRY(rte_flow) node;
+	void *rule;
+};
+
+TAILQ_HEAD(ice_flow_list, rte_flow);
+
 struct ice_pf {
 	struct ice_adapter *adapter; /* The adapter this PF associate to */
 	struct ice_vsi *main_vsi; /* pointer to main VSI structure */
@@ -240,11 +264,13 @@ struct ice_pf {
 	struct ice_res_pool_info qp_pool;    /*Queue pair pool */
 	struct ice_res_pool_info msix_pool;  /* MSIX interrupt pool */
 	struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
-	struct ether_addr dev_addr; /* PF device mac address */
+	struct rte_ether_addr dev_addr; /* PF device mac address */
 	uint64_t flags; /* PF feature flags */
 	uint16_t hash_lut_size; /* The size of hash lookup table */
 	uint16_t lan_nb_qp_max;
 	uint16_t lan_nb_qps; /* The number of queue pairs of LAN */
+	uint16_t base_queue; /* The base queue pairs index  in the device */
+	uint8_t *proto_xtr; /* Protocol extraction type for all queues */
 	struct ice_hw_port_stats stats_offset;
 	struct ice_hw_port_stats stats;
 	/* internal packet statistics, it should be excluded from the total */
@@ -252,6 +278,17 @@ struct ice_pf {
 	struct ice_eth_stats internal_stats;
 	bool offset_loaded;
 	bool adapter_stopped;
+	struct ice_flow_list flow_list;
+};
+
+#define ICE_MAX_QUEUE_NUM  2048
+
+/**
+ * Cache devargs parse result.
+ */
+struct ice_devargs {
+	int safe_mode_support;
+	uint8_t proto_xtr[ICE_MAX_QUEUE_NUM];
 };
 
 /**
@@ -263,10 +300,14 @@ struct ice_adapter {
 	struct rte_eth_dev *eth_dev;
 	struct ice_pf pf;
 	bool rx_bulk_alloc_allowed;
+	bool rx_vec_allowed;
+	bool tx_vec_allowed;
 	bool tx_simple_allowed;
 	/* ptype mapping table */
 	uint32_t ptype_tbl[ICE_MAX_PKT_TYPE] __rte_cache_min_aligned;
 	bool is_safe_mode;
+	struct ice_devargs devargs;
+	enum ice_pkg_type active_pkg_type; /* loaded ddp package type */
 };
 
 struct ice_vsi_vlan_pvid_info {
@@ -318,4 +359,44 @@ ice_align_floor(int n)
 		return 0;
 	return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));
 }
+
+#define ICE_PHY_TYPE_SUPPORT_50G(phy_type) \
+	(((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_CR2) || \
+	((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_SR2) || \
+	((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_LR2) || \
+	((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_KR2) || \
+	((phy_type) & ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC) || \
+	((phy_type) & ICE_PHY_TYPE_LOW_50G_LAUI2) || \
+	((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC) || \
+	((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI2) || \
+	((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_CP) || \
+	((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_SR) || \
+	((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_FR) || \
+	((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_LR) || \
+	((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4) || \
+	((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC) || \
+	((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI1))
+
+#define ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type) \
+	(((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CR4) || \
+	((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_SR4) || \
+	((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_LR4) || \
+	((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_KR4) || \
+	((phy_type) & ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC) || \
+	((phy_type) & ICE_PHY_TYPE_LOW_100G_CAUI4) || \
+	((phy_type) & ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC) || \
+	((phy_type) & ICE_PHY_TYPE_LOW_100G_AUI4) || \
+	((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4) || \
+	((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4) || \
+	((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CP2) || \
+	((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_SR2) || \
+	((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_DR))
+
+#define ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type) \
+	(((phy_type) & ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4) || \
+	((phy_type) & ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC) || \
+	((phy_type) & ICE_PHY_TYPE_HIGH_100G_CAUI2) || \
+	((phy_type) & ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC) || \
+	((phy_type) & ICE_PHY_TYPE_HIGH_100G_AUI2))
+
 #endif /* _ICE_ETHDEV_H_ */