X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fice%2Fice_rxtx.c;h=8d4820d3c82603ae254fb397bb473cdb723c4f10;hb=b5fedaedfcf272d1a86802132a1691ac5485f31d;hp=c794ee861ae09df7e73990b276aa54beed318be1;hpb=89760a006b826ec3f85f46f2c7a04efe75a8d6fa;p=dpdk.git diff --git a/drivers/net/ice/ice_rxtx.c b/drivers/net/ice/ice_rxtx.c index c794ee861a..8d4820d3c8 100644 --- a/drivers/net/ice/ice_rxtx.c +++ b/drivers/net/ice/ice_rxtx.c @@ -7,15 +7,41 @@ #include "ice_rxtx.h" -#define ICE_TD_CMD ICE_TX_DESC_CMD_EOP - #define ICE_TX_CKSUM_OFFLOAD_MASK ( \ PKT_TX_IP_CKSUM | \ PKT_TX_L4_MASK | \ PKT_TX_TCP_SEG | \ PKT_TX_OUTER_IP_CKSUM) -#define ICE_RX_ERR_BITS 0x3f +static inline uint8_t +ice_rxdid_to_proto_xtr_type(uint8_t rxdid) +{ + static uint8_t xtr_map[] = { + [ICE_RXDID_COMMS_AUX_VLAN] = PROTO_XTR_VLAN, + [ICE_RXDID_COMMS_AUX_IPV4] = PROTO_XTR_IPV4, + [ICE_RXDID_COMMS_AUX_IPV6] = PROTO_XTR_IPV6, + [ICE_RXDID_COMMS_AUX_IPV6_FLOW] = PROTO_XTR_IPV6_FLOW, + [ICE_RXDID_COMMS_AUX_TCP] = PROTO_XTR_TCP, + }; + + return rxdid < RTE_DIM(xtr_map) ? xtr_map[rxdid] : PROTO_XTR_NONE; +} + +static inline uint8_t +ice_proto_xtr_type_to_rxdid(uint8_t xtr_type) +{ + static uint8_t rxdid_map[] = { + [PROTO_XTR_NONE] = ICE_RXDID_COMMS_GENERIC, + [PROTO_XTR_VLAN] = ICE_RXDID_COMMS_AUX_VLAN, + [PROTO_XTR_IPV4] = ICE_RXDID_COMMS_AUX_IPV4, + [PROTO_XTR_IPV6] = ICE_RXDID_COMMS_AUX_IPV6, + [PROTO_XTR_IPV6_FLOW] = ICE_RXDID_COMMS_AUX_IPV6_FLOW, + [PROTO_XTR_TCP] = ICE_RXDID_COMMS_AUX_TCP, + }; + + return xtr_type < RTE_DIM(rxdid_map) ? + rxdid_map[xtr_type] : ICE_RXDID_COMMS_GENERIC; +} static enum ice_status ice_program_hw_rx_queue(struct ice_rx_queue *rxq) @@ -27,18 +53,9 @@ ice_program_hw_rx_queue(struct ice_rx_queue *rxq) enum ice_status err; uint16_t buf_size, len; struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; + uint32_t rxdid = ICE_RXDID_COMMS_GENERIC; uint32_t regval; - /** - * The kernel driver uses flex descriptor. It sets the register - * to flex descriptor mode. - * DPDK uses legacy descriptor. It should set the register back - * to the default value, then uses legacy descriptor mode. - */ - regval = (0x01 << QRXFLXP_CNTXT_RXDID_PRIO_S) & - QRXFLXP_CNTXT_RXDID_PRIO_M; - ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval); - /* Set buffer size as the head split is disabled. */ buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) - RTE_PKTMBUF_HEADROOM); @@ -49,30 +66,30 @@ ice_program_hw_rx_queue(struct ice_rx_queue *rxq) dev->data->dev_conf.rxmode.max_rx_pkt_len); if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { - if (rxq->max_pkt_len <= ETHER_MAX_LEN || + if (rxq->max_pkt_len <= RTE_ETHER_MAX_LEN || rxq->max_pkt_len > ICE_FRAME_SIZE_MAX) { PMD_DRV_LOG(ERR, "maximum packet length must " "be larger than %u and smaller than %u," "as jumbo frame is enabled", - (uint32_t)ETHER_MAX_LEN, + (uint32_t)RTE_ETHER_MAX_LEN, (uint32_t)ICE_FRAME_SIZE_MAX); return -EINVAL; } } else { - if (rxq->max_pkt_len < ETHER_MIN_LEN || - rxq->max_pkt_len > ETHER_MAX_LEN) { + if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN || + rxq->max_pkt_len > RTE_ETHER_MAX_LEN) { PMD_DRV_LOG(ERR, "maximum packet length must be " "larger than %u and smaller than %u, " "as jumbo frame is disabled", - (uint32_t)ETHER_MIN_LEN, - (uint32_t)ETHER_MAX_LEN); + (uint32_t)RTE_ETHER_MIN_LEN, + (uint32_t)RTE_ETHER_MAX_LEN); return -EINVAL; } } memset(&rx_ctx, 0, sizeof(rx_ctx)); - rx_ctx.base = rxq->rx_ring_phys_addr / ICE_QUEUE_BASE_ADDR_UNIT; + rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT; rx_ctx.qlen = rxq->nb_rx_desc; rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S; rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S; @@ -96,6 +113,26 @@ ice_program_hw_rx_queue(struct ice_rx_queue *rxq) rx_ctx.showiv = 0; rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0; + rxdid = ice_proto_xtr_type_to_rxdid(rxq->proto_xtr); + + PMD_DRV_LOG(DEBUG, "Port (%u) - Rx queue (%u) is set with RXDID : %u", + rxq->port_id, rxq->queue_id, rxdid); + + /* Enable Flexible Descriptors in the queue context which + * allows this driver to select a specific receive descriptor format + */ + regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) & + QRXFLXP_CNTXT_RXDID_IDX_M; + + /* increasing context priority to pick up profile ID; + * default is 0x01; setting to 0x03 to ensure profile + * is programming if prev context is of same priority + */ + regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) & + QRXFLXP_CNTXT_RXDID_PRIO_M; + + ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval); + err = ice_clear_rxq_ctx(hw, rxq->reg_idx); if (err) { PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context", @@ -113,7 +150,7 @@ ice_program_hw_rx_queue(struct ice_rx_queue *rxq) RTE_PKTMBUF_HEADROOM); /* Check if scattered RX needs to be used. */ - if ((rxq->max_pkt_len + 2 * ICE_VLAN_TAG_SIZE) > buf_size) + if (rxq->max_pkt_len > buf_size) dev->data->scattered_rx = 1; rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx); @@ -133,7 +170,7 @@ ice_alloc_rx_queue_mbufs(struct ice_rx_queue *rxq) uint16_t i; for (i = 0; i < rxq->nb_rx_desc; i++) { - volatile union ice_rx_desc *rxd; + volatile union ice_rx_flex_desc *rxd; struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp); if (unlikely(!mbuf)) { @@ -165,7 +202,7 @@ ice_alloc_rx_queue_mbufs(struct ice_rx_queue *rxq) /* Free all mbufs for descriptors in rx queue */ static void -ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq) +_ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq) { uint16_t i; @@ -193,6 +230,12 @@ ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq) #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */ } +static void +ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq) +{ + rxq->rx_rel_mbufs(rxq); +} + /* turn on or off rx queue * @q_idx: queue index in pf scope * @on: turn on or off the queue @@ -302,7 +345,7 @@ ice_reset_rx_queue(struct ice_rx_queue *rxq) #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */ len = rxq->nb_rx_desc; - for (i = 0; i < len * sizeof(union ice_rx_desc); i++) + for (i = 0; i < len * sizeof(union ice_rx_flex_desc); i++) ((volatile char *)rxq->rx_ring)[i] = 0; #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC @@ -319,6 +362,9 @@ ice_reset_rx_queue(struct ice_rx_queue *rxq) rxq->nb_rx_hold = 0; rxq->pkt_first_seg = NULL; rxq->pkt_last_seg = NULL; + + rxq->rxrearm_start = 0; + rxq->rxrearm_nb = 0; } int @@ -356,8 +402,6 @@ ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id) return -ENOMEM; } - rte_wmb(); - /* Init the RX tail register. */ ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1); @@ -435,7 +479,7 @@ ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id) txq_elem.num_txqs = 1; txq_elem.txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx); - tx_ctx.base = txq->tx_ring_phys_addr / ICE_QUEUE_BASE_ADDR_UNIT; + tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT; tx_ctx.qlen = txq->nb_tx_desc; tx_ctx.pf_num = hw->pf_id; tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF; @@ -453,8 +497,9 @@ ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id) /* Init the Tx tail register*/ ICE_PCI_REG_WRITE(txq->qtx_tail, 0); - err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, 1, &txq_elem, - sizeof(txq_elem), NULL); + /* Fix me, we assume TC always 0 here */ + err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1, + &txq_elem, sizeof(txq_elem), NULL); if (err) { PMD_DRV_LOG(ERR, "Failed to add lan txq"); return -EIO; @@ -466,9 +511,182 @@ ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id) return 0; } +static enum ice_status +ice_fdir_program_hw_rx_queue(struct ice_rx_queue *rxq) +{ + struct ice_vsi *vsi = rxq->vsi; + struct ice_hw *hw = ICE_VSI_TO_HW(vsi); + uint32_t rxdid = ICE_RXDID_COMMS_GENERIC; + struct ice_rlan_ctx rx_ctx; + enum ice_status err; + uint32_t regval; + + rxq->rx_hdr_len = 0; + rxq->rx_buf_len = 1024; + + memset(&rx_ctx, 0, sizeof(rx_ctx)); + + rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT; + rx_ctx.qlen = rxq->nb_rx_desc; + rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S; + rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S; + rx_ctx.dtype = 0; /* No Header Split mode */ +#ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC + rx_ctx.dsize = 1; /* 32B descriptors */ +#endif + rx_ctx.rxmax = RTE_ETHER_MAX_LEN; + /* TPH: Transaction Layer Packet (TLP) processing hints */ + rx_ctx.tphrdesc_ena = 1; + rx_ctx.tphwdesc_ena = 1; + rx_ctx.tphdata_ena = 1; + rx_ctx.tphhead_ena = 1; + /* Low Receive Queue Threshold defined in 64 descriptors units. + * When the number of free descriptors goes below the lrxqthresh, + * an immediate interrupt is triggered. + */ + rx_ctx.lrxqthresh = 2; + /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/ + rx_ctx.l2tsel = 1; + rx_ctx.showiv = 0; + rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0; + + /* Enable Flexible Descriptors in the queue context which + * allows this driver to select a specific receive descriptor format + */ + regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) & + QRXFLXP_CNTXT_RXDID_IDX_M; + + /* increasing context priority to pick up profile ID; + * default is 0x01; setting to 0x03 to ensure profile + * is programming if prev context is of same priority + */ + regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) & + QRXFLXP_CNTXT_RXDID_PRIO_M; + + ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval); + + err = ice_clear_rxq_ctx(hw, rxq->reg_idx); + if (err) { + PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context", + rxq->queue_id); + return -EINVAL; + } + err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx); + if (err) { + PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context", + rxq->queue_id); + return -EINVAL; + } + + rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx); + + /* Init the Rx tail register*/ + ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1); + + return 0; +} + +int +ice_fdir_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id) +{ + struct ice_rx_queue *rxq; + int err; + struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); + + PMD_INIT_FUNC_TRACE(); + + rxq = pf->fdir.rxq; + if (!rxq || !rxq->q_set) { + PMD_DRV_LOG(ERR, "FDIR RX queue %u not available or setup", + rx_queue_id); + return -EINVAL; + } + + err = ice_fdir_program_hw_rx_queue(rxq); + if (err) { + PMD_DRV_LOG(ERR, "fail to program FDIR RX queue %u", + rx_queue_id); + return -EIO; + } + + /* Init the RX tail register. */ + ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1); + + err = ice_switch_rx_queue(hw, rxq->reg_idx, TRUE); + if (err) { + PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u on", + rx_queue_id); + + ice_reset_rx_queue(rxq); + return -EINVAL; + } + + return 0; +} + +int +ice_fdir_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id) +{ + struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); + struct ice_tx_queue *txq; + int err; + struct ice_vsi *vsi; + struct ice_hw *hw; + struct ice_aqc_add_tx_qgrp txq_elem; + struct ice_tlan_ctx tx_ctx; + + PMD_INIT_FUNC_TRACE(); + + txq = pf->fdir.txq; + if (!txq || !txq->q_set) { + PMD_DRV_LOG(ERR, "FDIR TX queue %u is not available or setup", + tx_queue_id); + return -EINVAL; + } + + vsi = txq->vsi; + hw = ICE_VSI_TO_HW(vsi); + + memset(&txq_elem, 0, sizeof(txq_elem)); + memset(&tx_ctx, 0, sizeof(tx_ctx)); + txq_elem.num_txqs = 1; + txq_elem.txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx); + + tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT; + tx_ctx.qlen = txq->nb_tx_desc; + tx_ctx.pf_num = hw->pf_id; + tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF; + tx_ctx.src_vsi = vsi->vsi_id; + tx_ctx.port_num = hw->port_info->lport; + tx_ctx.tso_ena = 1; /* tso enable */ + tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */ + tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */ + + ice_set_ctx((uint8_t *)&tx_ctx, txq_elem.txqs[0].txq_ctx, + ice_tlan_ctx_info); + + txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx); + + /* Init the Tx tail register*/ + ICE_PCI_REG_WRITE(txq->qtx_tail, 0); + + /* Fix me, we assume TC always 0 here */ + err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1, + &txq_elem, sizeof(txq_elem), NULL); + if (err) { + PMD_DRV_LOG(ERR, "Failed to add FDIR txq"); + return -EIO; + } + /* store the schedule node id */ + txq->q_teid = txq_elem.txqs[0].q_teid; + + return 0; +} + /* Free all mbufs for descriptors in tx queue */ static void -ice_tx_queue_release_mbufs(struct ice_tx_queue *txq) +_ice_tx_queue_release_mbufs(struct ice_tx_queue *txq) { uint16_t i; @@ -484,6 +702,11 @@ ice_tx_queue_release_mbufs(struct ice_tx_queue *txq) } } } +static void +ice_tx_queue_release_mbufs(struct ice_tx_queue *txq) +{ + txq->tx_rel_mbufs(txq); +} static void ice_reset_tx_queue(struct ice_tx_queue *txq) @@ -528,9 +751,12 @@ ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id) { struct ice_tx_queue *txq; struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); + struct ice_vsi *vsi = pf->main_vsi; enum ice_status status; uint16_t q_ids[1]; uint32_t q_teids[1]; + uint16_t q_handle = tx_queue_id; if (tx_queue_id >= dev->data->nb_tx_queues) { PMD_DRV_LOG(ERR, "TX queue %u is out of range %u", @@ -548,8 +774,9 @@ ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id) q_ids[0] = txq->reg_idx; q_teids[0] = txq->q_teid; - status = ice_dis_vsi_txq(hw->port_info, 1, q_ids, q_teids, - ICE_NO_RESET, 0, NULL); + /* Fix me, we assume TC always 0 here */ + status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle, + q_ids, q_teids, ICE_NO_RESET, 0, NULL); if (status != ICE_SUCCESS) { PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue"); return -EINVAL; @@ -562,6 +789,63 @@ ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id) return 0; } +int +ice_fdir_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id) +{ + struct ice_rx_queue *rxq; + int err; + struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); + + rxq = pf->fdir.rxq; + + err = ice_switch_rx_queue(hw, rxq->reg_idx, FALSE); + if (err) { + PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u off", + rx_queue_id); + return -EINVAL; + } + ice_rx_queue_release_mbufs(rxq); + + return 0; +} + +int +ice_fdir_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id) +{ + struct ice_tx_queue *txq; + struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); + struct ice_vsi *vsi = pf->main_vsi; + enum ice_status status; + uint16_t q_ids[1]; + uint32_t q_teids[1]; + uint16_t q_handle = tx_queue_id; + + txq = pf->fdir.txq; + if (!txq) { + PMD_DRV_LOG(ERR, "TX queue %u is not available", + tx_queue_id); + return -EINVAL; + } + vsi = txq->vsi; + + q_ids[0] = txq->reg_idx; + q_teids[0] = txq->q_teid; + + /* Fix me, we assume TC always 0 here */ + status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle, + q_ids, q_teids, ICE_NO_RESET, 0, NULL); + if (status != ICE_SUCCESS) { + PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue"); + return -EINVAL; + } + + ice_tx_queue_release_mbufs(txq); + + return 0; +} + int ice_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, @@ -612,13 +896,15 @@ ice_rx_queue_setup(struct rte_eth_dev *dev, rxq->reg_idx = vsi->base_queue + queue_idx; rxq->port_id = dev->data->port_id; if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) - rxq->crc_len = ETHER_CRC_LEN; + rxq->crc_len = RTE_ETHER_CRC_LEN; else rxq->crc_len = 0; rxq->drop_en = rx_conf->rx_drop_en; rxq->vsi = vsi; rxq->rx_deferred_start = rx_conf->rx_deferred_start; + rxq->proto_xtr = pf->proto_xtr != NULL ? + pf->proto_xtr[queue_idx] : PROTO_XTR_NONE; /* Allocate the maximun number of RX ring hardware descriptor. */ len = ICE_MAX_RING_DESC; @@ -632,7 +918,7 @@ ice_rx_queue_setup(struct rte_eth_dev *dev, #endif /* Allocate the maximum number of RX ring hardware descriptor. */ - ring_size = sizeof(union ice_rx_desc) * len; + ring_size = sizeof(union ice_rx_flex_desc) * len; ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN); rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx, ring_size, ICE_RING_BASE_ALIGN, @@ -646,8 +932,8 @@ ice_rx_queue_setup(struct rte_eth_dev *dev, /* Zero all the descriptors in the ring. */ memset(rz->addr, 0, ring_size); - rxq->rx_ring_phys_addr = rz->phys_addr; - rxq->rx_ring = (union ice_rx_desc *)rz->addr; + rxq->rx_ring_dma = rz->iova; + rxq->rx_ring = rz->addr; #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC len = (uint16_t)(nb_desc + ICE_RX_MAX_BURST); @@ -669,6 +955,7 @@ ice_rx_queue_setup(struct rte_eth_dev *dev, ice_reset_rx_queue(rxq); rxq->q_set = TRUE; dev->data->rx_queues[queue_idx] = rxq; + rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs; use_def_burst_func = ice_check_rx_burst_bulk_alloc_preconditions(rxq); @@ -746,17 +1033,32 @@ ice_tx_queue_setup(struct rte_eth_dev *dev, * - tx_rs_thresh must be a divisor of the ring size. * - tx_free_thresh must be greater than 0. * - tx_free_thresh must be less than the size of the ring minus 3. + * - tx_free_thresh + tx_rs_thresh must not exceed nb_desc. * * One descriptor in the TX ring is used as a sentinel to avoid a H/W * race condition, hence the maximum threshold constraints. When set * to zero use default values. */ - tx_rs_thresh = (uint16_t)(tx_conf->tx_rs_thresh ? - tx_conf->tx_rs_thresh : - ICE_DEFAULT_TX_RSBIT_THRESH); tx_free_thresh = (uint16_t)(tx_conf->tx_free_thresh ? tx_conf->tx_free_thresh : ICE_DEFAULT_TX_FREE_THRESH); + /* force tx_rs_thresh to adapt an aggresive tx_free_thresh */ + tx_rs_thresh = + (ICE_DEFAULT_TX_RSBIT_THRESH + tx_free_thresh > nb_desc) ? + nb_desc - tx_free_thresh : ICE_DEFAULT_TX_RSBIT_THRESH; + if (tx_conf->tx_rs_thresh) + tx_rs_thresh = tx_conf->tx_rs_thresh; + if (tx_rs_thresh + tx_free_thresh > nb_desc) { + PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not " + "exceed nb_desc. (tx_rs_thresh=%u " + "tx_free_thresh=%u nb_desc=%u port = %d queue=%d)", + (unsigned int)tx_rs_thresh, + (unsigned int)tx_free_thresh, + (unsigned int)nb_desc, + (int)dev->data->port_id, + (int)queue_idx); + return -EINVAL; + } if (tx_rs_thresh >= (nb_desc - 2)) { PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the " "number of TX descriptors minus 2. " @@ -848,8 +1150,8 @@ ice_tx_queue_setup(struct rte_eth_dev *dev, txq->vsi = vsi; txq->tx_deferred_start = tx_conf->tx_deferred_start; - txq->tx_ring_phys_addr = tz->phys_addr; - txq->tx_ring = (struct ice_tx_desc *)tz->addr; + txq->tx_ring_dma = tz->iova; + txq->tx_ring = tz->addr; /* Allocate software ring */ txq->sw_ring = @@ -866,6 +1168,8 @@ ice_tx_queue_setup(struct rte_eth_dev *dev, ice_reset_tx_queue(txq); txq->q_set = TRUE; dev->data->tx_queues[queue_idx] = txq; + txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs; + ice_set_tx_function_flag(dev, txq); return 0; } @@ -926,16 +1230,15 @@ uint32_t ice_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id) { #define ICE_RXQ_SCAN_INTERVAL 4 - volatile union ice_rx_desc *rxdp; + volatile union ice_rx_flex_desc *rxdp; struct ice_rx_queue *rxq; uint16_t desc = 0; rxq = dev->data->rx_queues[rx_queue_id]; rxdp = &rxq->rx_ring[rxq->rx_tail]; while ((desc < rxq->nb_rx_desc) && - ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) & - ICE_RXD_QW1_STATUS_M) >> ICE_RXD_QW1_STATUS_S) & - (1 << ICE_RX_DESC_STATUS_DD_S)) { + rte_le_to_cpu_16(rxdp->wb.status_error0) & + (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)) { /** * Check the DD bit of a rx descriptor of each 4 in a group, * to avoid checking too frequently and downgrading performance @@ -951,72 +1254,69 @@ ice_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id) return desc; } -/* Translate the rx descriptor status to pkt flags */ -static inline uint64_t -ice_rxd_status_to_pkt_flags(uint64_t qword) -{ - uint64_t flags; - - /* Check if RSS_HASH */ - flags = (((qword >> ICE_RX_DESC_STATUS_FLTSTAT_S) & - ICE_RX_DESC_FLTSTAT_RSS_HASH) == - ICE_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0; - - return flags; -} +#define ICE_RX_FLEX_ERR0_BITS \ + ((1 << ICE_RX_FLEX_DESC_STATUS0_HBO_S) | \ + (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) | \ + (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) | \ + (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \ + (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) | \ + (1 << ICE_RX_FLEX_DESC_STATUS0_RXE_S)) /* Rx L3/L4 checksum */ static inline uint64_t -ice_rxd_error_to_pkt_flags(uint64_t qword) +ice_rxd_error_to_pkt_flags(uint16_t stat_err0) { uint64_t flags = 0; - uint64_t error_bits = (qword >> ICE_RXD_QW1_ERROR_S); - if (likely((error_bits & ICE_RX_ERR_BITS) == 0)) { + /* check if HW has decoded the packet and checksum */ + if (unlikely(!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_L3L4P_S)))) + return 0; + + if (likely(!(stat_err0 & ICE_RX_FLEX_ERR0_BITS))) { flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD); return flags; } - if (unlikely(error_bits & (1 << ICE_RX_DESC_ERROR_IPE_S))) + if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S))) flags |= PKT_RX_IP_CKSUM_BAD; else flags |= PKT_RX_IP_CKSUM_GOOD; - if (unlikely(error_bits & (1 << ICE_RX_DESC_ERROR_L4E_S))) + if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S))) flags |= PKT_RX_L4_CKSUM_BAD; else flags |= PKT_RX_L4_CKSUM_GOOD; - if (unlikely(error_bits & (1 << ICE_RX_DESC_ERROR_EIPE_S))) + if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S))) flags |= PKT_RX_EIP_CKSUM_BAD; return flags; } static inline void -ice_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union ice_rx_desc *rxdp) +ice_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union ice_rx_flex_desc *rxdp) { - if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) & - (1 << ICE_RX_DESC_STATUS_L2TAG1P_S)) { + if (rte_le_to_cpu_16(rxdp->wb.status_error0) & + (1 << ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) { mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED; mb->vlan_tci = - rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1); + rte_le_to_cpu_16(rxdp->wb.l2tag1); PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u", - rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1)); + rte_le_to_cpu_16(rxdp->wb.l2tag1)); } else { mb->vlan_tci = 0; } #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC - if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) & - (1 << ICE_RX_DESC_EXT_STATUS_L2TAG2P_S)) { + if (rte_le_to_cpu_16(rxdp->wb.status_error1) & + (1 << ICE_RX_FLEX_DESC_STATUS1_L2TAG2P_S)) { mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ | PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN; mb->vlan_tci_outer = mb->vlan_tci; - mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2); + mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd); PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u", - rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1), - rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2)); + rte_le_to_cpu_16(rxdp->wb.l2tag2_1st), + rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd)); } else { mb->vlan_tci_outer = 0; } @@ -1025,6 +1325,50 @@ ice_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union ice_rx_desc *rxdp) mb->vlan_tci, mb->vlan_tci_outer); } +#define ICE_RX_PROTO_XTR_VALID \ + ((1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S) | \ + (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S)) + +static inline void +ice_rxd_to_pkt_fields(struct rte_mbuf *mb, + volatile union ice_rx_flex_desc *rxdp) +{ + volatile struct ice_32b_rx_flex_desc_comms *desc = + (volatile struct ice_32b_rx_flex_desc_comms *)rxdp; + uint16_t stat_err; + + stat_err = rte_le_to_cpu_16(desc->status_error0); + if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) { + mb->ol_flags |= PKT_RX_RSS_HASH; + mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash); + } + +#ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC + init_proto_xtr_flds(mb); + + stat_err = rte_le_to_cpu_16(desc->status_error1); + if (stat_err & ICE_RX_PROTO_XTR_VALID) { + struct proto_xtr_flds *xtr = get_proto_xtr_flds(mb); + + if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S)) + xtr->u.raw.data0 = + rte_le_to_cpu_16(desc->flex_ts.flex.aux0); + + if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S)) + xtr->u.raw.data1 = + rte_le_to_cpu_16(desc->flex_ts.flex.aux1); + + xtr->type = ice_rxdid_to_proto_xtr_type(desc->rxdid); + xtr->magic = PROTO_XTR_MAGIC_ID; + } + + if (desc->flow_id != 0xFFFFFFFF) { + mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID; + mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id); + } +#endif +} + #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC #define ICE_LOOK_AHEAD 8 #if (ICE_LOOK_AHEAD != 8) @@ -1033,12 +1377,11 @@ ice_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union ice_rx_desc *rxdp) static inline int ice_rx_scan_hw_ring(struct ice_rx_queue *rxq) { - volatile union ice_rx_desc *rxdp; + volatile union ice_rx_flex_desc *rxdp; struct ice_rx_entry *rxep; struct rte_mbuf *mb; + uint16_t stat_err0; uint16_t pkt_len; - uint64_t qword1; - uint32_t rx_status; int32_t s[ICE_LOOK_AHEAD], nb_dd; int32_t i, j, nb_rx = 0; uint64_t pkt_flags = 0; @@ -1047,11 +1390,10 @@ ice_rx_scan_hw_ring(struct ice_rx_queue *rxq) rxdp = &rxq->rx_ring[rxq->rx_tail]; rxep = &rxq->sw_ring[rxq->rx_tail]; - qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len); - rx_status = (qword1 & ICE_RXD_QW1_STATUS_M) >> ICE_RXD_QW1_STATUS_S; + stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0); /* Make sure there is at least 1 packet to receive */ - if (!(rx_status & (1 << ICE_RX_DESC_STATUS_DD_S))) + if (!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S))) return 0; /** @@ -1061,42 +1403,31 @@ ice_rx_scan_hw_ring(struct ice_rx_queue *rxq) for (i = 0; i < ICE_RX_MAX_BURST; i += ICE_LOOK_AHEAD, rxdp += ICE_LOOK_AHEAD, rxep += ICE_LOOK_AHEAD) { /* Read desc statuses backwards to avoid race condition */ - for (j = ICE_LOOK_AHEAD - 1; j >= 0; j--) { - qword1 = rte_le_to_cpu_64( - rxdp[j].wb.qword1.status_error_len); - s[j] = (qword1 & ICE_RXD_QW1_STATUS_M) >> - ICE_RXD_QW1_STATUS_S; - } + for (j = ICE_LOOK_AHEAD - 1; j >= 0; j--) + s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0); rte_smp_rmb(); /* Compute how many status bits were set */ for (j = 0, nb_dd = 0; j < ICE_LOOK_AHEAD; j++) - nb_dd += s[j] & (1 << ICE_RX_DESC_STATUS_DD_S); + nb_dd += s[j] & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S); nb_rx += nb_dd; /* Translate descriptor info to mbuf parameters */ for (j = 0; j < nb_dd; j++) { mb = rxep[j].mbuf; - qword1 = rte_le_to_cpu_64( - rxdp[j].wb.qword1.status_error_len); - pkt_len = ((qword1 & ICE_RXD_QW1_LEN_PBUF_M) >> - ICE_RXD_QW1_LEN_PBUF_S) - rxq->crc_len; + pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) & + ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len; mb->data_len = pkt_len; mb->pkt_len = pkt_len; mb->ol_flags = 0; - pkt_flags = ice_rxd_status_to_pkt_flags(qword1); - pkt_flags |= ice_rxd_error_to_pkt_flags(qword1); - if (pkt_flags & PKT_RX_RSS_HASH) - mb->hash.rss = - rte_le_to_cpu_32( - rxdp[j].wb.qword0.hi_dword.rss); - mb->packet_type = ptype_tbl[(uint8_t)( - (qword1 & - ICE_RXD_QW1_PTYPE_M) >> - ICE_RXD_QW1_PTYPE_S)]; + stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0); + pkt_flags = ice_rxd_error_to_pkt_flags(stat_err0); + mb->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M & + rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)]; ice_rxd_to_vlan_tci(mb, &rxdp[j]); + ice_rxd_to_pkt_fields(mb, &rxdp[j]); mb->ol_flags |= pkt_flags; } @@ -1141,7 +1472,7 @@ ice_rx_fill_from_stage(struct ice_rx_queue *rxq, static inline int ice_rx_alloc_bufs(struct ice_rx_queue *rxq) { - volatile union ice_rx_desc *rxdp; + volatile union ice_rx_flex_desc *rxdp; struct ice_rx_entry *rxep; struct rte_mbuf *mb; uint16_t alloc_idx, i; @@ -1177,7 +1508,6 @@ ice_rx_alloc_bufs(struct ice_rx_queue *rxq) } /* Update rx tail regsiter */ - rte_wmb(); ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger); rxq->rx_free_trigger = @@ -1276,9 +1606,9 @@ ice_recv_scattered_pkts(void *rx_queue, uint16_t nb_pkts) { struct ice_rx_queue *rxq = rx_queue; - volatile union ice_rx_desc *rx_ring = rxq->rx_ring; - volatile union ice_rx_desc *rxdp; - union ice_rx_desc rxd; + volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring; + volatile union ice_rx_flex_desc *rxdp; + union ice_rx_flex_desc rxd; struct ice_rx_entry *sw_ring = rxq->sw_ring; struct ice_rx_entry *rxe; struct rte_mbuf *first_seg = rxq->pkt_first_seg; @@ -1289,21 +1619,18 @@ ice_recv_scattered_pkts(void *rx_queue, uint16_t nb_rx = 0; uint16_t nb_hold = 0; uint16_t rx_packet_len; - uint32_t rx_status; - uint64_t qword1; + uint16_t rx_stat_err0; uint64_t dma_addr; - uint64_t pkt_flags = 0; + uint64_t pkt_flags; uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl; struct rte_eth_dev *dev; while (nb_rx < nb_pkts) { rxdp = &rx_ring[rx_id]; - qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len); - rx_status = (qword1 & ICE_RXD_QW1_STATUS_M) >> - ICE_RXD_QW1_STATUS_S; + rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0); /* Check the DD bit first */ - if (!(rx_status & (1 << ICE_RX_DESC_STATUS_DD_S))) + if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S))) break; /* allocate mbuf */ @@ -1342,14 +1669,10 @@ ice_recv_scattered_pkts(void *rx_queue, /* Set data buffer address and data length of the mbuf */ rxdp->read.hdr_addr = 0; rxdp->read.pkt_addr = dma_addr; - rx_packet_len = (qword1 & ICE_RXD_QW1_LEN_PBUF_M) >> - ICE_RXD_QW1_LEN_PBUF_S; + rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) & + ICE_RX_FLX_DESC_PKT_LEN_M; rxm->data_len = rx_packet_len; rxm->data_off = RTE_PKTMBUF_HEADROOM; - ice_rxd_to_vlan_tci(rxm, rxdp); - rxm->packet_type = ptype_tbl[(uint8_t)((qword1 & - ICE_RXD_QW1_PTYPE_M) >> - ICE_RXD_QW1_PTYPE_S)]; /** * If this is the first buffer of the received packet, set the @@ -1375,7 +1698,7 @@ ice_recv_scattered_pkts(void *rx_queue, * update the pointer to the last mbuf of the current scattered * packet and continue to parse the RX ring. */ - if (!(rx_status & (1 << ICE_RX_DESC_STATUS_EOF_S))) { + if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_EOF_S))) { last_seg = rxm; continue; } @@ -1392,28 +1715,26 @@ ice_recv_scattered_pkts(void *rx_queue, */ rxm->next = NULL; if (unlikely(rxq->crc_len > 0)) { - first_seg->pkt_len -= ETHER_CRC_LEN; - if (rx_packet_len <= ETHER_CRC_LEN) { + first_seg->pkt_len -= RTE_ETHER_CRC_LEN; + if (rx_packet_len <= RTE_ETHER_CRC_LEN) { rte_pktmbuf_free_seg(rxm); first_seg->nb_segs--; last_seg->data_len = (uint16_t)(last_seg->data_len - - (ETHER_CRC_LEN - rx_packet_len)); + (RTE_ETHER_CRC_LEN - rx_packet_len)); last_seg->next = NULL; } else rxm->data_len = (uint16_t)(rx_packet_len - - ETHER_CRC_LEN); + RTE_ETHER_CRC_LEN); } first_seg->port = rxq->port_id; first_seg->ol_flags = 0; - - pkt_flags = ice_rxd_status_to_pkt_flags(qword1); - pkt_flags |= ice_rxd_error_to_pkt_flags(qword1); - if (pkt_flags & PKT_RX_RSS_HASH) - first_seg->hash.rss = - rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss); - + first_seg->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M & + rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)]; + ice_rxd_to_vlan_tci(first_seg, &rxd); + ice_rxd_to_pkt_fields(first_seg, &rxd); + pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0); first_seg->ol_flags |= pkt_flags; /* Prefetch data of first segment, if configured to do so. */ rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr, @@ -1488,15 +1809,23 @@ ice_dev_supported_ptypes_get(struct rte_eth_dev *dev) #endif dev->rx_pkt_burst == ice_recv_scattered_pkts) return ptypes; + +#ifdef RTE_ARCH_X86 + if (dev->rx_pkt_burst == ice_recv_pkts_vec || + dev->rx_pkt_burst == ice_recv_scattered_pkts_vec || + dev->rx_pkt_burst == ice_recv_pkts_vec_avx2 || + dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2) + return ptypes; +#endif + return NULL; } int ice_rx_descriptor_status(void *rx_queue, uint16_t offset) { + volatile union ice_rx_flex_desc *rxdp; struct ice_rx_queue *rxq = rx_queue; - volatile uint64_t *status; - uint64_t mask; uint32_t desc; if (unlikely(offset >= rxq->nb_rx_desc)) @@ -1509,10 +1838,9 @@ ice_rx_descriptor_status(void *rx_queue, uint16_t offset) if (desc >= rxq->nb_rx_desc) desc -= rxq->nb_rx_desc; - status = &rxq->rx_ring[desc].wb.qword1.status_error_len; - mask = rte_cpu_to_le_64((1ULL << ICE_RX_DESC_STATUS_DD_S) << - ICE_RXD_QW1_STATUS_S); - if (*status & mask) + rxdp = &rxq->rx_ring[desc]; + if (rte_le_to_cpu_16(rxdp->wb.status_error0) & + (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)) return RTE_ETH_RX_DESC_DONE; return RTE_ETH_RX_DESC_AVAIL; @@ -1591,15 +1919,137 @@ ice_free_queues(struct rte_eth_dev *dev) dev->data->nb_tx_queues = 0; } +#define ICE_FDIR_NUM_TX_DESC ICE_MIN_RING_DESC +#define ICE_FDIR_NUM_RX_DESC ICE_MIN_RING_DESC + +int +ice_fdir_setup_tx_resources(struct ice_pf *pf) +{ + struct ice_tx_queue *txq; + const struct rte_memzone *tz = NULL; + uint32_t ring_size; + struct rte_eth_dev *dev; + + if (!pf) { + PMD_DRV_LOG(ERR, "PF is not available"); + return -EINVAL; + } + + dev = pf->adapter->eth_dev; + + /* Allocate the TX queue data structure. */ + txq = rte_zmalloc_socket("ice fdir tx queue", + sizeof(struct ice_tx_queue), + RTE_CACHE_LINE_SIZE, + SOCKET_ID_ANY); + if (!txq) { + PMD_DRV_LOG(ERR, "Failed to allocate memory for " + "tx queue structure."); + return -ENOMEM; + } + + /* Allocate TX hardware ring descriptors. */ + ring_size = sizeof(struct ice_tx_desc) * ICE_FDIR_NUM_TX_DESC; + ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN); + + tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring", + ICE_FDIR_QUEUE_ID, ring_size, + ICE_RING_BASE_ALIGN, SOCKET_ID_ANY); + if (!tz) { + ice_tx_queue_release(txq); + PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX."); + return -ENOMEM; + } + + txq->nb_tx_desc = ICE_FDIR_NUM_TX_DESC; + txq->queue_id = ICE_FDIR_QUEUE_ID; + txq->reg_idx = pf->fdir.fdir_vsi->base_queue; + txq->vsi = pf->fdir.fdir_vsi; + + txq->tx_ring_dma = tz->iova; + txq->tx_ring = (struct ice_tx_desc *)tz->addr; + /* + * don't need to allocate software ring and reset for the fdir + * program queue just set the queue has been configured. + */ + txq->q_set = TRUE; + pf->fdir.txq = txq; + + txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs; + + return ICE_SUCCESS; +} + +int +ice_fdir_setup_rx_resources(struct ice_pf *pf) +{ + struct ice_rx_queue *rxq; + const struct rte_memzone *rz = NULL; + uint32_t ring_size; + struct rte_eth_dev *dev; + + if (!pf) { + PMD_DRV_LOG(ERR, "PF is not available"); + return -EINVAL; + } + + dev = pf->adapter->eth_dev; + + /* Allocate the RX queue data structure. */ + rxq = rte_zmalloc_socket("ice fdir rx queue", + sizeof(struct ice_rx_queue), + RTE_CACHE_LINE_SIZE, + SOCKET_ID_ANY); + if (!rxq) { + PMD_DRV_LOG(ERR, "Failed to allocate memory for " + "rx queue structure."); + return -ENOMEM; + } + + /* Allocate RX hardware ring descriptors. */ + ring_size = sizeof(union ice_rx_flex_desc) * ICE_FDIR_NUM_RX_DESC; + ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN); + + rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring", + ICE_FDIR_QUEUE_ID, ring_size, + ICE_RING_BASE_ALIGN, SOCKET_ID_ANY); + if (!rz) { + ice_rx_queue_release(rxq); + PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX."); + return -ENOMEM; + } + + rxq->nb_rx_desc = ICE_FDIR_NUM_RX_DESC; + rxq->queue_id = ICE_FDIR_QUEUE_ID; + rxq->reg_idx = pf->fdir.fdir_vsi->base_queue; + rxq->vsi = pf->fdir.fdir_vsi; + + rxq->rx_ring_dma = rz->iova; + memset(rz->addr, 0, ICE_FDIR_NUM_RX_DESC * + sizeof(union ice_rx_flex_desc)); + rxq->rx_ring = (union ice_rx_flex_desc *)rz->addr; + + /* + * Don't need to allocate software ring and reset for the fdir + * rx queue, just set the queue has been configured. + */ + rxq->q_set = TRUE; + pf->fdir.rxq = rxq; + + rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs; + + return ICE_SUCCESS; +} + uint16_t ice_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) { struct ice_rx_queue *rxq = rx_queue; - volatile union ice_rx_desc *rx_ring = rxq->rx_ring; - volatile union ice_rx_desc *rxdp; - union ice_rx_desc rxd; + volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring; + volatile union ice_rx_flex_desc *rxdp; + union ice_rx_flex_desc rxd; struct ice_rx_entry *sw_ring = rxq->sw_ring; struct ice_rx_entry *rxe; struct rte_mbuf *nmb; /* new allocated mbuf */ @@ -1608,21 +2058,18 @@ ice_recv_pkts(void *rx_queue, uint16_t nb_rx = 0; uint16_t nb_hold = 0; uint16_t rx_packet_len; - uint32_t rx_status; - uint64_t qword1; + uint16_t rx_stat_err0; uint64_t dma_addr; - uint64_t pkt_flags = 0; + uint64_t pkt_flags; uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl; struct rte_eth_dev *dev; while (nb_rx < nb_pkts) { rxdp = &rx_ring[rx_id]; - qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len); - rx_status = (qword1 & ICE_RXD_QW1_STATUS_M) >> - ICE_RXD_QW1_STATUS_S; + rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0); /* Check the DD bit first */ - if (!(rx_status & (1 << ICE_RX_DESC_STATUS_DD_S))) + if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S))) break; /* allocate mbuf */ @@ -1652,8 +2099,8 @@ ice_recv_pkts(void *rx_queue, rxdp->read.pkt_addr = dma_addr; /* calculate rx_packet_len of the received pkt */ - rx_packet_len = ((qword1 & ICE_RXD_QW1_LEN_PBUF_M) >> - ICE_RXD_QW1_LEN_PBUF_S) - rxq->crc_len; + rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) & + ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len; /* fill old mbuf with received descriptor: rxd */ rxm->data_off = RTE_PKTMBUF_HEADROOM; @@ -1663,15 +2110,11 @@ ice_recv_pkts(void *rx_queue, rxm->pkt_len = rx_packet_len; rxm->data_len = rx_packet_len; rxm->port = rxq->port_id; - ice_rxd_to_vlan_tci(rxm, rxdp); - rxm->packet_type = ptype_tbl[(uint8_t)((qword1 & - ICE_RXD_QW1_PTYPE_M) >> - ICE_RXD_QW1_PTYPE_S)]; - pkt_flags = ice_rxd_status_to_pkt_flags(qword1); - pkt_flags |= ice_rxd_error_to_pkt_flags(qword1); - if (pkt_flags & PKT_RX_RSS_HASH) - rxm->hash.rss = - rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss); + rxm->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M & + rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)]; + ice_rxd_to_vlan_tci(rxm, &rxd); + ice_rxd_to_pkt_fields(rxm, &rxd); + pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0); rxm->ol_flags |= pkt_flags; /* copy old mbuf to rx_pkts */ rx_pkts[nb_rx++] = rxm; @@ -1697,15 +2140,73 @@ ice_recv_pkts(void *rx_queue, return nb_rx; } +static inline void +ice_parse_tunneling_params(uint64_t ol_flags, + union ice_tx_offload tx_offload, + uint32_t *cd_tunneling) +{ + /* EIPT: External (outer) IP header type */ + if (ol_flags & PKT_TX_OUTER_IP_CKSUM) + *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4; + else if (ol_flags & PKT_TX_OUTER_IPV4) + *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4_NO_CSUM; + else if (ol_flags & PKT_TX_OUTER_IPV6) + *cd_tunneling |= ICE_TX_CTX_EIPT_IPV6; + + /* EIPLEN: External (outer) IP header length, in DWords */ + *cd_tunneling |= (tx_offload.outer_l3_len >> 2) << + ICE_TXD_CTX_QW0_EIPLEN_S; + + /* L4TUNT: L4 Tunneling Type */ + switch (ol_flags & PKT_TX_TUNNEL_MASK) { + case PKT_TX_TUNNEL_IPIP: + /* for non UDP / GRE tunneling, set to 00b */ + break; + case PKT_TX_TUNNEL_VXLAN: + case PKT_TX_TUNNEL_GTP: + case PKT_TX_TUNNEL_GENEVE: + *cd_tunneling |= ICE_TXD_CTX_UDP_TUNNELING; + break; + case PKT_TX_TUNNEL_GRE: + *cd_tunneling |= ICE_TXD_CTX_GRE_TUNNELING; + break; + default: + PMD_TX_LOG(ERR, "Tunnel type not supported"); + return; + } + + /* L4TUNLEN: L4 Tunneling Length, in Words + * + * We depend on app to set rte_mbuf.l2_len correctly. + * For IP in GRE it should be set to the length of the GRE + * header; + * For MAC in GRE or MAC in UDP it should be set to the length + * of the GRE or UDP headers plus the inner MAC up to including + * its last Ethertype. + * If MPLS labels exists, it should include them as well. + */ + *cd_tunneling |= (tx_offload.l2_len >> 1) << + ICE_TXD_CTX_QW0_NATLEN_S; + + if ((ol_flags & PKT_TX_OUTER_UDP_CKSUM) && + (ol_flags & PKT_TX_OUTER_IP_CKSUM) && + (*cd_tunneling & ICE_TXD_CTX_UDP_TUNNELING)) + *cd_tunneling |= ICE_TXD_CTX_QW0_L4T_CS_M; +} + static inline void ice_txd_enable_checksum(uint64_t ol_flags, uint32_t *td_cmd, uint32_t *td_offset, union ice_tx_offload tx_offload) { - /* L2 length must be set. */ - *td_offset |= (tx_offload.l2_len >> 1) << - ICE_TX_DESC_LEN_MACLEN_S; + /* Set MACLEN */ + if (ol_flags & PKT_TX_TUNNEL_MASK) + *td_offset |= (tx_offload.outer_l2_len >> 1) + << ICE_TX_DESC_LEN_MACLEN_S; + else + *td_offset |= (tx_offload.l2_len >> 1) + << ICE_TX_DESC_LEN_MACLEN_S; /* Enable L3 checksum offloads */ if (ol_flags & PKT_TX_IP_CKSUM) { @@ -1733,17 +2234,17 @@ ice_txd_enable_checksum(uint64_t ol_flags, switch (ol_flags & PKT_TX_L4_MASK) { case PKT_TX_TCP_CKSUM: *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP; - *td_offset |= (sizeof(struct tcp_hdr) >> 2) << + *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) << ICE_TX_DESC_LEN_L4_LEN_S; break; case PKT_TX_SCTP_CKSUM: *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_SCTP; - *td_offset |= (sizeof(struct sctp_hdr) >> 2) << + *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) << ICE_TX_DESC_LEN_L4_LEN_S; break; case PKT_TX_UDP_CKSUM: *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_UDP; - *td_offset |= (sizeof(struct udp_hdr) >> 2) << + *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) << ICE_TX_DESC_LEN_L4_LEN_S; break; default: @@ -1819,7 +2320,10 @@ ice_build_ctob(uint32_t td_cmd, static inline uint16_t ice_calc_context_desc(uint64_t flags) { - static uint64_t mask = PKT_TX_TCP_SEG | PKT_TX_QINQ; + static uint64_t mask = PKT_TX_TCP_SEG | + PKT_TX_QINQ | + PKT_TX_OUTER_IP_CKSUM | + PKT_TX_TUNNEL_MASK; return (flags & mask) ? 1 : 0; } @@ -1836,15 +2340,9 @@ ice_set_tso_ctx(struct rte_mbuf *mbuf, union ice_tx_offload tx_offload) return ctx_desc; } - /** - * in case of non tunneling packet, the outer_l2_len and - * outer_l3_len must be 0. - */ - hdr_len = tx_offload.outer_l2_len + - tx_offload.outer_l3_len + - tx_offload.l2_len + - tx_offload.l3_len + - tx_offload.l4_len; + hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len; + hdr_len += (mbuf->ol_flags & PKT_TX_TUNNEL_MASK) ? + tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0; cd_cmd = ICE_TX_CTX_DESC_TSO; cd_tso_len = mbuf->pkt_len - hdr_len; @@ -1865,6 +2363,7 @@ ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) struct ice_tx_entry *txe, *txn; struct rte_mbuf *tx_pkt; struct rte_mbuf *m_seg; + uint32_t cd_tunneling_params; uint16_t tx_id; uint16_t nb_tx; uint16_t nb_used; @@ -1935,6 +2434,12 @@ ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) td_tag = tx_pkt->vlan_tci; } + /* Fill in tunneling parameters if necessary */ + cd_tunneling_params = 0; + if (ol_flags & PKT_TX_TUNNEL_MASK) + ice_parse_tunneling_params(ol_flags, tx_offload, + &cd_tunneling_params); + /* Enable checksum offloading */ if (ol_flags & ICE_TX_CKSUM_OFFLOAD_MASK) { ice_txd_enable_checksum(ol_flags, &td_cmd, @@ -1960,6 +2465,9 @@ ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) cd_type_cmd_tso_mss |= ice_set_tso_ctx(tx_pkt, tx_offload); + ctx_txd->tunneling_params = + rte_cpu_to_le_32(cd_tunneling_params); + /* TX context descriptor based double VLAN insert */ if (ol_flags & PKT_TX_QINQ) { cd_l2tag2 = tx_pkt->vlan_tci_outer; @@ -2024,8 +2532,6 @@ ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) ICE_TXD_QW1_CMD_S); } end_of_tx: - rte_wmb(); - /* update Tail register */ ICE_PCI_REG_WRITE(txq->qtx_tail, tx_id); txq->tx_tail = tx_id; @@ -2181,7 +2687,6 @@ tx_xmit_pkts(struct ice_tx_queue *txq, txq->tx_tail = 0; /* Update the tx tail register */ - rte_wmb(); ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail); return nb_pkts; @@ -2219,6 +2724,52 @@ ice_set_rx_function(struct rte_eth_dev *dev) PMD_INIT_FUNC_TRACE(); struct ice_adapter *ad = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); +#ifdef RTE_ARCH_X86 + struct ice_rx_queue *rxq; + int i; + bool use_avx2 = false; + + if (rte_eal_process_type() == RTE_PROC_PRIMARY) { + if (!ice_rx_vec_dev_check(dev) && ad->rx_bulk_alloc_allowed) { + ad->rx_vec_allowed = true; + for (i = 0; i < dev->data->nb_rx_queues; i++) { + rxq = dev->data->rx_queues[i]; + if (rxq && ice_rxq_vec_setup(rxq)) { + ad->rx_vec_allowed = false; + break; + } + } + + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) + use_avx2 = true; + + } else { + ad->rx_vec_allowed = false; + } + } + + if (ad->rx_vec_allowed) { + if (dev->data->scattered_rx) { + PMD_DRV_LOG(DEBUG, + "Using %sVector Scattered Rx (port %d).", + use_avx2 ? "avx2 " : "", + dev->data->port_id); + dev->rx_pkt_burst = use_avx2 ? + ice_recv_scattered_pkts_vec_avx2 : + ice_recv_scattered_pkts_vec; + } else { + PMD_DRV_LOG(DEBUG, "Using %sVector Rx (port %d).", + use_avx2 ? "avx2 " : "", + dev->data->port_id); + dev->rx_pkt_burst = use_avx2 ? + ice_recv_pkts_vec_avx2 : + ice_recv_pkts_vec; + } + return; + } + +#endif if (dev->data->scattered_rx) { /* Set the non-LRO scattered function */ @@ -2242,6 +2793,60 @@ ice_set_rx_function(struct rte_eth_dev *dev) } } +int +ice_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id, + struct rte_eth_burst_mode *mode) +{ + eth_rx_burst_t pkt_burst = dev->rx_pkt_burst; + uint64_t options; + + if (pkt_burst == ice_recv_scattered_pkts) + options = RTE_ETH_BURST_SCALAR | RTE_ETH_BURST_SCATTERED; + else if (pkt_burst == ice_recv_pkts_bulk_alloc) + options = RTE_ETH_BURST_SCALAR | RTE_ETH_BURST_BULK_ALLOC; + else if (pkt_burst == ice_recv_pkts) + options = RTE_ETH_BURST_SCALAR; +#ifdef RTE_ARCH_X86 + else if (pkt_burst == ice_recv_scattered_pkts_vec_avx2) + options = RTE_ETH_BURST_VECTOR | RTE_ETH_BURST_AVX2 | + RTE_ETH_BURST_SCATTERED; + else if (pkt_burst == ice_recv_pkts_vec_avx2) + options = RTE_ETH_BURST_VECTOR | RTE_ETH_BURST_AVX2; + else if (pkt_burst == ice_recv_scattered_pkts_vec) + options = RTE_ETH_BURST_VECTOR | RTE_ETH_BURST_SSE | + RTE_ETH_BURST_SCATTERED; + else if (pkt_burst == ice_recv_pkts_vec) + options = RTE_ETH_BURST_VECTOR | RTE_ETH_BURST_SSE; +#endif + else + options = 0; + + mode->options = options; + + return options != 0 ? 0 : -EINVAL; +} + +void __attribute__((cold)) +ice_set_tx_function_flag(struct rte_eth_dev *dev, struct ice_tx_queue *txq) +{ + struct ice_adapter *ad = + ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); + + /* Use a simple Tx queue if possible (only fast free is allowed) */ + ad->tx_simple_allowed = + (txq->offloads == + (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) && + txq->tx_rs_thresh >= ICE_TX_MAX_BURST); + + if (ad->tx_simple_allowed) + PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.", + txq->queue_id); + else + PMD_INIT_LOG(DEBUG, + "Simple Tx can NOT be enabled on Tx queue %u.", + txq->queue_id); +} + /********************************************************************* * * TX prep functions @@ -2270,20 +2875,20 @@ ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts, /** * MSS outside the range are considered malicious */ - rte_errno = -EINVAL; + rte_errno = EINVAL; return i; } #ifdef RTE_LIBRTE_ETHDEV_DEBUG ret = rte_validate_tx_offload(m); if (ret != 0) { - rte_errno = ret; + rte_errno = -ret; return i; } #endif ret = rte_net_intel_cksum_prepare(m); if (ret != 0) { - rte_errno = ret; + rte_errno = -ret; return i; } } @@ -2295,6 +2900,43 @@ ice_set_tx_function(struct rte_eth_dev *dev) { struct ice_adapter *ad = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); +#ifdef RTE_ARCH_X86 + struct ice_tx_queue *txq; + int i; + bool use_avx2 = false; + + if (rte_eal_process_type() == RTE_PROC_PRIMARY) { + if (!ice_tx_vec_dev_check(dev)) { + ad->tx_vec_allowed = true; + for (i = 0; i < dev->data->nb_tx_queues; i++) { + txq = dev->data->tx_queues[i]; + if (txq && ice_txq_vec_setup(txq)) { + ad->tx_vec_allowed = false; + break; + } + } + + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) + use_avx2 = true; + + } else { + ad->tx_vec_allowed = false; + } + } + + if (ad->tx_vec_allowed) { + PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).", + use_avx2 ? "avx2 " : "", + dev->data->port_id); + dev->tx_pkt_burst = use_avx2 ? + ice_xmit_pkts_vec_avx2 : + ice_xmit_pkts_vec; + dev->tx_pkt_prepare = NULL; + + return; + } +#endif if (ad->tx_simple_allowed) { PMD_INIT_LOG(DEBUG, "Simple tx finally be used."); @@ -2307,6 +2949,31 @@ ice_set_tx_function(struct rte_eth_dev *dev) } } +int +ice_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id, + struct rte_eth_burst_mode *mode) +{ + eth_tx_burst_t pkt_burst = dev->tx_pkt_burst; + uint64_t options; + + if (pkt_burst == ice_xmit_pkts_simple) + options = RTE_ETH_BURST_SCALAR | RTE_ETH_BURST_SIMPLE; + else if (pkt_burst == ice_xmit_pkts) + options = RTE_ETH_BURST_SCALAR; +#ifdef RTE_ARCH_X86 + else if (pkt_burst == ice_xmit_pkts_vec_avx2) + options = RTE_ETH_BURST_VECTOR | RTE_ETH_BURST_AVX2; + else if (pkt_burst == ice_xmit_pkts_vec) + options = RTE_ETH_BURST_VECTOR | RTE_ETH_BURST_SSE; +#endif + else + options = 0; + + mode->options = options; + + return options != 0 ? 0 : -EINVAL; +} + /* For each value it means, datasheet of hardware can tell more details * * @note: fix ice_dev_supported_ptypes_get() if any change here. @@ -2871,3 +3538,49 @@ ice_set_default_ptype_table(struct rte_eth_dev *dev) for (i = 0; i < ICE_MAX_PKT_TYPE; i++) ad->ptype_tbl[i] = ice_get_default_pkt_type(i); } + +#define ICE_FDIR_MAX_WAIT_US 10000 + +int +ice_fdir_programming(struct ice_pf *pf, struct ice_fltr_desc *fdir_desc) +{ + struct ice_tx_queue *txq = pf->fdir.txq; + volatile struct ice_fltr_desc *fdirdp; + volatile struct ice_tx_desc *txdp; + uint32_t td_cmd; + uint16_t i; + + fdirdp = (volatile struct ice_fltr_desc *) + (&txq->tx_ring[txq->tx_tail]); + fdirdp->qidx_compq_space_stat = fdir_desc->qidx_compq_space_stat; + fdirdp->dtype_cmd_vsi_fdid = fdir_desc->dtype_cmd_vsi_fdid; + + txdp = &txq->tx_ring[txq->tx_tail + 1]; + txdp->buf_addr = rte_cpu_to_le_64(pf->fdir.dma_addr); + td_cmd = ICE_TX_DESC_CMD_EOP | + ICE_TX_DESC_CMD_RS | + ICE_TX_DESC_CMD_DUMMY; + + txdp->cmd_type_offset_bsz = + ice_build_ctob(td_cmd, 0, ICE_FDIR_PKT_LEN, 0); + + txq->tx_tail += 2; + if (txq->tx_tail >= txq->nb_tx_desc) + txq->tx_tail = 0; + /* Update the tx tail register */ + ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail); + for (i = 0; i < ICE_FDIR_MAX_WAIT_US; i++) { + if ((txdp->cmd_type_offset_bsz & + rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) == + rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE)) + break; + rte_delay_us(1); + } + if (i >= ICE_FDIR_MAX_WAIT_US) { + PMD_DRV_LOG(ERR, + "Failed to program FDIR filter: time out to get DD on tx queue."); + return -ETIMEDOUT; + } + + return 0; +}