X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fionic%2Fionic_lif.c;h=28ae9dc8a971fea3494093f96312ce887f234eb2;hb=cb71192486c34eada5b65c6c46d32afd05cc091b;hp=1214ebf93b831248c5cda929e86ab1a1bbf5ef8c;hpb=54fe083f534ab4f8633660421aa403ee206b703f;p=dpdk.git

diff --git a/drivers/net/ionic/ionic_lif.c b/drivers/net/ionic/ionic_lif.c
index 1214ebf93b..28ae9dc8a9 100644
--- a/drivers/net/ionic/ionic_lif.c
+++ b/drivers/net/ionic/ionic_lif.c
@@ -10,6 +10,7 @@
 #include "ionic_lif.h"
 #include "ionic_ethdev.h"
 #include "ionic_rx_filter.h"
+#include "ionic_rxtx.h"
 
 static int ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr);
 static int ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr);
@@ -76,11 +77,161 @@ void
 ionic_lif_reset(struct ionic_lif *lif)
 {
 	struct ionic_dev *idev = &lif->adapter->idev;
+	int err;
 
 	IONIC_PRINT_CALL();
 
 	ionic_dev_cmd_lif_reset(idev, lif->index);
-	ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
+	err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
+	if (err)
+		IONIC_PRINT(WARNING, "Failed to reset %s", lif->name);
+}
+
+static void
+ionic_lif_get_abs_stats(const struct ionic_lif *lif, struct rte_eth_stats *stats)
+{
+	struct ionic_lif_stats *ls = &lif->info->stats;
+	uint32_t i;
+	uint32_t num_rx_q_counters = RTE_MIN(lif->nrxqcqs, (uint32_t)
+			RTE_ETHDEV_QUEUE_STAT_CNTRS);
+	uint32_t num_tx_q_counters = RTE_MIN(lif->ntxqcqs, (uint32_t)
+			RTE_ETHDEV_QUEUE_STAT_CNTRS);
+
+	memset(stats, 0, sizeof(*stats));
+
+	if (ls == NULL) {
+		IONIC_PRINT(DEBUG, "Stats on port %u not yet initialized",
+			lif->port_id);
+		return;
+	}
+
+	/* RX */
+
+	stats->ipackets = ls->rx_ucast_packets +
+		ls->rx_mcast_packets +
+		ls->rx_bcast_packets;
+
+	stats->ibytes = ls->rx_ucast_bytes +
+		ls->rx_mcast_bytes +
+		ls->rx_bcast_bytes;
+
+	for (i = 0; i < lif->nrxqcqs; i++) {
+		struct ionic_rx_stats *rx_stats = &lif->rxqcqs[i]->stats.rx;
+		stats->imissed +=
+			rx_stats->no_cb_arg +
+			rx_stats->bad_cq_status +
+			rx_stats->no_room +
+			rx_stats->bad_len;
+	}
+
+	stats->imissed +=
+		ls->rx_ucast_drop_packets +
+		ls->rx_mcast_drop_packets +
+		ls->rx_bcast_drop_packets;
+
+	stats->imissed +=
+		ls->rx_queue_empty +
+		ls->rx_dma_error +
+		ls->rx_queue_disabled +
+		ls->rx_desc_fetch_error +
+		ls->rx_desc_data_error;
+
+	for (i = 0; i < num_rx_q_counters; i++) {
+		struct ionic_rx_stats *rx_stats = &lif->rxqcqs[i]->stats.rx;
+		stats->q_ipackets[i] = rx_stats->packets;
+		stats->q_ibytes[i] = rx_stats->bytes;
+		stats->q_errors[i] =
+			rx_stats->no_cb_arg +
+			rx_stats->bad_cq_status +
+			rx_stats->no_room +
+			rx_stats->bad_len;
+	}
+
+	/* TX */
+
+	stats->opackets = ls->tx_ucast_packets +
+		ls->tx_mcast_packets +
+		ls->tx_bcast_packets;
+
+	stats->obytes = ls->tx_ucast_bytes +
+		ls->tx_mcast_bytes +
+		ls->tx_bcast_bytes;
+
+	for (i = 0; i < lif->ntxqcqs; i++) {
+		struct ionic_tx_stats *tx_stats = &lif->txqcqs[i]->stats.tx;
+		stats->oerrors += tx_stats->drop;
+	}
+
+	stats->oerrors +=
+		ls->tx_ucast_drop_packets +
+		ls->tx_mcast_drop_packets +
+		ls->tx_bcast_drop_packets;
+
+	stats->oerrors +=
+		ls->tx_dma_error +
+		ls->tx_queue_disabled +
+		ls->tx_desc_fetch_error +
+		ls->tx_desc_data_error;
+
+	for (i = 0; i < num_tx_q_counters; i++) {
+		struct ionic_tx_stats *tx_stats = &lif->txqcqs[i]->stats.tx;
+		stats->q_opackets[i] = tx_stats->packets;
+		stats->q_obytes[i] = tx_stats->bytes;
+	}
+}
+
+void
+ionic_lif_get_stats(const struct ionic_lif *lif,
+		struct rte_eth_stats *stats)
+{
+	ionic_lif_get_abs_stats(lif, stats);
+
+	stats->ipackets  -= lif->stats_base.ipackets;
+	stats->opackets  -= lif->stats_base.opackets;
+	stats->ibytes    -= lif->stats_base.ibytes;
+	stats->obytes    -= lif->stats_base.obytes;
+	stats->imissed   -= lif->stats_base.imissed;
+	stats->ierrors   -= lif->stats_base.ierrors;
+	stats->oerrors   -= lif->stats_base.oerrors;
+	stats->rx_nombuf -= lif->stats_base.rx_nombuf;
+}
+
+void
+ionic_lif_reset_stats(struct ionic_lif *lif)
+{
+	uint32_t i;
+
+	for (i = 0; i < lif->nrxqcqs; i++) {
+		memset(&lif->rxqcqs[i]->stats.rx, 0,
+			sizeof(struct ionic_rx_stats));
+		memset(&lif->txqcqs[i]->stats.tx, 0,
+			sizeof(struct ionic_tx_stats));
+	}
+
+	ionic_lif_get_abs_stats(lif, &lif->stats_base);
+}
+
+void
+ionic_lif_get_hw_stats(struct ionic_lif *lif, struct ionic_lif_stats *stats)
+{
+	uint16_t i, count = sizeof(struct ionic_lif_stats) / sizeof(uint64_t);
+	uint64_t *stats64 = (uint64_t *)stats;
+	uint64_t *lif_stats64 = (uint64_t *)&lif->info->stats;
+	uint64_t *lif_stats64_base = (uint64_t *)&lif->lif_stats_base;
+
+	for (i = 0; i < count; i++)
+		stats64[i] = lif_stats64[i] - lif_stats64_base[i];
+}
+
+void
+ionic_lif_reset_hw_stats(struct ionic_lif *lif)
+{
+	uint16_t i, count = sizeof(struct ionic_lif_stats) / sizeof(uint64_t);
+	uint64_t *lif_stats64 = (uint64_t *)&lif->info->stats;
+	uint64_t *lif_stats64_base = (uint64_t *)&lif->lif_stats_base;
+
+	for (i = 0; i < count; i++)
+		lif_stats64_base[i] = lif_stats64[i];
 }
 
 static int
@@ -157,10 +308,11 @@ ionic_dev_add_mac(struct rte_eth_dev *eth_dev,
 }
 
 void
-ionic_dev_remove_mac(struct rte_eth_dev *eth_dev, uint32_t index __rte_unused)
+ionic_dev_remove_mac(struct rte_eth_dev *eth_dev, uint32_t index)
 {
 	struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
 	struct ionic_adapter *adapter = lif->adapter;
+	struct rte_ether_addr *mac_addr;
 
 	IONIC_PRINT_CALL();
 
@@ -171,11 +323,12 @@ ionic_dev_remove_mac(struct rte_eth_dev *eth_dev, uint32_t index __rte_unused)
 		return;
 	}
 
-	if (!rte_is_valid_assigned_ether_addr(&eth_dev->data->mac_addrs[index]))
+	mac_addr = &eth_dev->data->mac_addrs[index];
+
+	if (!rte_is_valid_assigned_ether_addr(mac_addr))
 		return;
 
-	ionic_lif_addr_del(lif, (const uint8_t *)
-		&eth_dev->data->mac_addrs[index]);
+	ionic_lif_addr_del(lif, (const uint8_t *)mac_addr);
 }
 
 int
@@ -388,8 +541,6 @@ ionic_lif_change_mtu(struct ionic_lif *lif, int new_mtu)
 	if (err)
 		return err;
 
-	lif->mtu = new_mtu;
-
 	return 0;
 }
 
@@ -403,7 +554,7 @@ ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr)
 	/*
 	 * Note: interrupt handler is called for index = 0 only
 	 * (we use interrupts for the notifyq only anyway,
-	 * which hash index = 0)
+	 * which has index = 0)
 	 */
 
 	for (index = 0; index < adapter->nintrs; index++)
@@ -435,7 +586,7 @@ ionic_qcq_alloc(struct ionic_lif *lif, uint8_t type,
 		uint32_t desc_size,
 		uint32_t cq_desc_size,
 		uint32_t sg_desc_size,
-		uint32_t pid, struct ionic_qcq **qcq)
+		struct ionic_qcq **qcq)
 {
 	struct ionic_dev *idev = &lif->adapter->idev;
 	struct ionic_qcq *new;
@@ -485,7 +636,7 @@ ionic_qcq_alloc(struct ionic_lif *lif, uint8_t type,
 	new->q.type = type;
 
 	err = ionic_q_init(lif, idev, &new->q, index, num_descs,
-		desc_size, sg_desc_size, pid);
+		desc_size, sg_desc_size);
 	if (err) {
 		IONIC_PRINT(ERR, "Queue initialization failed");
 		return err;
@@ -536,8 +687,8 @@ ionic_qcq_alloc(struct ionic_lif *lif, uint8_t type,
 		ionic_q_sg_map(&new->q, sg_base, sg_base_pa);
 	}
 
-	IONIC_PRINT(DEBUG, "Q-Base-PA = %ju CQ-Base-PA = %ju "
-		"SG-base-PA = %ju",
+	IONIC_PRINT(DEBUG, "Q-Base-PA = %#jx CQ-Base-PA = %#jx "
+		"SG-base-PA = %#jx",
 		q_base_pa, cq_base_pa, sg_base_pa);
 
 	ionic_q_map(&new->q, q_base, q_base_pa);
@@ -573,6 +724,50 @@ ionic_qcq_free(struct ionic_qcq *qcq)
 	rte_free(qcq);
 }
 
+int
+ionic_rx_qcq_alloc(struct ionic_lif *lif, uint32_t index, uint16_t nrxq_descs,
+		struct ionic_qcq **qcq)
+{
+	uint32_t flags;
+	int err = -ENOMEM;
+
+	flags = IONIC_QCQ_F_SG;
+	err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, index, "rx", flags,
+		nrxq_descs,
+		sizeof(struct ionic_rxq_desc),
+		sizeof(struct ionic_rxq_comp),
+		sizeof(struct ionic_rxq_sg_desc),
+		&lif->rxqcqs[index]);
+	if (err)
+		return err;
+
+	*qcq = lif->rxqcqs[index];
+
+	return 0;
+}
+
+int
+ionic_tx_qcq_alloc(struct ionic_lif *lif, uint32_t index, uint16_t ntxq_descs,
+		struct ionic_qcq **qcq)
+{
+	uint32_t flags;
+	int err = -ENOMEM;
+
+	flags = IONIC_QCQ_F_SG;
+	err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, index, "tx", flags,
+		ntxq_descs,
+		sizeof(struct ionic_txq_desc),
+		sizeof(struct ionic_txq_comp),
+		sizeof(struct ionic_txq_sg_desc),
+		&lif->txqcqs[index]);
+	if (err)
+		return err;
+
+	*qcq = lif->txqcqs[index];
+
+	return 0;
+}
+
 static int
 ionic_admin_qcq_alloc(struct ionic_lif *lif)
 {
@@ -585,7 +780,7 @@ ionic_admin_qcq_alloc(struct ionic_lif *lif)
 		sizeof(struct ionic_admin_cmd),
 		sizeof(struct ionic_admin_comp),
 		0,
-		lif->kern_pid, &lif->adminqcq);
+		&lif->adminqcq);
 	if (err)
 		return err;
 
@@ -606,7 +801,7 @@ ionic_notify_qcq_alloc(struct ionic_lif *lif)
 		sizeof(struct ionic_notifyq_cmd),
 		sizeof(union ionic_notifyq_comp),
 		0,
-		lif->kern_pid, &lif->notifyqcq);
+		&lif->notifyqcq);
 	if (err)
 		return err;
 
@@ -632,15 +827,19 @@ ionic_lif_alloc(struct ionic_lif *lif)
 	int dbpage_num;
 	int err;
 
-	snprintf(lif->name, sizeof(lif->name), "lif%u", lif->index);
+	/*
+	 * lif->name was zeroed on allocation.
+	 * Copy (sizeof() - 1) bytes to ensure that it is NULL terminated.
+	 */
+	memcpy(lif->name, lif->eth_dev->data->name, sizeof(lif->name) - 1);
+
+	IONIC_PRINT(DEBUG, "LIF: %s", lif->name);
 
 	IONIC_PRINT(DEBUG, "Allocating Lif Info");
 
 	rte_spinlock_init(&lif->adminq_lock);
 	rte_spinlock_init(&lif->adminq_service_lock);
 
-	lif->kern_pid = 0;
-
 	dbpage_num = ionic_db_page_num(lif, 0);
 
 	lif->kern_dbpage = ionic_bus_map_dbpage(adapter, dbpage_num);
@@ -649,6 +848,22 @@ ionic_lif_alloc(struct ionic_lif *lif)
 		return -ENOMEM;
 	}
 
+	lif->txqcqs = rte_zmalloc("ionic", sizeof(*lif->txqcqs) *
+		adapter->max_ntxqs_per_lif, 0);
+
+	if (!lif->txqcqs) {
+		IONIC_PRINT(ERR, "Cannot allocate tx queues array");
+		return -ENOMEM;
+	}
+
+	lif->rxqcqs = rte_zmalloc("ionic", sizeof(*lif->rxqcqs) *
+		adapter->max_nrxqs_per_lif, 0);
+
+	if (!lif->rxqcqs) {
+		IONIC_PRINT(ERR, "Cannot allocate rx queues array");
+		return -ENOMEM;
+	}
+
 	IONIC_PRINT(DEBUG, "Allocating Notify Queue");
 
 	err = ionic_notify_qcq_alloc(lif);
@@ -659,8 +874,6 @@ ionic_lif_alloc(struct ionic_lif *lif)
 
 	IONIC_PRINT(DEBUG, "Allocating Admin Queue");
 
-	IONIC_PRINT(DEBUG, "Allocating Admin Queue");
-
 	err = ionic_admin_qcq_alloc(lif);
 	if (err) {
 		IONIC_PRINT(ERR, "Cannot allocate admin queue");
@@ -698,12 +911,113 @@ ionic_lif_free(struct ionic_lif *lif)
 		lif->adminqcq = NULL;
 	}
 
+	if (lif->txqcqs) {
+		rte_free(lif->txqcqs);
+		lif->txqcqs = NULL;
+	}
+
+	if (lif->rxqcqs) {
+		rte_free(lif->rxqcqs);
+		lif->rxqcqs = NULL;
+	}
+
 	if (lif->info) {
 		rte_memzone_free(lif->info_z);
 		lif->info = NULL;
 	}
 }
 
+int
+ionic_lif_rss_config(struct ionic_lif *lif,
+		const uint16_t types, const uint8_t *key, const uint32_t *indir)
+{
+	struct ionic_admin_ctx ctx = {
+		.pending_work = true,
+		.cmd.lif_setattr = {
+			.opcode = IONIC_CMD_LIF_SETATTR,
+			.attr = IONIC_LIF_ATTR_RSS,
+			.rss.types = types,
+			.rss.addr = lif->rss_ind_tbl_pa,
+		},
+	};
+	unsigned int i;
+
+	IONIC_PRINT_CALL();
+
+	lif->rss_types = types;
+
+	if (key)
+		memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE);
+
+	if (indir)
+		for (i = 0; i < lif->adapter->ident.lif.eth.rss_ind_tbl_sz; i++)
+			lif->rss_ind_tbl[i] = indir[i];
+
+	memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key,
+	       IONIC_RSS_HASH_KEY_SIZE);
+
+	return ionic_adminq_post_wait(lif, &ctx);
+}
+
+static int
+ionic_lif_rss_setup(struct ionic_lif *lif)
+{
+	size_t tbl_size = sizeof(*lif->rss_ind_tbl) *
+		lif->adapter->ident.lif.eth.rss_ind_tbl_sz;
+	static const uint8_t toeplitz_symmetric_key[] = {
+		0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
+		0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
+		0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
+		0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
+		0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
+	};
+	uint32_t socket_id = rte_socket_id();
+	uint32_t i;
+	int err;
+
+	IONIC_PRINT_CALL();
+
+	lif->rss_ind_tbl_z = rte_eth_dma_zone_reserve(lif->eth_dev,
+		"rss_ind_tbl",
+		0 /* queue_idx*/, tbl_size, IONIC_ALIGN, socket_id);
+
+	if (!lif->rss_ind_tbl_z) {
+		IONIC_PRINT(ERR, "OOM");
+		return -ENOMEM;
+	}
+
+	lif->rss_ind_tbl = lif->rss_ind_tbl_z->addr;
+	lif->rss_ind_tbl_pa = lif->rss_ind_tbl_z->iova;
+
+	/* Fill indirection table with 'default' values */
+	for (i = 0; i < lif->adapter->ident.lif.eth.rss_ind_tbl_sz; i++)
+		lif->rss_ind_tbl[i] = i % lif->nrxqcqs;
+
+	err = ionic_lif_rss_config(lif, IONIC_RSS_OFFLOAD_ALL,
+		toeplitz_symmetric_key, NULL);
+	if (err)
+		return err;
+
+	return 0;
+}
+
+static void
+ionic_lif_rss_teardown(struct ionic_lif *lif)
+{
+	if (!lif->rss_ind_tbl)
+		return;
+
+	if (lif->rss_ind_tbl_z) {
+		/* Disable RSS on the NIC */
+		ionic_lif_rss_config(lif, 0x0, NULL, NULL);
+
+		lif->rss_ind_tbl = NULL;
+		lif->rss_ind_tbl_pa = 0;
+		rte_memzone_free(lif->rss_ind_tbl_z);
+		lif->rss_ind_tbl_z = NULL;
+	}
+}
+
 static void
 ionic_lif_qcq_deinit(struct ionic_lif *lif, struct ionic_qcq *qcq)
 {
@@ -719,6 +1033,18 @@ ionic_lif_qcq_deinit(struct ionic_lif *lif, struct ionic_qcq *qcq)
 	qcq->flags &= ~IONIC_QCQ_F_INITED;
 }
 
+void
+ionic_lif_txq_deinit(struct ionic_qcq *qcq)
+{
+	ionic_lif_qcq_deinit(qcq->lif, qcq);
+}
+
+void
+ionic_lif_rxq_deinit(struct ionic_qcq *qcq)
+{
+	ionic_lif_qcq_deinit(qcq->lif, qcq);
+}
+
 bool
 ionic_adminq_service(struct ionic_cq *cq, uint32_t cq_desc_index,
 		void *cb_arg __rte_unused)
@@ -890,19 +1216,18 @@ ionic_lif_notifyq_init(struct ionic_lif *lif)
 			.index = q->index,
 			.flags = (IONIC_QINIT_F_IRQ | IONIC_QINIT_F_ENA),
 			.intr_index = qcq->intr.index,
-			.pid = q->pid,
 			.ring_size = rte_log2_u32(q->num_descs),
 			.ring_base = q->base_pa,
 		}
 	};
 
-	IONIC_PRINT(DEBUG, "notifyq_init.pid %d", ctx.cmd.q_init.pid);
 	IONIC_PRINT(DEBUG, "notifyq_init.index %d",
 		ctx.cmd.q_init.index);
 	IONIC_PRINT(DEBUG, "notifyq_init.ring_base 0x%" PRIx64 "",
 		ctx.cmd.q_init.ring_base);
 	IONIC_PRINT(DEBUG, "notifyq_init.ring_size %d",
 		ctx.cmd.q_init.ring_size);
+	IONIC_PRINT(DEBUG, "notifyq_init.ver %u", ctx.cmd.q_init.ver);
 
 	err = ionic_adminq_post_wait(lif, &ctx);
 	if (err)
@@ -984,6 +1309,100 @@ ionic_lif_set_features(struct ionic_lif *lif)
 	return 0;
 }
 
+int
+ionic_lif_txq_init(struct ionic_qcq *qcq)
+{
+	struct ionic_queue *q = &qcq->q;
+	struct ionic_lif *lif = qcq->lif;
+	struct ionic_cq *cq = &qcq->cq;
+	struct ionic_admin_ctx ctx = {
+		.pending_work = true,
+		.cmd.q_init = {
+			.opcode = IONIC_CMD_Q_INIT,
+			.lif_index = lif->index,
+			.type = q->type,
+			.index = q->index,
+			.flags = IONIC_QINIT_F_SG,
+			.intr_index = cq->bound_intr->index,
+			.ring_size = rte_log2_u32(q->num_descs),
+			.ring_base = q->base_pa,
+			.cq_ring_base = cq->base_pa,
+			.sg_ring_base = q->sg_base_pa,
+		},
+	};
+	int err;
+
+	IONIC_PRINT(DEBUG, "txq_init.index %d", ctx.cmd.q_init.index);
+	IONIC_PRINT(DEBUG, "txq_init.ring_base 0x%" PRIx64 "",
+		ctx.cmd.q_init.ring_base);
+	IONIC_PRINT(DEBUG, "txq_init.ring_size %d",
+		ctx.cmd.q_init.ring_size);
+	IONIC_PRINT(DEBUG, "txq_init.ver %u", ctx.cmd.q_init.ver);
+
+	err = ionic_adminq_post_wait(qcq->lif, &ctx);
+	if (err)
+		return err;
+
+	q->hw_type = ctx.comp.q_init.hw_type;
+	q->hw_index = ctx.comp.q_init.hw_index;
+	q->db = ionic_db_map(lif, q);
+
+	IONIC_PRINT(DEBUG, "txq->hw_type %d", q->hw_type);
+	IONIC_PRINT(DEBUG, "txq->hw_index %d", q->hw_index);
+	IONIC_PRINT(DEBUG, "txq->db %p", q->db);
+
+	qcq->flags |= IONIC_QCQ_F_INITED;
+
+	return 0;
+}
+
+int
+ionic_lif_rxq_init(struct ionic_qcq *qcq)
+{
+	struct ionic_queue *q = &qcq->q;
+	struct ionic_lif *lif = qcq->lif;
+	struct ionic_cq *cq = &qcq->cq;
+	struct ionic_admin_ctx ctx = {
+		.pending_work = true,
+		.cmd.q_init = {
+			.opcode = IONIC_CMD_Q_INIT,
+			.lif_index = lif->index,
+			.type = q->type,
+			.index = q->index,
+			.flags = IONIC_QINIT_F_SG,
+			.intr_index = cq->bound_intr->index,
+			.ring_size = rte_log2_u32(q->num_descs),
+			.ring_base = q->base_pa,
+			.cq_ring_base = cq->base_pa,
+			.sg_ring_base = q->sg_base_pa,
+		},
+	};
+	int err;
+
+	IONIC_PRINT(DEBUG, "rxq_init.index %d", ctx.cmd.q_init.index);
+	IONIC_PRINT(DEBUG, "rxq_init.ring_base 0x%" PRIx64 "",
+		ctx.cmd.q_init.ring_base);
+	IONIC_PRINT(DEBUG, "rxq_init.ring_size %d",
+		ctx.cmd.q_init.ring_size);
+	IONIC_PRINT(DEBUG, "rxq_init.ver %u", ctx.cmd.q_init.ver);
+
+	err = ionic_adminq_post_wait(qcq->lif, &ctx);
+	if (err)
+		return err;
+
+	q->hw_type = ctx.comp.q_init.hw_type;
+	q->hw_index = ctx.comp.q_init.hw_index;
+	q->db = ionic_db_map(lif, q);
+
+	qcq->flags |= IONIC_QCQ_F_INITED;
+
+	IONIC_PRINT(DEBUG, "rxq->hw_type %d", q->hw_type);
+	IONIC_PRINT(DEBUG, "rxq->hw_index %d", q->hw_index);
+	IONIC_PRINT(DEBUG, "rxq->db %p", q->db);
+
+	return 0;
+}
+
 static int
 ionic_station_set(struct ionic_lif *lif)
 {
@@ -1036,8 +1455,8 @@ ionic_lif_set_name(struct ionic_lif *lif)
 		},
 	};
 
-	snprintf(ctx.cmd.lif_setattr.name, sizeof(ctx.cmd.lif_setattr.name),
-		"%d", lif->port_id);
+	memcpy(ctx.cmd.lif_setattr.name, lif->name,
+		sizeof(ctx.cmd.lif_setattr.name) - 1);
 
 	ionic_adminq_post_wait(lif, &ctx);
 }
@@ -1049,6 +1468,8 @@ ionic_lif_init(struct ionic_lif *lif)
 	struct ionic_q_init_comp comp;
 	int err;
 
+	memset(&lif->stats_base, 0, sizeof(lif->stats_base));
+
 	ionic_dev_cmd_lif_init(idev, lif->index, lif->info_pa);
 	err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
 	ionic_dev_cmd_comp(idev, &comp);
@@ -1065,7 +1486,18 @@ ionic_lif_init(struct ionic_lif *lif)
 	if (err)
 		goto err_out_adminq_deinit;
 
-	lif->features = 0;
+	lif->features =
+		  IONIC_ETH_HW_VLAN_TX_TAG
+		| IONIC_ETH_HW_VLAN_RX_STRIP
+		| IONIC_ETH_HW_VLAN_RX_FILTER
+		| IONIC_ETH_HW_RX_HASH
+		| IONIC_ETH_HW_TX_SG
+		| IONIC_ETH_HW_RX_SG
+		| IONIC_ETH_HW_TX_CSUM
+		| IONIC_ETH_HW_RX_CSUM
+		| IONIC_ETH_HW_TSO
+		| IONIC_ETH_HW_TSO_IPV6
+		| IONIC_ETH_HW_TSO_ECN;
 
 	err = ionic_lif_set_features(lif);
 	if (err)
@@ -1104,6 +1536,7 @@ ionic_lif_deinit(struct ionic_lif *lif)
 		return;
 
 	ionic_rx_filters_deinit(lif);
+	ionic_lif_rss_teardown(lif);
 	ionic_lif_qcq_deinit(lif, lif->notifyqcq);
 	ionic_lif_qcq_deinit(lif, lif->adminqcq);
 
@@ -1113,8 +1546,28 @@ ionic_lif_deinit(struct ionic_lif *lif)
 int
 ionic_lif_configure(struct ionic_lif *lif)
 {
+	struct ionic_identity *ident = &lif->adapter->ident;
+	uint32_t ntxqs_per_lif =
+		ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ];
+	uint32_t nrxqs_per_lif =
+		ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ];
+	uint32_t nrxqs = lif->eth_dev->data->nb_rx_queues;
+	uint32_t ntxqs = lif->eth_dev->data->nb_tx_queues;
+
 	lif->port_id = lif->eth_dev->data->port_id;
 
+	IONIC_PRINT(DEBUG, "Configuring LIF on port %u",
+		lif->port_id);
+
+	if (nrxqs > 0)
+		nrxqs_per_lif = RTE_MIN(nrxqs_per_lif, nrxqs);
+
+	if (ntxqs > 0)
+		ntxqs_per_lif = RTE_MIN(ntxqs_per_lif, ntxqs);
+
+	lif->nrxqcqs = nrxqs_per_lif;
+	lif->ntxqcqs = ntxqs_per_lif;
+
 	return 0;
 }
 
@@ -1122,6 +1575,15 @@ int
 ionic_lif_start(struct ionic_lif *lif)
 {
 	uint32_t rx_mode = 0;
+	uint32_t i;
+	int err;
+
+	IONIC_PRINT(DEBUG, "Setting RSS configuration on port %u",
+		lif->port_id);
+
+	err = ionic_lif_rss_setup(lif);
+	if (err)
+		return err;
 
 	IONIC_PRINT(DEBUG, "Setting RX mode on port %u",
 		lif->port_id);
@@ -1134,6 +1596,30 @@ ionic_lif_start(struct ionic_lif *lif)
 
 	ionic_set_rx_mode(lif, rx_mode);
 
+	IONIC_PRINT(DEBUG, "Starting %u RX queues and %u TX queues "
+		"on port %u",
+		lif->nrxqcqs, lif->ntxqcqs, lif->port_id);
+
+	for (i = 0; i < lif->nrxqcqs; i++) {
+		struct ionic_qcq *rxq = lif->rxqcqs[i];
+		if (!(rxq->flags & IONIC_QCQ_F_DEFERRED)) {
+			err = ionic_dev_rx_queue_start(lif->eth_dev, i);
+
+			if (err)
+				return err;
+		}
+	}
+
+	for (i = 0; i < lif->ntxqcqs; i++) {
+		struct ionic_qcq *txq = lif->txqcqs[i];
+		if (!(txq->flags & IONIC_QCQ_F_DEFERRED)) {
+			err = ionic_dev_tx_queue_start(lif->eth_dev, i);
+
+			if (err)
+				return err;
+		}
+	}
+
 	ionic_link_status_check(lif);
 
 	/* Carrier ON here */
@@ -1201,7 +1687,8 @@ ionic_lifs_size(struct ionic_adapter *adapter)
 	nintrs = nlifs * 1 /* notifyq */;
 
 	if (nintrs > dev_nintrs) {
-		IONIC_PRINT(ERR, "At most %d intr queues supported, minimum required is %u",
+		IONIC_PRINT(ERR,
+			"At most %d intr supported, minimum req'd is %u",
 			dev_nintrs, nintrs);
 		return -ENOSPC;
 	}